CN1163956C - Improved method for forming multiple interconnection line and internal metal dielectric connection structure - Google Patents
Improved method for forming multiple interconnection line and internal metal dielectric connection structure Download PDFInfo
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- CN1163956C CN1163956C CNB001318845A CN00131884A CN1163956C CN 1163956 C CN1163956 C CN 1163956C CN B001318845 A CNB001318845 A CN B001318845A CN 00131884 A CN00131884 A CN 00131884A CN 1163956 C CN1163956 C CN 1163956C
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
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- 229910000838 Al alloy Inorganic materials 0.000 claims description 5
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 229920000620 organic polymer Polymers 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
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- 230000015572 biosynthetic process Effects 0.000 claims description 4
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- 239000000126 substance Substances 0.000 claims description 4
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- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 14
- 239000000377 silicon dioxide Substances 0.000 claims 6
- 235000012239 silicon dioxide Nutrition 0.000 claims 4
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 125000003118 aryl group Chemical group 0.000 claims 1
- 125000001183 hydrocarbyl group Chemical group 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 abstract 1
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
一种多重内连线与低K值内金属介电质的装构键结的改良方法。此方法的特徵系于一内连线层上的每一对内连线间形成一渠沟，然后以一氧化介电质填充此一渠沟，以取代未形成渠沟之前，填充于此区域的K值小于3的低K值内金属介电质。此氧化介电质的K值大于此低K值内金属介电质的K值，此氧化介电质有足够的硬度可以承受装构键结下压的力量。因此，可提高多重内连线与低K值内金属介电质之间的结合强度。
An improved method for structural bonding of multiple interconnects to low-K intermetallic dielectrics. The method is characterized in that a trench is formed between each pair of interconnects on an interconnect layer, and then the trench is filled with an oxide dielectric to replace the low-K intermetallic dielectric with a K value less than 3 that was filled in the area before the trench was formed. The K value of the oxide dielectric is greater than the K value of the low-K intermetallic dielectric, and the oxide dielectric has sufficient hardness to withstand the force of structural bonding. Therefore, the bonding strength between the multiple interconnects and the low-K intermetallic dielectric can be improved.
Description
The present invention relates to a kind of modification method that forms the joint construction of metal and dielectric matter in multiple internal connecting lines and the low K value, particularly about a kind of method of improving the bond structure that metal and dielectric matter is constituted in multiple internal connecting lines and the low K value, this bond structure is especially with the manufacturing of dual-inlaid manufacture process.
The integrated circuit system use multiplex conductor structure of many high integration connects the interior zone of each device and the various devices on the connection integrated circuit.When forming this multiplex conductor structure, be to form one first or one base conductor layer or intraconnections structure earlier traditionally, form one second conductor layer or intraconnections afterwards and construct therewith that conductor layer No.1 contacts.First internal connecting layer can contact with an intrabasement doped region of integrated circuit (IC) apparatus.Perhaps, first internal connecting layer can form polysilicon or plain conductor, and contacts with one or more device in substrate or in it.On the typical case, one or more intraconnections series of strata are formed between first lead or internal connecting layer and other device of integrated circuit, or and other structure of integrated circuit outside between.
Dual-inlaid manufacture process (dual damascene process) is a kind of advanced method of making intraconnections on integrated circuit.By during the dual-inlaid manufacture process, use chemical and mechanical grinding method, can select more metal, as aluminium, copper and aluminium alloy, and be not subject to traditional etch process.Can select more metal is favourable for the requirement of low resistance intraconnections, and for preventing that electromigration (electromigration) from also being favourable.
Yet the plant bulk on the wafer more and more hour, and intraconnections spacing density is promptly more and more high.For general dielectric medium, for example a silicon layer because it has high-k, causes higher RC to postpone easily.Therefore, this kind dielectric medium promptly is unsuitable for the interior metal and dielectric matter (inter-metaldielectric) as high density integrated circuit.Use low-K dielectric layer to have reduction intraconnections parasitic capacitance, reduce the advantage that RC postpones or reduce cross-talk (cross talk) phenomenon between metal interconnecting, therefore can improve service speed.
Only shown in first figure, it is a kind of bond structure (bondstructure) with the manufacturing of dual-inlaid manufacture process, the copper interconnects layer that this bond structure system is replaced by plural layer reaches the interlayer contact hole layer (via layer) of filling with copper and is formed, one low K value dielectric medium is to insert in this bond structure, as an interior metal and dielectric matter layer.This bond structure faces the problem of bond (bondability) between copper interconnects and the interior metal and dielectric matter of low K value.Low K value dielectric medium, as low K value spin-on glasses (low K spin-on glass) is too soft in itself, press down strength and can't resist the syndeton (package bonding) that forms this bond structure, and bad conjugation (poor adhesion) in fact also can't bear the pulling force that comes self-chambering structure board during the formation syndeton between copper and the low K value spin-coating glass.
In view of the above, demand developing a kind of modification method that forms the syndeton between the metal and dielectric matter in multiple internal connecting lines and the low K value urgently.
Main purpose of the present invention is that a kind of modification method that forms the syndeton between the metal and dielectric matter in multiple internal connecting lines and the low K value is provided, wherein between each of an internal connecting layer is to intraconnections, form a trench (trench), fill this trench with an oxidation dielectric medium then, and replace do not form trench before, be filled in the interior metal and dielectric matter of low K value in this zone.This oxidation dielectric medium has enough hardness can bear the strength that presses down when this forms syndeton, therefore can improve to combine confidence level (reliability ofbondability) between intraconnections and the interior metal and dielectric matter of low K value.
Another object of the present invention system provides a kind of modification method that forms the syndeton between multiple internal connecting lines and the interior metal and dielectric matter of low K value, and wherein oxidation dielectric medium system is in order to metal and dielectric matter in the low K value that replaces part in the multiple internal connecting lines structure.By this, this oxidation dielectric medium can improve the conjugation between the metal and dielectric matter in multiple internal connecting lines and the low K value, and can resist and form the pulling force that comes self-chambering structure board during the syndeton.
Another purpose of the present invention is that a kind of modification method that forms the syndeton between the metal and dielectric matter in multiple internal connecting lines and the low K value is provided.The method simply is easy to reach, and can not increase the complexity of original manufacture process.
According to above-described purpose, the invention provides a kind of modification method that forms the syndeton between the metal and dielectric matter in multiple internal connecting lines and the low K value.At first, the one semiconductor-based end with a bedded structure (a layered structure) was provided, and this bedded structure has internal connecting layer and the dielectric layer contact hole layer that a top internal connecting layer, a bottom internal connecting layer and marginal plural layer replace mutually.Each dielectric layer contact hole series of strata and an adjacent upper end internal connecting layer and an adjacent lower end internal connecting layer are alignd.One low K value dielectric medium is to insert in this bedded structure, as interior metal and dielectric matter (inter-metal dielectric).Then, this bedded structure of pattern etching forms a trench (trench) between on the internal connecting layer each is to intraconnections.Next, form one first oxide skin(coating) on this bedded structure, to fill up the trench that is positioned at this bedded structure, then with this first oxide skin(coating) planarization.Afterwards, form one second oxide skin(coating) on this first oxide skin(coating), and this second oxide skin(coating) of pattern etching, to form plurality of openings, each opening system aligns with each top intraconnections.At last, form a conductive layer on this second oxide skin(coating), fill these a little openings to form a plurality of connectors (plug) in this second oxide layer.This conductive layer of now pattern etching with form one the conduction bed course (conductive pad) across each to connector.First oxide dielectric matter system is in order to metal and dielectric matter in the low K value that is substituted in this multiple internal connecting lines mid-structure part.The strength that this first oxide dielectric matter has enough hardness to bear to form the syndeton of multiple internal connecting lines and the interior metal and dielectric matter of low K value to press down improves by this and combines reliability (reliability of bonding) between multiple internal connecting lines and the interior metal and dielectric matter of low K value.
Purpose of the present invention and plurality of advantages are by the detailed description of following preferred embodiment, and reference is appended graphic, will be tending towards clear.
Preferred embodiment of the present invention is described in detail with reference to first figure to the, eight figure.
This preferred embodiment provides a kind of modification method that forms the joint construction between the metal and dielectric matter in multiple internal connecting lines and the low K value.The formed bond structure of metal and dielectric matter (bondstructure) is to create with a pair of embedding manufacture process (dual damascene process) of resetting in this multiple internal connecting lines and the low K value.But the bond that method of the present invention is not limited to make with the dual-inlaid manufacture process is constructed.Any other can provide the method for multiple internal connecting lines and the formed bond structure of low K value dielectric medium all to be suitable for the present invention.
With reference to first figure, semiconductor substrate 10 at first is provided, be formed with a bedded structure on it.Multiple internal connecting lines layer (multi-level interconnection lines) and dielectric layer contact hole layer (via layers) that this bedded structure system is replaced mutually by plural layer are constituted.This bedded structure has a bottom internal connecting layer 20, a top internal connecting layer 24 and a middle internal connecting layer 22, and dielectric layer contact hole layer 21,23 is formed at these a little internal connecting layer respectively between any two.Each intraconnections system can be formed by copper, aluminium/copper alloy or other low resistance conductivity material, and each dielectric layer contact hole can be same as the conductivity material filling of this intraconnections material.One K value is less than 3 low K value dielectric medium, as spin-coating low K value organic polymer, for example, flare, silk and parylene and low K value spin-on glasses (spin-on glass), system inserts in this bedded structure, as interior metal and dielectric matter 30,32,34,36 and 38.Afterwards, form a dielectric layer 40 in these top internal connecting layer 24 tops.This dielectric layer 40 can be silicon nitride (Si3N4), and it can use SiH2Cl2/NH3 to regard reacting gas, under behaviour does pressure 1-0.1 holder and temperature 650-800 ℃, forms with Low Pressure Chemical Vapor Deposition.Dielectric layer 40 also can be SiNx (x=0.8-1.2), uses SiH4/NH3 as reacting gas, under behaviour does pressure 1-5 holder and temperature 250-400 ℃, forms with electric pulp vapour deposition process (PECVD).This dielectric layer 40 is not oxidized in follow-up process steps in order to protection top internal connecting layer 24.In addition, this dielectric layer 40 also can be nitrogen oxidation silicon (SiON) layer, is to use the mist of SiH4, N2O and N2 as reacting gas, forms with electric pulp vapour deposition process.
With reference to second figure, form a photoresistance on this dielectric layer 40, then with little shadow and etching technique pattern etching dielectric layer 40, in that each forms a trench 50 between to intraconnections at semiconductor-based the end 10.With reference to the 3rd figure, after removing this photoresistance, form one first oxide skin(coating) 52 on this dielectric layer 40, filling up this trench 50, and replace and do not form the interior metal and dielectric matter of low K value that is filled in this zone before the trench.First oxide skin(coating) 52 can be a silicon layer, is to use TEOS/O3 to regard reacting gas, under temperature 650-750 ℃, forms with Low Pressure Chemical Vapor Deposition.First oxide skin(coating) 52 also can be a PSG layer (its phosphorus content is controlled in the 6-8wt.% scope), and the mist that can use SiH4, PH3 and O2 forms with aumospheric pressure cvd method (APCVD) as reacting gas.
In addition, first oxide skin(coating) 52 also can be a bpsg layer, and its boron content and phosphorus content are controlled at respectively in the scope of about 1-4wt.% and 4-6wt.%.
With reference to the 4th figure, utilize chemical mechanical milling method with 52 planarizations of first oxide skin(coating), until the height of dielectric layer 40.Next, with reference to the 5th figure, second oxide skin(coating) 54 that forms about 1000 dusts of a thickness in this on first oxide skin(coating) 52 of planarization.This second oxide skin(coating) 54 can be and the silicon of first oxide skin(coating) 52 with material.With little shadow and etching technique pattern etching second oxide skin(coating) 54, form plurality of openings 56 within it, each opening 56 is to be positioned at each top intraconnections 24 top, shown in the 6th figure.
With reference to the 7th figure, the conductive layer 60 that forms about 5000 dusts of a thickness is on second oxide skin(coating) 54 of pattern etching, filling up this a little openings 56, and forms a plurality of connectors (plug).The material of this conductive layer 60 can be the copper and the aluminium/copper alloy of sputter or the formed aluminium of chemical vapour deposition (CVD), chemical vapour deposition (CVD).At last, with reference to the 8th figure, with little shadow and engraving method, this conductive layer 60 of pattern etching, form a conductivity bed course 60 across each to the connector top.
In sum, because the low K value inner metal dielectric layer of the part in the bond that multiple internal connecting lines of the present invention and dielectric layer contact hole layer the are constituted structure is to be replaced by first oxide such as silicon.The strength that the joint construction that this first oxide has enough hardness can bear this bond structure of formation presses down.And the conjugation of metal and dielectric matter also is raised in multiple internal connecting lines and the low K value.Therefore, this bond structure can resist form syndeton come self-chambering structure board to upper pulling force.
The above is a preferred embodiment of the present invention only, is not in order to limit claim scope of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in following claims scope.
First figure to the, eight figure are the schematic cross-section of the various process steps of preferred embodiment of the present invention.
The conventional letter of major part: 10: the semiconductor-based end
20: the bottom internal connecting layer
21: dielectric layer contact hole layer
22: middle internal connecting layer
23: dielectric layer contact hole layer
24: the top internal connecting layer
30,32,34,36,38: interior metal and dielectric matter
40: dielectric layer
50: trench
52: the first oxide skin(coating)s
54: the second oxide skin(coating)s
56: opening
60: the conductivity bed course
Claims (30)
1. modification method that forms multiple internal connecting lines and dielectric constant less than the joint construction between 3 the interior metal and dielectric matter, this method comprises at least:
The semiconductor substrate is provided, this substrate has a bedded structure, this bedded structure has internal connecting layer and the dielectric layer contact hole layer that a top internal connecting layer, a bottom internal connecting layer and the multilayer between between this two internal connecting layer replace mutually, each these dielectric layer contact hole series of strata and adjacent this internal connecting layer of upper end and adjacent this internal connecting layer of lower end are alignd, wherein a dielectric constant is filled in this bedded structure less than 3 dielectric medium system, as interior metal and dielectric matter;
This bedded structure of pattern etching, with form a trench on this internal connecting layer each to adjacent intraconnections between;
Form one first oxide skin(coating) on this bedded structure, to fill up this trench within it;
This first oxide skin(coating) of planarization;
Form one second oxide skin(coating) on this first oxide skin(coating);
This second oxide skin(coating) of pattern etching, to form a plurality of openings, each described opening is to align with this top intraconnections;
Form a conductive layer on this second oxide skin(coating), fill up this a plurality of openings, to form a plurality of connectors; And
This conductive layer of pattern etching, form a conduction bed course across each to described connector above.
2. the method for claim 1 is characterized in that described method comprises that above-mentioned steps also comprises formation one dielectric layer outward on this top internal connecting layer.
3. method as claimed in claim 2 is characterized in that described dielectric layer is silicon nitride Si
3N
4
4. method as claimed in claim 2 is characterized in that described dielectric layer is silicon oxynitride SiON.
5. the method for claim 1 is characterized in that described intraconnections is to be formed by copper.
6. the method for claim 1 is characterized in that described dielectric layer contact hole is to fill with copper to form.
7. the method for claim 1 is characterized in that described dielectric constant comprises spin-coating dielectric constant less than 3 organic polymers less than 3 dielectric medium.
8. method as claimed in claim 7 is characterized in that described spin-coating dielectric constant is the poly aromatic hydrocarbyl ether less than 3 organic polymer.
9. method as claimed in claim 7 is characterized in that described spin-coating dielectric constant is a dielectric constant less than 3 silicide less than 3 organic polymer.
10. method as claimed in claim 7 is characterized in that described spin-coating dielectric constant is a Parylene less than 3 organic polymer.
11. the method for claim 1 is characterized in that described dielectric constant is a dielectric constant less than 3 spin-on glasses less than 3 dielectric medium.
12. the method for claim 1 is characterized in that described first oxide skin(coating) is a silicon dioxide layer, is to be formed by chemical vapour deposition technique.
13. method as claimed in claim 12 is characterized in that described silicon dioxide series of strata use TEOS/O3 as reacting gas, under temperature 650-750 ℃, forms with Low Pressure Chemical Vapor Deposition.
14. the method for claim 1 is characterized in that the described first oxide series of strata are with the chemical mechanical milling method planarization.
15. the method for claim 1 is characterized in that described second oxide skin(coating) is the silicon dioxide of a thickness 1000 dusts, is to form with chemical vapour deposition technique.
16. method as claimed in claim 15 is characterized in that described silica-based use TEOS/O3 as reacting gas, under temperature 650-750 ℃, forms with Low Pressure Chemical Vapor Deposition.
17. the method for claim 1 is characterized in that described conductive layer is an aluminium.
18. the method for claim 1 is characterized in that described conductive layer is aluminium/copper alloy.
19. a modification method that forms copper/dielectric constant less than the joint construction of 3 dielectric medium dual-inlaid manufacture process, this method comprises at least:
The semiconductor substrate is provided, this substrate has a bedded structure, this bedded structure has a top copper internal connecting layer, copper interconnects layer and dielectric layer contact hole layer that one base copper internal connecting layer and the multilayer between between this two internal connecting layer replace mutually, each this dielectric layer contact hole layer is filled a plurality of contact holes wherein with copper and is alignd with adjacent this internal connecting layer of upper end and adjacent this internal connecting layer of lower end, wherein this bedded structure system forms with a pair of embedding manufacture process of resetting, and a dielectric constant is filled in this bedded structure less than 3 dielectric medium system, as interior metal and dielectric matter;
This bedded structure of pattern etching, with form a trench on this internal connecting layer each to adjacent intraconnections between;
Form one first oxide skin(coating) on this bedded structure, to fill up this trench within it, then with this first oxide skin(coating) planarization;
Form one second oxide skin(coating) on this first oxide skin(coating);
This second oxide skin(coating) of pattern etching, to form a plurality of openings, each described opening is to align with this top intraconnections;
Form a conductive layer on this second oxide skin(coating), fill up described a plurality of opening, to form a plurality of connectors; And
This conductive layer of pattern etching, form a conduction bed course across each to described connector above.
20. method as claimed in claim 19 is characterized in that described step more comprises formation one dielectric layer on this top internal connecting layer.
21. method as claimed in claim 20 is characterized in that described dielectric layer is silicon nitride Si
3N
4
22. method as claimed in claim 20 is characterized in that described dielectric layer is silicon oxynitride SiON.
23. method as claimed in claim 19 is characterized in that described first oxide skin(coating) is a silicon dioxide layer, is to be formed by chemical vapour deposition technique.
24. method as claimed in claim 23 is characterized in that described silicon dioxide series of strata use TEOS/O3 as reacting gas, under temperature 650-750 ℃, forms with Low Pressure Chemical Vapor Deposition.
25. method as claimed in claim 19 is characterized in that the described first oxide series of strata are with the chemical mechanical milling method planarization.
26. method as claimed in claim 19 is characterized in that described second oxide skin(coating) is the silicon dioxide of a thickness 1000 dusts, is to form with chemical vapour deposition technique.
27. method as claimed in claim 26 is characterized in that described silica-based use TEOS/O3 as reacting gas, under temperature 650-750 ℃, forms with Low Pressure Chemical Vapor Deposition.
28. method as claimed in claim 19 is characterized in that described conductive layer is an aluminium.
29. method as claimed in claim 19 is characterized in that described conductive layer is aluminium/copper alloy.
30. method as claimed in claim 19 is characterized in that described dielectric constant comprises dielectric constant less than 3 spin-on glasses less than 3 dielectric medium.
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| CNB001318845A CN1163956C (en) | 2000-10-30 | 2000-10-30 | Improved method for forming multiple interconnection line and internal metal dielectric connection structure |
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| CNB001318845A CN1163956C (en) | 2000-10-30 | 2000-10-30 | Improved method for forming multiple interconnection line and internal metal dielectric connection structure |
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| CN100499108C (en) * | 2006-06-20 | 2009-06-10 | 台湾积体电路制造股份有限公司 | Interconnection structure and chip |
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