CN116388963B - Method, device and system for encrypting packet - Google Patents

Abstract

The present invention discloses a group encryption method, device and system, the method comprising: inputting an original key and a round number as input data into a first round function to obtain a number of subkeys related to the round number; grouping the original data to obtain a number of groups of data; and inputting each group of data and all subkeys related to the round number as input data into a second round function to obtain a number of groups of encrypted data. The present invention can improve encryption efficiency and reduce required energy consumption and memory. The subkey generation process and data encryption process of the present invention are consistent and can resist related key attacks.

Description

A block encryption method, device and system

Technical Field

The present invention belongs to the technical field of data security transmission in a network environment, and specifically relates to a packet encryption method, device and system.

Background Art

In order to prevent the confidentiality of data during network transmission, an encryption algorithm is usually used to encrypt the message to be sent into garbled code before transmission. After receiving the message, the receiver can decrypt the garbled code to restore it to the original message. The existing standard encryption algorithms include the international encryption standard AES and the Chinese encryption standard SM4. In resource-constrained environments such as the Internet of Things, China does not yet have a standard lightweight encryption standard, while the international ISO standard lightweight encryption algorithms HIGHT, PRESENT, CLEFIA and SIMON and SPECK proposed by the US NIST have emerged.

The research on lightweight encryption algorithms is still immature. The current standard encryption algorithms are often expensive to implement in software and hardware, and are even difficult to directly apply in environments with extremely limited resources. China currently does not have a standard lightweight encryption algorithm. The various lightweight encryption standard algorithms proposed internationally also have various problems, such as the full-round attack of HIGHT, the non-random distinguisher of the PRESENT algorithm, the heavy weight of CLEFIA hardware implementation, and the lack of security self-assessment results of SIMON and SPECK.

Summary of the invention

In view of the above problems, the present invention proposes a block encryption method, device and system, which can improve encryption efficiency and reduce required energy consumption and memory.

In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:

In a first aspect, the present invention provides a block encryption method, comprising:

The original key and the round number are used as input data and input into the first round function to obtain a number of sub-keys related to the round number;

Group the original data to obtain several groups of data;

Each group of data and all subkeys related to the round number are respectively input as input data to the second round function to obtain several groups of encrypted data.

Optionally, the first round function and the second round function have the same structure, both comprising N logical units connected in sequence;

The structures of the logic units are the same, and all include a first cyclic shift module, a second cyclic shift module, a first XOR module, a second XOR module and a modular addition module;

One end of the first cyclic shift module is connected to one end of the first XOR module and is used as one of the input ends of the logic unit, and the other end is connected to one end of the second XOR module;

The other end of the second XOR module is used as another input end of the logic unit;

The other end of the first XOR module is connected to one end of the second cyclic shift module and is used as one of the output ends of the logic unit;

The other end of the second cyclic shift module is connected to one end of the modular addition module;

The other end of the analog addition module is connected to the other end of the second XOR module and is used as another output end of the logic unit.

Optionally, before the original key is input as input data to the first round function, the method further includes: dividing the original key into two keys, k ₀ and t ₀ ;

The output expressions of each logic unit in the first round function are:

Wherein, k _i+1 and t _i+1 represent the two output subkeys of the ith logic unit, k _i and t _i represent the two input subkeys of the ith logic unit, c _i represents the ith round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module, <<< represents left cyclic shift, represents XOR, Represents bit modular addition, i=1,2,…N.

Optionally, the output expression of each logic unit in the second round function is:

In the formula, and Respectively represent the two output data of the i-th logic unit, and They represent two input data of the i-th logic unit, k _i represents the key of the i-th round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module respectively, and <<< represents left cyclic shift. represents XOR, Represents bit modular addition, i=0,2,…N-1.

Optionally, when the original data is grouped to obtain several groups of data, if the length of the last group of data is less than the group length, a padding operation is performed on the last group of data so that the length of the padded data is equal to the group length.

In a second aspect, the present invention provides a block encryption device, comprising:

A subkey acquisition module, used to input the original key and the round number as input data into the first round function to obtain a number of subkeys related to the round number;

A grouping module is used to group the original data to obtain several groups of data;

The encryption module is used to input each group of data and all subkeys related to the round number as input data to the second round function to obtain several groups of encrypted data.

Optionally, the first round function and the second round function have the same structure, both comprising N logical units connected in sequence;

The structures of the logic units are the same, and all include a first cyclic shift module, a second cyclic shift module, a first XOR module, a second XOR module and a modular addition module;

One end of the first cyclic shift module is connected to one end of the first XOR module and is used as one of the input ends of the logic unit, and the other end is connected to one end of the second XOR module;

The other end of the second XOR module is used as another input end of the logic unit;

The other end of the first XOR module is connected to one end of the second cyclic shift module and is used as one of the output ends of the logic unit;

The other end of the second cyclic shift module is connected to one end of the modular addition module;

The other end of the analog addition module is connected to the other end of the second XOR module and is used as another output end of the logic unit.

Optionally, before the original key is input as input data to the first round function, the method further includes: dividing the original key into two keys, k ₀ and t ₀ ;

The output expressions of each logic unit in the first round function are:

Wherein, k _i+1 and t _i+1 represent the two output subkeys of the ith logic unit, k _i and t _i represent the two input subkeys of the ith logic unit, c _i represents the ith round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module, <<< represents left cyclic shift, represents XOR, Represents bit modular addition, i=1,2,…N.

Optionally, the output expression of each logic unit in the second round function is:

In the formula, and Respectively represent the two output data of the i-th logic unit, and They represent two input data of the i-th logic unit, k _i represents the key of the i-th round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module respectively, <<< represents left cyclic shift, represents XOR, Represents bit modular addition, i=0,2,…N-1.

Optionally, when the original data is grouped to obtain several groups of data, if the length of the last group of data is less than the group length, a padding operation is performed on the last group of data so that the length of the padded data is equal to the group length.

In a third aspect, the present invention provides a block encryption system, including a storage medium and a processor;

The storage medium is used to store instructions;

The processor is configured to operate according to the instructions to execute the method according to any one of the first aspects.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention utilizes a first round function to generate a plurality of subkeys, and utilizes a second round function and all subkeys related to the round number to implement data encryption, which can not only improve encryption efficiency but also reduce required energy consumption and memory.

In the present invention, the logic units of the first round function and the second round function only include two cyclic shift modules, one modular addition module and two XOR modules, and the structure is simple and lightweight as much as possible.

The present invention adopts modular addition operation instead of S-box (the basic structure of symmetric key algorithm to perform permutation calculation) operation as the nonlinear component of the algorithm. Compared with the traditional algorithm with S-box, the software implementation efficiency has obvious advantages and the cost of protecting against side channel attacks is low.

The subkey generation process and data encryption process of the present invention are consistent and can resist related key attacks.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments and in conjunction with the accompanying drawings, wherein:

FIG1 is a flow chart of a block encryption method according to an embodiment of the present invention;

FIG2 is a schematic diagram of the structure of a first round function according to an embodiment of the present invention;

FIG3 is a schematic diagram of the structure of a second round function according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the scope of protection of the present invention.

The application principle of the present invention is described in detail below in conjunction with the accompanying drawings.

Example 1

The present invention provides a block encryption method, as shown in FIG1 , comprising the following steps:

(1) The original key and the round number are input into the first round function to obtain a number of subkeys related to the round number;

(3) Grouping the original data to obtain several groups of data;

(3) Each group of data and all subkeys related to the round number are input as input data to the second round function to obtain several groups of encrypted data.

In a specific implementation of the embodiment of the present invention, as shown in FIG2-3, the first round function and the second round function have the same structure, but the input and output data of the first round function and the second round function are different; the first round function and the second round function both include N logical units connected in sequence; the structures of the logical units are the same, including a first cyclic shift module, a second cyclic shift module, a first XOR module, a second XOR module and a modular addition module;

One end of the first cyclic shift module is connected to one end of the first XOR module and is used as one of the input ends of the logic unit, and the other end is connected to one end of the second XOR module;

The other end of the second XOR module is used as another input end of the logic unit;

The other end of the first XOR module is connected to one end of the second cyclic shift module and is used as one of the output ends of the logic unit;

The other end of the second cyclic shift module is connected to one end of the modular addition module;

The other end of the analog addition module is connected to the other end of the second XOR module and is used as another output end of the logic unit.

In a specific implementation of the embodiment of the present invention, before the original key is used as input data and input into the first round function, it also includes: dividing the original key into two keys, k ₀ and t ₀ ;

When the step of inputting the original key and the round number as input data into the first round function to obtain a plurality of subkeys related to the round number is executed, the output expression of each logic unit in the first round function is:

Wherein, k _i+1 and t _i+1 represent the two output subkeys of the ith logic unit, k _i and t _i represent the two input subkeys of the ith logic unit, c _i represents the ith round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module, <<< represents left cyclic shift, represents XOR, represents bitwise modular addition, i=1,2,…N. In a specific implementation, x1 and x2 can be set to 13 and 22, or other parameters can be set to achieve similar security, such as 2 and 21, 22 and 13, etc. N can be set to 24. The length of each subkey can be set to 64, and N and the length of each subkey can also be set to other appropriate values.

When executing the step of inputting each group of data and all subkeys related to the round number as input data to the second round function to obtain a plurality of groups of encrypted data, the output expression of each logic unit in the second round function is:

In the formula, and Respectively represent the two output data of the i-th logic unit, and They represent two input data of the i-th logic unit, k _i represents the key of the i-th round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module respectively, <<< represents left cyclic shift, represents XOR, represents bit modular addition, i=0,2,…N-1. In the specific implementation process, x1 and x2 can be set to 13 and 22, and other parameters can also be set to achieve similar security, such as 2 and 21, 22 and 13, etc. N can be set to 24. The length of each group of data can be set to 64, and N and the length of each subkey can also be set to other appropriate values.

In a specific implementation of an embodiment of the present invention, when the original data is grouped to obtain several groups of data, if the length of the last group of data is less than the group length, the last group of data is padded so that the length of the padded data is equal to the group length.

In particular, in the present invention, in order to improve the security of the algorithm, the parameters of the two cyclic left shift operations in the round function are set to 13 and 22.

In addition to the above parameters, other parameters can also be set to achieve similar security, such as 2 and 21, 22 and 13.

The packet encryption method of the present invention has the advantages of light weight, high efficiency, low power consumption and small amount of memory during data transmission. The packet encryption method in the embodiment of the present invention can be used for small devices such as power IoT sensor equipment with limited computing and storage resources.

The block encryption method in the embodiment of the present invention is described in detail below in conjunction with a specific implementation manner.

Set the packet length to 64 bits and the number of cycles to 24.

If the original data is larger than 64 bits, the original data is grouped and the grouped data less than 64 bits are padded with zeros, and then each group of data is divided into two left and right branches. To generate 64-bit output, proceed as follows

If the original data is exactly 64 bits, the original data is directly divided into left and right branches To generate 64-bit output, proceed as follows

From 64-bit plaintext Initially, the process requires 23 updates, i.e., i=0,1,…,22.

Finally, execute

Generate 64-bit ciphertext Where k _i is the subkey of round i=0,1,…,23, and its generation process is as follows:

Assume that the 64-bit master key is divided into two parts: left and right The update process from (k _i ,t _i ) to (k _i+1 ,t _i+1 ), i=0,1,…,23 is as follows:

Test vector:

Plain text: 0x0123456789abcdef

Key: 0x0123456789abcdef

Ciphertext: 0x8441cbc2ea3eff46.

Example 2

An embodiment of the present invention provides a packet encryption device, including:

A subkey acquisition module, used to input the original key and the round number as input data into the first round function to obtain a number of subkeys related to the round number;

A grouping module is used to group the original data to obtain several groups of data;

The encryption module is used to input each group of data and all subkeys related to the round number as input data to the second round function to obtain several groups of encrypted data.

In a specific implementation of the embodiment of the present invention, as shown in FIG2-3, the first round function and the second round function have the same structure, but the input and output data of the first round function and the second round function are different; the first round function and the second round function both include N logical units connected in sequence; the structures of the logical units are the same, including a first cyclic shift module, a second cyclic shift module, a first XOR module, a second XOR module and a modular addition module;

One end of the first cyclic shift module is connected to one end of the first XOR module and is used as one of the input ends of the logic unit, and the other end is connected to one end of the second XOR module;

The other end of the second XOR module is used as another input end of the logic unit;

The other end of the first XOR module is connected to one end of the second cyclic shift module and is used as one of the output ends of the logic unit;

The other end of the second cyclic shift module is connected to one end of the modular addition module;

The other end of the analog addition module is connected to the other end of the second XOR module and is used as another output end of the logic unit.

In a specific implementation of the embodiment of the present invention, before the original key is used as input data and input into the first round function, it also includes: dividing the original key into two keys, k ₀ and t ₀ ;

When the step of inputting the original key and the round number as input data into the first round function to obtain a plurality of subkeys related to the round number is executed, the output expression of each logic unit in the first round function is:

Wherein, k _i+1 and t _i+1 represent the two output subkeys of the ith logic unit, k _i and t _i represent the two input subkeys of the ith logic unit, c _i represents the ith round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module, respectively, <<< represents left cyclic shift, represents XOR, represents bitwise modular addition, i=1,2,…N. In a specific implementation, x1 and x2 can be set to 13 and 22, or other parameters can be set to achieve similar security, such as 2 and 21, 22 and 13, etc. N can be set to 24. The length of each subkey can be set to 64, and N and the length of each subkey can also be set to other appropriate values.

When executing the step of inputting each group of data and all subkeys related to the round number as input data to the second round function to obtain a plurality of groups of encrypted data, the output expression of each logic unit in the second round function is:

In the formula, and Respectively represent the two output data of the i-th logic unit, and They represent two input data of the i-th logic unit, k _i represents the key of the i-th round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module respectively, and <<< represents left cyclic shift. represents XOR, represents bit modular addition, i=0,2,…N-1. In the specific implementation process, x1 and x2 can be set to 13 and 22, and other parameters can also be set to achieve similar security, such as 2 and 21, 22 and 13, etc. N can be set to 24. The length of each group of data can be set to 64, and N and the length of each subkey can also be set to other appropriate values.

In a specific implementation of an embodiment of the present invention, when the original data is grouped to obtain several groups of data, if the length of the last group of data is less than the group length, the last group of data is padded so that the length of the padded data is equal to the group length.

The working process of the block encryption device in the embodiment of the present invention is described in detail below in conjunction with a specific implementation method.

Set the packet length to 64 bits and the number of cycles to 24.

If the original data is larger than 64 bits, the original data is grouped and the grouped data less than 64 bits are padded with zeros, and then each group of data is divided into two left and right branches. To generate 64-bit output, proceed as follows

If the original data is exactly 64 bits, the original data is directly divided into left and right branches To generate 64-bit output, proceed as follows

From 64-bit plaintext Initially, the process requires 23 updates, i.e., i=0,1,…,22.

Finally, execute

Generate 64-bit ciphertext Where k _i is the subkey of round i=0,1,…,23, and its generation process is as follows:

Assume that the 64-bit master key is divided into two parts: left and right The update process from (k _i ,t _i ) to (k _i+1 ,t _i+1 ), i=0,1,…,23 is as follows:

Test vector:

Plain text: 0x0123456789abcdef

Key: 0x0123456789abcdef

Ciphertext: 0x8441cbc2ea3eff46.

Example 3

Based on the same inventive concept as that of Embodiment 1, the present invention provides a block encryption system, including a storage medium and a processor;

The storage medium is used to store instructions;

The processor is configured to operate according to the instructions to execute the method according to any one of the embodiments 1.

Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

The present application is described with reference to the flowchart and/or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and/or box in the flowchart and/or block diagram, and the combination of the process and/or box in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims (5)

1. A block encryption method, comprising: The original key and the round number are used as input data and input into the first round function to obtain a number of sub-keys related to the round number; Group the original data to obtain several groups of data; Each group of data and all subkeys related to the round number are input as input data to the second round function to obtain several groups of encrypted data; The first round function and the second round function have the same structure, both comprising N logical units connected in sequence; The structures of the logic units are the same, and all include a first cyclic shift module, a second cyclic shift module, a first XOR module, a second XOR module and a modular addition module; One end of the first cyclic shift module is connected to one end of the first XOR module and is used as one of the input ends of the logic unit, and the other end is connected to one end of the second XOR module; The other end of the second XOR module is used as another input end of the logic unit; The other end of the first XOR module is connected to one end of the second cyclic shift module and is used as one of the output ends of the logic unit; The other end of the second cyclic shift module is connected to one end of the modular addition module; The other end of the analog addition module is connected to the other end of the second XOR module and is used as another output end of the logic unit; Before the original key is input as input data to the first round function, it also includes: Divide the original key into two keys, k ₀ and t ₀ ; The output expressions of each logic unit in the first round function are: Wherein, k _i+1 and t _i+1 represent the two output subkeys of the ith logic unit, k _i and t _i represent the two input subkeys of the ith logic unit, c _i represents the ith round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module, respectively, <<< represents left cyclic shift, represents XOR, Represents bitwise addition, i = 1, 2, ... N; The output expression of each logic unit in the second round function is: In the formula, and Respectively represent the two output data of the i-th logic unit, and They represent two input data of the i-th logic unit, k _i represents the key of the i-th round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module respectively, and <<< represents left cyclic shift. represents XOR, Represents bit modular addition, i=0,2,…N-1. 2. According to claim 1, a packet encryption method is characterized in that: when the original data is grouped to obtain several groups of data, if the length of the last group of data is less than the group length, the last group of data is padded so that the length of the padded data is equal to the group length. 3. A block encryption device, comprising: A subkey acquisition module, used to input the original key and the round number as input data into the first round function to obtain a number of subkeys related to the round number; A grouping module is used to group the original data to obtain several groups of data; The encryption module is used to input each group of data and all subkeys related to the round number as input data to the second round function to obtain a plurality of groups of encrypted data; The first round function and the second round function have the same structure, both comprising N logical units connected in sequence; The structures of the logic units are the same, and all include a first cyclic shift module, a second cyclic shift module, a first XOR module, a second XOR module and a modular addition module; One end of the first cyclic shift module is connected to one end of the first XOR module and is used as one of the input ends of the logic unit, and the other end is connected to one end of the second XOR module; The other end of the second XOR module is used as another input end of the logic unit; The other end of the first XOR module is connected to one end of the second cyclic shift module and is used as one of the output ends of the logic unit; The other end of the second cyclic shift module is connected to one end of the modular addition module; The other end of the analog addition module is connected to the other end of the second XOR module and is used as another output end of the logic unit; Before the original key is input as input data to the first round function, the method further includes: dividing the original key into two keys, k ₀ and t ₀ ; The output expressions of each logic unit in the first round function are: Wherein, k _i+1 and t _i+1 represent the two output subkeys of the ith logic unit, k _i and t _i represent the two input subkeys of the ith logic unit, c _i represents the ith round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module, respectively, <<< represents left cyclic shift, represents XOR, Indicates bitwise addition, i = 1, 2, ... N; The output expression of each logic unit in the second round function is: In the formula, and Respectively represent the two output data of the i-th logic unit, and They represent two input data of the i-th logic unit, k _i represents the key of the i-th round, x1 and x2 represent the shift bits of the first cyclic shift module and the second cyclic shift module respectively, and <<< represents left cyclic shift. represents XOR, Represents bit modular addition, i=0,2,…N-1. 4. A group encryption device according to claim 3, characterized in that when the original data is grouped to obtain several groups of data, if the length of the last group of data is less than the group length, the last group of data is padded so that the length of the padded data is equal to the group length. 5. A block encryption system, characterized in that: it includes a storage medium and a processor; The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the method according to any one of claims 1 to 2.