CN116364781A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a method for manufacturing the same, the semiconductor structure including: a substrate; an oxide semiconductor layer on a part of the surface of the substrate, the oxide semiconductor layer having a dopant ion therein for pinning oxygen vacancies; the doped layer is at least positioned between the oxide semiconductor layer and the substrate, and doped ions are arranged in the doped layer; a gate electrode on a portion of the surface of the oxide semiconductor layer remote from the substrate; the source-drain doped region is positioned in the oxide semiconductor layer at two sides of the grid electrode. At least carrier mobility in the semiconductor structure may be improved.

Description

Semiconductor structure and manufacturing method thereof

technical field

Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.

Background technique

Thin Film Transistor (TFT, Thin Film Transistor), as the core device of active matrix driven flat panel display technology, is widely used in the display field. At present, in flat panel display technology, silicon-based thin film transistors are relatively mature industrialized technologies, mainly including amorphous silicon and polysilicon thin film transistors. With the development of flat panel display technology towards large area, high resolution, flexible and rollable type and the emergence of many new flat panel display technologies, higher requirements are put forward for the performance of thin film transistors.

Oxide semiconductor layers such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), etc. are amorphous oxides, It has a higher electron mobility than amorphous silicon. Applying the oxide semiconductor layer to the channel material of a new generation of thin film transistors can greatly increase the charge and discharge rate of the thin film transistor to the pixel electrode, improve the corresponding speed of the pixel, and achieve a faster refresh rate. The semiconductor structure has a higher energy efficiency level and higher efficiency. However, there are still some problems with this semiconductor structure at present.

Contents of the invention

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can at least improve carrier mobility in the semiconductor structure.

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; Doping ions for vacancies; a doping layer located at least between the oxide semiconductor layer and the substrate, and having the doping ions in the doping layer; a gate located away from the oxide semiconductor layer On a part of the surface of the substrate; a source-drain doped region located in the oxide semiconductor layer on both sides of the gate.

In some embodiments, the dopant ions include one or more of fluoride ions or hydrogen ions.

In some embodiments, the material of the doped layer includes silicon nitride.

In some embodiments, the doped layer has a thickness of 10-30 nm.

In some embodiments, the base includes: a substrate and at least one fin located on the substrate, the substrate also has an isolation layer covering the sides of the fin part, and the top surface of the fin is as high as On the top surface of the isolation layer; the oxide semiconductor layer is at least located on the top surface of the fin and on the side surface higher than the isolation layer, and the doped layer is located on the top and side surfaces of the fin.

In some embodiments, the at least one fin includes a plurality of fins arranged at intervals along a predetermined direction; the oxide semiconductor layer and the gate both straddle the predetermined direction along the the plurality of fins.

According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming an oxide semiconductor layer and a doped layer, and the oxide semiconductor layer is located on the substrate On a part of the surface, the doped layer is located at least between the oxide semiconductor layer and the substrate, and the doped layer has dopant ions; a gate is formed, and the oxide semiconductor layer is located away from the part of the surface of the substrate; forming source-drain doped regions located in the oxide semiconductor layer on both sides of the gate; performing annealing treatment so that part of the dopant ions in the doped layer diffuse to the In the oxide semiconductor layer, the doping is used to pin oxygen vacancies in the oxide semiconductor layer.

In some embodiments, before forming the gate, further comprising: treating the surface of the oxide semiconductor layer by using a plasma treatment process.

In some embodiments, the step of forming the base includes: providing an initial substrate; patterning a partial thickness of the initial substrate to form at least one fin, and the rest of the substrate under the at least one fin The initial substrate serves as a substrate, said substrate and said at least one fin forming said base.

In some embodiments, the steps of forming the source-drain doped region and performing the annealing treatment include: performing doping treatment on the oxide semiconductor layer on opposite sides of the gate; After the treatment, the annealing treatment is performed to activate ions in the doped layer and diffuse part of the doped ions in the doped layer into the oxide semiconductor layer.

The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

In the technical solution of the semiconductor structure provided by the embodiments of the present disclosure, it includes: a substrate; an oxide semiconductor layer located on a part of the surface of the substrate, and the oxide semiconductor layer has doping ions for pinning oxygen vacancies; a doped layer, At least located between the oxide semiconductor layer and the substrate, and the doped layer has dopant ions; the gate is located on a part of the surface of the oxide semiconductor layer away from the substrate; the source and drain doped regions are located on both sides of the oxide semiconductor gate layer. In the semiconductor structure provided by the embodiments of the present disclosure, a doping layer is provided at least between the oxide semiconductor layer and the substrate, and the oxide semiconductor layer has doping ions for pinning oxygen vacancies. The dopant ions pin more oxygen vacancies in the oxide semiconductor layer, which can increase the number of oxygen vacancies in the oxide semiconductor layer as carrier migration tracks, thereby improving the carrier density in the oxide semiconductor layer. Mobility, maintains the carrier concentration and thermal stability in the oxide semiconductor layer during annealing, and improves the carrier mobility in the semiconductor structure. In addition, the embodiment of the present disclosure also enlarges the channel area of the oxide semiconductor layer, keeps the channel length unchanged, and maintains device performance.

Description of drawings

One or more embodiments are exemplified by the pictures in the accompanying drawings, and these exemplifications do not constitute a limitation to the embodiments, unless otherwise stated, the figures in the accompanying drawings do not constitute a scale limitation; for To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure , for those skilled in the art, other drawings can also be obtained according to these drawings on the premise of not paying creative work.

Fig. 1 is a structural schematic diagram of a semiconductor structure;

FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

3 is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure;

5 is a schematic cross-sectional structure diagram of a semiconductor structure provided by another embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure;

7 is a schematic cross-sectional structure diagram of a semiconductor structure provided by another embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure;

9 to 18 are structural schematic diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure.

Detailed ways

It can be seen from the background art that the current semiconductor structure has the problem that the carrier mobility needs to be improved.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a semiconductor structure. The semiconductor structure includes: a substrate 10; an oxide semiconductor layer 20 located on a part of the surface of the substrate 10; a gate 30 located on a part of the surface of the oxide semiconductor layer 20 away from the substrate 10; a source-drain doped region 21 located on the gate In the oxide semiconductor layer 20 on both sides of the gate 30 ; the source and drain electrodes 40 are located on both sides of the gate 30 and also located on a part of the surface of the oxide semiconductor layer 20 away from the substrate 10 . In addition, there is an insulating layer 50 between the gate 30 and the source and drain 40, the insulating layer 50 covers the sides of the gate 30 and the source and drain 40 and the insulating layer 50 electrically isolates the gate 30 from the source and drain 40, and the gate 30 is electrically isolated from the source and drain 40. There is also a gate oxide layer 60 between 30 and the oxide semiconductor layer 20 , and there is an isolation layer 70 between the substrate 10 and the oxide semiconductor layer 20 .

Analysis found that in the above semiconductor structure, the oxide semiconductor layer 20, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO ) is the channel of the semiconductor structure. When the semiconductor structure is in operation, carriers will move in the oxide semiconductor layer 20 to form a current. Since the number of oxygen vacancies serving as carrier migration tracks in the oxide semiconductor layer 20 is small, the concentration of carriers in the oxide semiconductor layer 20 is small, and the carrier mobility in the oxide semiconductor layer 20 is also low. Low, so that the mobility of carriers in the semiconductor structure is low. If a semiconductor structure can be provided so that the number of oxygen vacancies serving as carrier migration tracks in the oxide semiconductor layer 20 of the semiconductor structure increases, the above problems can be improved.

An embodiment of the present disclosure provides a semiconductor structure, including: a substrate; an oxide semiconductor layer located on a part of the surface of the substrate, wherein the oxide semiconductor layer has doping ions for pinning oxygen vacancies; a doped layer located at least on the oxide semiconductor layer Between the material semiconductor layer and the substrate, and the doped layer has dopant ions; the gate is located on the part of the surface of the oxide semiconductor layer away from the substrate; the source and drain doped regions are located in the oxide semiconductor layer on both sides of the gate . In this way, the dopant ions in the doped layer can pin more oxygen vacancies in the oxide semiconductor layer, and these oxygen vacancies can be used as the migration track of the carriers, which can keep the charge in the oxide semiconductor layer during annealing. The concentration and thermal stability of carriers can improve the mobility of carriers in the oxide semiconductor layer, thereby increasing the mobility of carriers in the semiconductor structure and optimizing the performance of the semiconductor structure.

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in various embodiments of the present disclosure, many technical details are provided for readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be realized.

2 to 8 are structural schematic diagrams of semiconductor structures provided by embodiments of the present disclosure.

FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, and FIG. 3 is a schematic cross-sectional structural diagram of FIG. 2 taken along the AA1 direction. Referring to FIGS. 2 to 3 , the semiconductor structure includes: a substrate 100; an oxide semiconductor layer 110 located on a part of the surface of the substrate 100, the oxide semiconductor layer 110 having dopant ions for pinning oxygen vacancies; a doped layer 120 , located at least between the oxide semiconductor layer 110 and the substrate 100, and the doped layer 120 has dopant ions; the gate 130, located on a part of the surface of the oxide semiconductor layer 110 away from the substrate 100; the source-drain doped region 111, located in the oxide semiconductor layer 110 on both sides of the gate 130 .

In some embodiments, the substrate 100 may be an active region. The material of the substrate 100 may include single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); Or it can also be a glass substrate or other materials, such as III-V group compounds such as gallium arsenide. In an embodiment of the present disclosure, the material of the substrate 100 may be single crystal silicon (Si) or a glass substrate.

The oxide semiconductor layer 110, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), such as IGZO, contains indium , gallium and zinc. Using an oxide semiconductor material in the oxide semiconductor layer 110 in the semiconductor structure as a channel of the semiconductor structure can improve the performance of the semiconductor structure. Compared with the channel layer of amorphous silicon material, the carrier mobility of the channel layer made of oxide semiconductor is 20-30 times that of amorphous silicon, and the oxide semiconductor layer can also improve the charge and discharge rate of the semiconductor structure , to improve the energy efficiency of semiconductor structures.

The source-drain doping region 111 needs to be doped. If N-type doping is required, N-type ions, such as nitrogen ions and phosphorus ions, can be implanted. If P-type doping is required, P-type ions such as boron ions and aluminum ions can be implanted.

Referring to FIG. 2 , the doped layer 120 may be located only between the oxide semiconductor layer 110 and the substrate 100 . The dopant ions in the doped layer 120 can be pinned into the oxide semiconductor layer 110 adjacent to the doped layer 120 through high-temperature annealing treatment, and the dopant ions can pin more oxygen vacancies in the oxide semiconductor layer 110 , oxygen vacancies can be used as carrier migration orbits, and the increase of oxygen vacancies can increase the carrier migration orbits. The carrier mobility in the oxide semiconductor layer 110 is increased.

In some embodiments, the dopant ions may include one or more of fluoride ions or hydrogen ions. When the dopant ions are fluorine ions or hydrogen ions, the dopant ions in the doped layer 120 are easier to diffuse into the oxide semiconductor layer 110 to pin oxygen vacancies that can be used as carrier migration tracks, which can further enhance the doping Effect of ions on increasing carrier mobility in semiconductor structures.

In some embodiments, the material of the doped layer 120 may include silicon nitride. Silicon nitride has high hardness and compactness, good compatibility with process, and can introduce dopant ions, such as H and F, without damaging device performance. Using silicon nitride as the material of doped layer 120 can This enables the doping layer 120 to meet the requirement of carrying dopant ions for pinning oxygen vacancies in the oxide semiconductor layer 110 , while improving the mechanical strength and insulation performance of the semiconductor structure, and improving the stability of the semiconductor structure.

In some embodiments, the thickness of the doped layer 120 may be 10-30 nm. For example, the thickness of the doped layer 120 may be 10 nm, 12 nm, 16 nm, 18 nm, 24 nm, and so on. If the thickness of the doped layer 120 is small, there are fewer dopant ions in the doped layer 120 that can diffuse into the oxide semiconductor layer 110 to pin oxygen vacancies, and the oxygen vacancies in the oxide semiconductor layer 110 are still less. The improvement of the carrier mobility of the semiconductor structure is not good; if the thickness of the doped layer 120 is large, it may cause certain waste, increase the manufacturing cost of the semiconductor structure, and also increase the size of the semiconductor structure. It is conducive to the development of the semiconductor structure towards the direction of miniaturization and miniaturization. Therefore, the thickness of the doped layer 120 can be selected in an appropriate range. When the thickness of the doped layer 120 is 10-30 nm, the doped layer 120 can provide enough doping ions so that the carrier mobility of the semiconductor structure is effectively obtained. Improve without causing waste.

In some embodiments, the material of the gate 130 may include one or more of polysilicon or tungsten.

FIG. 4 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, and FIG. 5 is a schematic cross-sectional structural diagram of FIG. 4 taken along the AA1 direction.

Referring to FIGS. 4 to 5 , in some embodiments, the semiconductor structure may further include a gate oxide layer 140 located between the gate 130 and the oxide semiconductor layer 110 . The material of the gate oxide layer 140 may include silicon oxide, aluminum oxide, or the like. The setting of the gate oxide layer 140 can improve the electron conduction performance of the semiconductor structure, making the conduction of electrons in the semiconductor structure smoother, and the gate oxide layer 140 can also control the current, prevent the device from being overheated or short-circuited due to excessive current, and can form a charge The channel, which is used to control the flow of electrons in the device, can also improve the stability of the device, improve the efficiency of the device, and protect the device from environmental factors to a certain extent. In addition, the gate oxide layer 140 also has a certain surface activity and can be used as a surface active layer in the semiconductor structure to receive or place other substances.

In some embodiments, the semiconductor structure may have source and drain electrodes 150 located on both sides of the gate 130 and the source and drain electrodes 150 are located on a part of the surface of the oxide semiconductor layer 110 away from the substrate 100 . The material of the source and drain electrodes 150 may include one or more of polysilicon or tungsten.

In some embodiments, the semiconductor structure may further have an insulating layer 160 located between the gate 130 and the source/drain 150 , and the insulating layer 160 covers the sides of the gate 130 and the source/drain 150 . The material of the insulating layer 160 may include silicon nitride. The insulating layer 160 can function to isolate the gate 130 and the source-drain 150 . In a direction perpendicular to the surface of the substrate 100 , the oxide semiconductor layer 110 directly under the insulating layer 160 may also be a source-drain doped region 111 .

In some embodiments, the semiconductor structure may further have an isolation layer 170 located on the surface of the substrate 100 , and the doped layer 120 is located at least on a part of the surface of the isolation layer 170 away from the substrate 100 . The material of the isolation layer 170 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. The isolation layer 170 can isolate the substrate 100 from the oxide semiconductor layer 110 to reduce the occurrence of electric leakage in the semiconductor structure and improve the stability of the semiconductor structure.

FIG. 6 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, and FIG. 7 is a schematic cross-sectional structural diagram of FIG. 6 taken along the AA1 direction. Referring to FIGS. 6 to 7 , in some embodiments, the base 100 may include: a substrate 101 and at least one fin 102 on the substrate 101 . An isolation layer 170 may also be provided on the substrate 101, the isolation layer 170 covers part of the sides of the fin 102, and the top surface of the fin 102 is higher than the top surface of the isolation layer 170; the oxide semiconductor layer 110 is located at least on the top surface of the fin 102 and higher than the side of the isolation layer 170 , and the doped layer 120 is located on the top and side of the fin 102 . In this way, without increasing the length of the oxide semiconductor layer 110 as a channel in the semiconductor structure, the contact area between the oxide semiconductor layer 110 as a channel and the gate 130 in the semiconductor structure can be increased, and the size of the semiconductor structure can be reduced. In addition, the control ability of the gate 130 on the oxide semiconductor layer 110 can be improved, the short channel effect can be effectively suppressed, the subthreshold leakage current can be reduced, the gate leakage current can be reduced, and the performance of the semiconductor structure can be improved.

In some embodiments, at least one fin 102 may include a plurality of fins 102 arranged at intervals along a preset direction; the oxide semiconductor layer 110 and the gate 130 may both span the plurality of fins along a preset direction Section 102. A plurality of fins 102 arranged at intervals along a predetermined direction can further increase the contact area between the oxide semiconductor layer 110 and the gate 130, further improve the control ability of the gate 130 on the oxide semiconductor layer 110, and further improve the semiconductor structure. performance.

Referring to FIG. 8 , in some embodiments, a filling layer 180 may also be included in the semiconductor structure. The filling layer 180 covers the top and side surfaces of the doped layer 120, the gate 130, the source and drain 150, the insulating layer 160 and other structures, and the top of the filling layer 180 covers the top of the gate 130 and the top of the source and drain 150. noodle. The filling layer 180 can make the semiconductor structure have higher mechanical strength, improve the stability of the semiconductor structure, and can protect components in the semiconductor structure from being damaged by the external environment.

In some embodiments, the material of the filling layer 180 may include one or more of silicon oxide or silicon nitride.

The semiconductor structure provided by the embodiments of the present disclosure includes a substrate; an oxide semiconductor layer is located on a part of the surface of the substrate, and the oxide semiconductor layer has doping ions for pinning oxygen vacancies; the doped layer is at least located on the oxide semiconductor layer Between the layer and the substrate, and the doped layer contains doping ions; the gate is located on the part of the surface of the oxide semiconductor layer away from the substrate; the source and drain doped regions are located in the oxide semiconductor layer on both sides of the gate. The carrier mobility in the semiconductor structure can be improved, and the performance of the semiconductor structure can be optimized.

Correspondingly, another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, reference may be made to the corresponding description of the foregoing embodiment, and details will not be described in detail below.

FIGS. 9 to 18 are structural schematic diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure, and FIGS. 9 to 18 are semiconductor structures corresponding to each step in the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure. Schematic diagram of the cross-sectional structure of the structure. It can be understood that the schematic cross-sectional structure does not show all structures in the semiconductor structure.

Referring to FIGS. 9 to 13 , a substrate 100 is provided.

In some embodiments, the step of forming the base 100 may include: providing an initial substrate 200; patterning a partial thickness of the initial substrate 200 to form at least one fin 102, and the remaining initial substrate under the at least one fin 102 The bottom 200 serves as a substrate 101 , and the substrate 101 and at least one fin 102 form the base 100 .

Specifically, the process of providing the base 100 including the substrate 101 and at least one fin 102 may be a self-aligned double patterning process (SADP, Self-aligned Double Patterning).

Referring to FIG. 9 , an initial substrate 200 is provided on which a protective layer 191 , a hard mask layer 192 , a sacrificial layer 193 , and a photoresist layer 194 are sequentially formed. Wherein, the material of the protection layer 191 may include silicon oxide, and the material of the hard mask layer 192 may include silicon nitride. The photoresist layer 194 covers part of the surface of the sacrificial layer 193 , and the photoresist layer 194 has a predetermined pattern therein.

Referring to FIG. 10 , the sacrificial layer 193 is etched using the photoresist layer 194 as a mask, so that the preset pattern in the photoresist layer 194 is transferred to the sacrificial layer 193 , and the photoresist layer 194 is removed after the etching is completed.

Referring to FIG. 11 , a mask layer 195 is formed covering the sides of the sacrificial layer 193 , and the sacrificial layer 193 is removed after the formation. Wherein, the method for forming the mask layer 195 may include: first forming the mask layer 195 on the surface of the hard mask layer 192 and the top surface and side surfaces of the sacrificial layer 193 by atomic layer deposition (ALD, Atomic layer deposition) , and then remove part of the mask layer 195 through an etch-back process, so that the remaining mask layer 195 only covers the side surface of the sacrificial layer 193 .

Referring to FIG. 12 , the hard mask layer 192 is etched using the mask layer 195 as a mask, and the mask layer 195 is removed after the etching is completed. At this time, the etching pattern in the hard mask layer 192 has a higher density than the preset pattern in the photoresist layer 194, which can make the fins 102 formed in subsequent steps have a higher density, and can further improve The contact area between the oxide semiconductor layer 110 and the gate 130 further improves the control ability of the gate 130 on the oxide semiconductor layer 110 , and further improves the performance of the semiconductor structure. The protective layer 191 located between the initial substrate 200 and the hard mask layer 192 can protect the initial substrate 200 and prevent over-etching when the hard mask layer 192 is etched using the mask layer 195 as a mask. In this case, the initial substrate 200 is damaged.

Referring to FIG. 13 , the protective layer 191 and the initial substrate 200 are etched using the hard mask layer 192 as a mask, so that the initial substrate 200 includes the substrate 101 and at least one fin 102 . Due to the influence of wet etching process properties, the initial substrate 200 close to the protective layer 191 contacts the etching environment before the initial substrate 200 away from the protective layer 191, and in the direction away from the substrate 101, the width of the fin portion 102 slowing shrieking.

Referring to FIG. 14, an initial isolation layer 270 is formed. The initial isolation layer 270 may cover the top surface of the substrate 101 , the sides of the fin 102 , and the sides of the protection layer 191 and the hard mask layer 192 . The material of the initial isolation layer 270 may include one or more of silicon nitride, silicon oxide, or silicon oxynitride.

Referring to FIG. 15, the hard mask layer, protective layer and part of the initial isolation layer are removed by etching to form an isolation layer. The isolation layer 170 can cover the top surface of the substrate and part of the side surfaces of the fins 102, and the top surface of the fins 102 is as high as on the top surface of the isolation layer 170. The isolation layer 170 can isolate the substrate 100 and the oxide semiconductor layer 110 , reduce the occurrence of electric leakage in the semiconductor structure, and improve the stability of the semiconductor structure.

In some embodiments, the hard mask layer 192 and the passivation layer 191 may also be removed before forming the isolation layer 170 .

Referring to FIG. 16, an oxide semiconductor layer 110 and a doped layer 120 are formed, the oxide semiconductor layer 110 is located on a part of the surface of the substrate 100, the doped layer 120 is located at least between the oxide semiconductor layer 110 and the substrate 100, and the doped layer 120 has dopant ions in it. The step of forming the oxide semiconductor layer 110 and the doped layer 120 may include: first forming the doped layer 120, the doped layer 120 covers at least part of the surface of the substrate 100, and the doped layer 120 may cover the entire top surface and side surfaces of the fin 102 Forming an oxide semiconductor layer 110 , the oxide semiconductor layer 110 covers a portion of the surface of the doped layer 120 away from the substrate 100 , and the oxide semiconductor layer 110 may span a plurality of fins 102 along a predetermined direction. Since the oxide semiconductor layer 110 does not cover the entire surface of the substrate 100, when forming the oxide semiconductor layer 110, an initial oxide semiconductor layer covering the entire surface of the substrate 100 can be formed first, and then part of the initial oxide semiconductor layer is removed to form oxide semiconductor layer 110 .

In some embodiments, before forming the gate 130 , it may further include: treating the surface of the oxide semiconductor layer 110 with a plasma treatment process. In this way, the number of oxygen vacancies serving as carrier migration tracks in the oxide semiconductor layer 110 can be increased, thereby increasing the carrier concentration and carrier mobility of the oxide semiconductor layer 110, so that the current carrying capacity of the semiconductor structure The ion mobility is increased, optimizing the performance of the semiconductor structure.

Referring to FIG. 17 , a gate electrode 130 is formed on a portion of the surface of the oxide semiconductor layer 110 away from the substrate 100 .

In some embodiments, a gate oxide layer 140 may be formed before forming the gate 130, the gate oxide layer 140 is located on a part of the surface of the oxide semiconductor layer 110 away from the substrate 100, and the gate 130 is located on a part of the gate oxide layer 140 away from the substrate 100. partly on the surface. The material of the gate oxide layer 140 may include silicon oxide or aluminum oxide, etc., and the gate oxide layer 140 can improve the electron conduction performance of the semiconductor structure.

Continuing to refer to FIG. 17 , source and drain doped regions 111 are formed in the oxide semiconductor 110 on both sides of the gate 130 . The source-drain doping region 111 needs to be doped. If N-type doping is required, N-type ions, such as nitrogen ions and phosphorus ions, can be implanted. If P-type doping is required, P-type ions such as boron ions and aluminum ions can be implanted.

Continuing to refer to FIG. 17 , an annealing treatment is performed, so that part of the dopant ions in the doped layer 120 diffuses into the oxide semiconductor layer 110 , and the dopant ions pin oxygen vacancies in the oxide semiconductor layer 110 . The pinning of oxygen vacancies in the oxide semiconductor layer 110 by the dopant ions may increase the number of oxygen vacancies serving as carrier migration tracks in the oxide semiconductor layer 110 , thereby increasing the carrier mobility of the semiconductor structure.

In some embodiments, the temperature of the annealing treatment may be 150°C-350°C. For example, the temperature of the annealing treatment may be 350°C, 320°C, 300°C, 290°C, 270°C, 250°C, 210°C, 200°C, 150°C or the like. If the temperature of the annealing treatment is too high, the carrier concentration in the oxide semiconductor layer 110 may decrease, affecting the performance of the semiconductor structure; if the temperature of the annealing treatment is too low, the dopant ions will be pinned in the oxide semiconductor layer 110 Oxygen vacancies may be less effective and the carrier mobility in the semiconductor structure remains low.

In some embodiments, the step of forming the source-drain doped region 111 and performing the annealing treatment may include: performing doping treatment on the oxide semiconductor layer 110 on opposite sides of the gate 130; after performing the doping treatment, performing an annealing treatment , so as to activate the ions in the doped layer 120 and diffuse part of the doped ions in the doped layer 120 into the oxide semiconductor layer 110 . The activated dopant ions in the doped layer 120 diffuse into the oxide semiconductor layer 110 to pin more oxygen vacancies, preventing the oxygen vacancies from disappearing in large quantities during annealing, thereby affecting the performance of the channel. Afterwards, these doped Ions may remain in the oxide semiconductor layer 110 .

Referring to FIG. 18 , in some embodiments, an insulating layer 160 and source and drain electrodes 150 may also be formed after annealing. The source and drain electrodes 150 are located on both sides of the gate 130 and the source and drain electrodes 150 are located on a part of the surface of the oxide semiconductor layer 110 away from the substrate 100 . The material of the source and drain electrodes 150 may include one or more of polysilicon or tungsten. The insulating layer 160 may be located between the gate 130 and the source and drain 150 , and the insulating layer 160 covers the sides of the gate 130 and the source and drain 150 . The insulating layer 160 can isolate the gate 130 and the source and drain 150 .

Continuing to refer to FIG. 18 , a filling layer 180 can also be formed. The filling layer 180 covers the top and side surfaces of structures such as the doped layer 120 , the gate 130 , the source and drain electrodes 150 , and the insulating layer 160 , and the top surface of the filling layer 180 covers The top surface of the gate 130 and the top surface of the source and drain 150 . The material of the filling layer 180 may include one or more of silicon oxide or silicon nitride.

In the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, a substrate is provided; an oxide semiconductor layer and a doped layer are formed, the oxide semiconductor layer is located on a part of the surface of the substrate, and the doped layer is at least located between the oxide semiconductor layer and the substrate , and there are dopant ions in the doped layer; forming a gate, located on a part of the surface of the oxide semiconductor layer away from the substrate; forming a source-drain doped region, located in the oxide semiconductor layer on both sides of the gate; performing annealing treatment, Part of the dopant ions in the doped layer are diffused into the oxide semiconductor layer, and the doping is used to pin oxygen vacancies in the oxide semiconductor layer. The carrier mobility in the semiconductor structure can be improved, and the performance of the semiconductor structure can be optimized.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and spirit of the present disclosure. scope. Any person skilled in the art can make respective alterations and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined in the claims.

Claims (10)

1. A semiconductor structure, comprising:

a substrate;

an oxide semiconductor layer on a part of a surface of the substrate, the oxide semiconductor layer having a dopant ion therein for pinning oxygen vacancies;

a doped layer at least between the oxide semiconductor layer and the substrate, wherein the doped layer is provided with doped ions;

a gate electrode on a portion of a surface of the oxide semiconductor layer remote from the substrate;

and the source-drain doped region is positioned in the oxide semiconductor layer at two sides of the grid electrode.

2. The semiconductor structure of claim 1, wherein the dopant ions comprise one or more of fluoride ions or hydrogen ions.

3. The semiconductor structure of claim 1, wherein the material of the doped layer comprises silicon nitride.

4. The semiconductor structure of claim 1, wherein the doped layer has a thickness of 10nm-30nm.

5. The semiconductor structure of any one of claims 1 to 4, wherein the substrate comprises: the semiconductor device comprises a substrate and at least one fin part positioned on the substrate, wherein an isolation layer covering the side surface of the fin part is further arranged on the substrate, and the top surface of the fin part is higher than the top surface of the isolation layer; the oxide semiconductor layer is at least located on the top surface of the fin portion and on the side surface higher than the isolation layer, and the doped layer is located on the top and the side surface of the fin portion.

6. The semiconductor structure of claim 5, wherein the at least one fin comprises a plurality of fins arranged at intervals along a predetermined direction; the oxide semiconductor layer and the gate electrode cross the fin portions along the preset direction.

7. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming an oxide semiconductor layer and a doped layer, wherein the oxide semiconductor layer is positioned on part of the surface of the substrate, the doped layer is positioned at least between the oxide semiconductor layer and the substrate, and doped ions are arranged in the doped layer;

forming a gate electrode on a portion of the surface of the oxide semiconductor layer remote from the substrate;

forming source-drain doped regions in the oxide semiconductor layer at two sides of the grid electrode;

an annealing treatment is performed so that a part of the dopant ions in the doped layer is diffused into the oxide semiconductor layer, and the doping is used for pinning oxygen vacancies in the oxide semiconductor layer.

8. The method of manufacturing of claim 7, further comprising, prior to forming the gate:

and treating the surface of the oxide semiconductor layer by adopting a plasma treatment process.

9. The method of manufacturing according to claim 7, wherein the step of forming the substrate includes:

providing an initial substrate;

patterning the initial substrate with partial thickness to form at least one fin portion, wherein the rest initial substrate below the at least one fin portion is used as a substrate, and the substrate and the at least one fin portion form the base.

10. The method of manufacturing of claim 7, wherein the steps of forming the source drain doped regions and performing the annealing treatment comprise: doping the oxide semiconductor layers on two opposite sides of the grid electrode; after the doping treatment is performed, the annealing treatment is performed to activate ions in the doped layer and diffuse a part of the doped ions in the doped layer into the oxide semiconductor layer.

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