CN116359713A - Chip testing system, device, chip and testing method thereof - Google Patents

Abstract

The embodiment of the disclosure provides a chip testing system, a device, a chip and a testing method thereof. The chip test system comprises a chip and a chip test device. The chip is provided with a second microstrip antenna; chip testing device, comprising: the probe card is arranged at intervals with the chip and is opposite to the chip; the first microstrip antenna is arranged on the probe card and is used for sending a test signal to the second microstrip antenna; the second microstrip antenna is used for receiving the test signal, acquiring test information from the chip according to the test signal, returning a signal to be tested containing the test information to the first microstrip antenna, and the first microstrip antenna is also used for receiving the signal to be tested. The chip testing system of the embodiment of the disclosure can avoid damage to the metal pad, so that subsequent packaging is smoothly performed, and the cost is reduced.

Description

Chip testing system, device, chip and testing method thereof

Technical Field

The present disclosure relates to the field of semiconductor testing technologies, and in particular, to a chip testing system, a device, a chip, and a testing method thereof.

Background

After the chips are formed on the wafer, the chips on the wafer are tested. Typically, a metal Pad (Pad) is formed on the surface of each chip on the wafer, and during testing, the wafer is placed on a probe station, a tester is connected to a probe card, probes are provided on the probe card, the probes are pricked on the metal pads on the chips, and information of chip testing can be obtained through the probes.

Because the probes need to be pricked into the metal pads, damage can be caused to the metal pads, so that subsequent packaging has the risk of damage. And for different products, the positions of the metal pads are different, and different probe cards need to be replaced, so that the testing cost is increased.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and thus it may include information that does not form a related art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The embodiment of the disclosure provides a chip testing system, a device, a chip and a testing method thereof, which can avoid damage to a metal pad, enable subsequent packaging to be carried out smoothly, reduce cost and improve accuracy of signal transmission.

The embodiment of the disclosure provides a chip testing system, which comprises a chip and a chip testing device. The chip is provided with a second microstrip antenna; the chip testing device comprises a probe card and a first microstrip antenna. The probe card is spaced from the chip and is arranged opposite to the chip; the first microstrip antenna is arranged on the probe card and is used for sending a test signal to the second microstrip antenna; the second microstrip antenna is used for receiving the test signal, acquiring test information from the chip according to the test signal, returning a signal to be tested containing the test information to the first microstrip antenna, and the first microstrip antenna is also used for receiving the signal to be tested.

In some embodiments of the present disclosure, the chip has a semiconductor device and a first lead inside, the first lead is electrically connected to the semiconductor device, a metal pad is disposed on the chip, and the metal pad is electrically connected to the first lead.

In some embodiments of the disclosure, the second microstrip antenna is disposed on one side of the metal pad and is electrically connected to the metal pad; and/or the second microstrip antenna is arranged on the surface of the chip or inside the chip.

In some embodiments of the disclosure, the second microstrip antenna is disposed on the metal pad; or, the chip further includes a circuit protection layer, the circuit protection layer is located at an edge of the chip, and the second microstrip antenna is disposed on the circuit protection layer and is electrically connected with any one of the metal pad, the first lead and the semiconductor device through a second lead.

In some embodiments of the present disclosure, the chip has a plurality of the chip stacks such that the second microstrip antenna stack is located in the chip or in the metal pad.

In some embodiments of the present disclosure, a rectifying circuit is further disposed in the chip, and the rectifying circuit is electrically connected to the second microstrip antenna, and is configured to convert the test signal received by the second microstrip antenna into a first current signal, and obtain, according to the first current signal, a current signal of test information of the chip, where the rectifying circuit is further configured to convert the current signal of the test information into the signal to be tested, and transmit the signal to be tested to the second microstrip antenna.

In some embodiments of the disclosure, the chip testing device further includes a testing machine electrically connected to the first microstrip antenna, the testing machine is configured to send a control signal to the first microstrip antenna, so that the first microstrip antenna sends the test signal to the second microstrip antenna, and after the first microstrip antenna receives the signal to be tested, the first microstrip antenna is configured to send the signal to be tested to the testing machine.

The embodiment of the disclosure also provides a chip testing device, which comprises: the probe card is arranged at intervals and opposite to the chip, and the chip is provided with a second microstrip antenna; the first microstrip antenna is arranged on the probe card and is used for sending a test signal to the second microstrip antenna so that the second microstrip antenna can receive the test signal conveniently, test information is acquired from the chip according to the test signal, and the first microstrip antenna is also used for receiving a signal to be tested containing the test information, which is returned by the second microstrip antenna.

The embodiment of the disclosure also provides a chip which is arranged at intervals and opposite to the probe card, wherein the probe card is provided with a first microstrip antenna; the chip comprises a second microstrip antenna, wherein the second microstrip antenna is used for receiving the test signal sent by the first microstrip antenna and acquiring test information from the chip so as to send the signal to be tested containing the test information to the first microstrip antenna.

The embodiment of the disclosure also provides a chip testing method applied to the chip testing system described in any one of the embodiments, the method comprising: transmitting a test signal from the first microstrip antenna to the second microstrip antenna; the second microstrip antenna receives the test signal, acquires test information from the chip according to the test signal, and returns a signal to be tested containing the test information to the first microstrip antenna; the first microstrip antenna receives the signal to be detected so as to analyze the signal to be detected.

According to the technical scheme, the chip testing system of the embodiment of the disclosure has at least one of the following advantages and positive effects:

in the embodiment of the disclosure, the first microstrip antenna is arranged on the probe card, the second microstrip antenna is arranged on the chip, and the first microstrip antenna and the second microstrip antenna can realize radio connection and mutually transmit signals so as to realize the test of the chip, so that a probe is not required to be pricked into a metal pad to obtain test information, damage to the metal pad is avoided, and subsequent packaging can be smoothly carried out. Although the products are different so that the positions of the chips are different, the probe card can be omitted because the two microstrip antennas are in radio connection, and therefore, the cost is reduced.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a schematic diagram of a chip testing system shown in some embodiments of the present disclosure;

FIG. 2 is a schematic top view of a chip shown in some embodiments of the disclosure;

fig. 3 is a schematic perspective view of a first microstrip antenna or a second microstrip antenna according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a chip testing system shown in some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of the internal structure of a chip shown in some embodiments of the disclosure;

FIG. 6 is a schematic diagram of a chip stack test shown in some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of a chip test system with a rectifying circuit shown in some embodiments of the present disclosure;

FIG. 8 is a schematic diagram of a chip testing system shown in some embodiments of the present disclosure;

FIG. 9 is a schematic diagram of a test shown in some embodiments of the present disclosure;

fig. 10 is a flow chart of a chip testing method shown in some embodiments of the present disclosure.

Reference numerals illustrate:

1. a probe card; 11. a PCB; 10. a test head; 2. a chip; 20. a wafer; 21. a circuit protection layer; 22. a metal pad; 23. a rectifying circuit; 231. a power rectifier; 24. a via hole; 25 a first lead; 26. a semiconductor device; 27. a second lead; 28. a third lead; 3. a first microstrip antenna; 4. a second microstrip antenna; 41. a ground plate; 42. a dielectric substrate; 43. a conductor patch; 44. a wiring layer; 5. a test machine; 6. a probe station; d. testing the spacing; x, horizontal direction; y, vertical direction.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.

In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of examples in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not intended to limit the numerals of their objects.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.

In the process of wafer, a large number of chips are formed on the wafer, and the chips on the wafer need to be tested for electrical performance before dicing and packaging the wafer. In the test stage, metal pads are typically formed on the chip in advance, and the metal pads are connected to leads inside the chip to provide electrical paths to external components. During testing, the wafer is placed on the probe station, the tester is connected with the probe card, the probe card is provided with probes, and the probes are pricked on the metal pads on the chip so as to realize the electric connection between the probes and the inside of the chip. After connection, the tester tests the electrical properties of the chip via the probes.

However, since the chip is not packaged, the probe may damage the metal pad, which may affect the subsequent packaging, resulting in abnormal packaging rate. Different semiconductor products, the distribution position of the chip on the wafer is different, the position of the metal pad is also different, and different probe cards need to be replaced to test different products, and the probe cards are expensive in manufacturing cost, so that the testing cost is increased, and the testing efficiency is reduced.

Based on this, the embodiment of the disclosure provides a chip test system. As shown in fig. 1, the chip test system includes a chip test apparatus and a chip 2. Wherein the chip 2 is provided with a second microstrip antenna 4.

The chip testing device comprises a probe card 1 and a first microstrip antenna 3. The probe card 1 is spaced from and disposed opposite the chip 2.

The Probe Card 1 (Probe Card) is an interface for electrically testing chips on a wafer before a large-scale integrated circuit is packaged, and is widely used for wafer testing of chip products such as memory, logic, driving, communication and the like. The probe card is provided with a PCB11 (Printed Circuit Board ), and the first microstrip antenna 3 is arranged on the PCB 11. As shown in fig. 8, the probe card 1 is electrically connected to the test head 10.

The chip 2 refers to a chip that is not yet divided on a wafer (wafer). The chip may be, for example, a DRAM (dynamic random access memory ) or the like, and is not particularly limited herein. Before packaging, the chip 2 needs to be tested for electrical performance so as to remove the chip failed in test in advance, avoid packaging the chip and save the process and the cost. As shown in fig. 8, the chip 2 is placed on the probe stage 6 before the test.

The microstrip antenna (Microstrip antenna) is an antenna which is formed by attaching a metal thin layer as a grounding plate on one surface of a thin dielectric substrate, manufacturing a metal patch with a certain shape on the other surface by a photoetching method, and feeding the patch by utilizing a microstrip line or a coaxial probe.

In the embodiment of the present disclosure, as shown in fig. 3, the microstrip antenna includes a wiring layer 44, a conductor patch 43, a dielectric substrate 42, and a ground plate 41. The wiring layer 44 is disposed on the conductor patch 43, the conductor patch 43 is disposed on the dielectric substrate 42, and the dielectric substrate 42 is disposed on the ground plate 41. The wiring layer 44 is provided with an antenna for transmitting or receiving a test signal, the wiring layer 44 includes a plurality of substantially U-shaped units, the plurality of U-shaped units are arranged in parallel, and the top ends of the plurality of U-shaped units are connected to the top ends of adjacent U-shaped units, so that the wiring layer 44 is formed to include a plurality of repeating units, and the arrangement is favorable for stability of signal transmission. The microstrip antenna is electrically connected to the chip 2 by its ground plane 41.

In some embodiments, as shown in fig. 1, a first microstrip antenna 3 is provided on the probe card 1, and as shown in fig. 1 and 4, a second microstrip antenna 4 is provided on the chip 2, and is in radio connection with the first microstrip antenna 3. Wherein the first microstrip antenna 3 is used for transmitting a test signal to the second microstrip antenna 4. The second microstrip antenna 4 is configured to receive a test signal, obtain test information from the chip 2 according to the test signal, and return a signal to be tested including the test information to the first microstrip antenna 3, where the first microstrip antenna 3 is further configured to receive the signal to be tested.

As shown in fig. 5, the chip of the embodiment of the present disclosure has a semiconductor device 26 and a first lead 25, the first lead 25 is electrically connected to the semiconductor device 26, a metal pad 22 is provided on the chip 2, and the metal pad 22 is electrically connected to the first lead 25.

Specifically, as shown in fig. 5, in the process of preparing the chip 2, after forming the semiconductor device 26 in the chip 2, a dielectric layer is formed on the semiconductor device 26, holes are etched in the dielectric layer to form the via holes 24, in some embodiments, two ends of the via holes 24 may extend to the semiconductor device 26 and the portion where the metal pad 22 is formed, respectively, and the via holes 24 may be filled with a metal conductive material to form the conductive first lead 25, and then a metal layer is deposited at the portion where the metal pad 22 is formed to form the metal pad 22, so that the metal pad 22 is electrically connected to the semiconductor device 26 through the first lead 25 located in the via holes 24. The semiconductor device 26 may be a transistor, a capacitor, or the like, and is not particularly limited herein.

In some embodiments, the second microstrip antenna 4 is disposed on one side of the metal pad 22 and is electrically connected to the metal pad 22.

Specifically, the second microstrip antenna 4 may be disposed on any one side around the metal pad 22, and as shown in fig. 2, since the lower side of the metal pad 22 has sufficient space, the second microstrip antenna 4 may be disposed on the lower side of the metal pad 22. Of course, the second microstrip antenna 4 may also be provided on the upper, left and right sides of the metal pad 22 as in fig. 2. In some embodiments, the second microstrip antenna 4 may be further disposed on any two sides, three sides or all around the metal pad 22, so long as there is sufficient space for disposing the second microstrip antenna 4, and electrical connection between the second microstrip antenna 4 and the metal pad 22 can be achieved, which is not particularly limited herein. Since the metal pad 22 is electrically connected to the first lead 25 located inside the chip 2, the first lead 25 is electrically connected to the semiconductor device 26, and thus, if the second microstrip antenna 4 is connected to the metal pad 22, the second microstrip antenna 4 can be electrically connected to the semiconductor device 26, so that the second microstrip antenna 4 can obtain information to be measured of the semiconductor device 26.

In some embodiments, the second microstrip antenna 4 is provided on the surface of the chip or inside the chip.

A wafer 20 includes a plurality of chips 2 arranged side by side, and if the chips 2 on the wafer 20 are tested, the second microstrip antenna 4 may be disposed on the surface of the chips 2. For example, a separate second microstrip antenna 4 is prepared by a processing process, and the second microstrip antenna 4 is adhered to the surface of the chip 2 by a conductive adhesive. The conductive paste may extend to the metal pad 22 so that the second microstrip antenna 4 is electrically connected to the metal pad 22.

Of course, in some embodiments, the second microstrip antenna 4 may also be provided inside the chip 2. The second microstrip antenna 4 may be provided in a recess formed on the chip 2 by an etching process, the second microstrip antenna 4 may be fixed in the recess by, for example, a conductive adhesive, and the second microstrip antenna 4 may be electrically connected to the metal pad 22 or the first lead 25.

The second microstrip antenna 4 may also be directly formed inside the chip 2 (e.g. inside the chip 2 where the second microstrip antenna 4 is located in fig. 2) by an etching process, i.e. the second microstrip antenna 4 does not protrude from the surface of the wafer 20. As shown in fig. 5, in the process of manufacturing the chip, after the semiconductor device 26 and the first lead 25 are formed, the functional layer inside the chip 2 is etched by an etching process, and may include a plurality of layers formed by a deposition process, and the materials of the plurality of layers correspond to the materials of the wiring layer 44, the conductor patch 43, the dielectric substrate 42, and the ground plate 41 in the microstrip antenna. The functional layer is etched on the premise that other structures inside the chip 2 are not affected. The person skilled in the art can adjust the parameters of the etching process according to the structure and dimensions of the second microstrip antenna 4 to form the final desired second microstrip antenna 4. For example, a photolithography process may be used when forming the wiring layer 44, and a dry etching process or a wet etching process may be used when forming the conductor patch 43, the dielectric substrate 42, and the ground plate 41.

The dry etching process can be a plasma etching process, the etching gas adopted in the plasma etching process can be chlorine, the etching degree can be controlled by controlling the using amount of the etching gas, the etching size can be accurately controlled by the plasma etching process, and the accurate anisotropic etching can be realized. The wet etching process can use hydrofluoric acid and hydrogen peroxide as etchants, and the etching degree can be controlled by adjusting the concentration of the etchants, so that a person skilled in the art can select the etching process according to actual conditions, and the etching process is not particularly limited.

In some embodiments, the first microstrip antenna 3 and the second microstrip antenna 4 have dimensions of 60 μm to 120 μm. Specifically, the above-mentioned two end values may be 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 115 μm, and the present invention is not particularly limited.

In some embodiments, as shown in fig. 5, the chip 2 further includes a circuit protection layer 21, the circuit protection layer 21 is located at an edge of the chip 2, and the second microstrip antenna 4 is disposed on the circuit protection layer 21 and is electrically connected to any one of the metal pad 22, the first lead 25, and the semiconductor device 26 through the second lead 27.

As shown in fig. 2, the circuit protection layer 21 is located around the chip 2, and plays a role in protecting the chip 2, and the second microstrip antenna 4 is disposed in the circuit protection layer 21, so that an influence on the internal structure of the chip 2 can be avoided.

As shown in fig. 5, when the second microstrip antenna 4 is provided on the circuit protection layer 21, since it is far from the metal pad 22, a second lead 27 may be provided between the metal pad 22 and the second microstrip antenna 4, and the electrical connection between the metal pad 22 and the second microstrip antenna 4 may be achieved through the second lead 27. When the second microstrip antenna 4 is disposed on the surface of the circuit protection layer 21, the second lead 27 may be a metal wire or a metal block, or may be conductive adhesive. When the second microstrip antenna 4 is disposed inside the circuit protection layer 21, a second lead 27 may be disposed inside the circuit protection layer 21, and the second lead 27 may be connected to the metal pad 22, or may be connected to the first lead 25, or may be directly connected to the semiconductor device 26, so that the second microstrip antenna 4 may be electrically connected to the semiconductor device 26, and further may obtain test information of the semiconductor device 26.

In some embodiments, a multi-layered wire may be included, as shown in fig. 5, with a third wire 28 also formed under the first wire 25, the third wire 28 being electrically connected to the semiconductor device 26 and the first wire 25 to make electrical connection of the first wire 25 to the semiconductor device 26.

In some embodiments, the second microstrip antenna 4 may be disposed on one side of the protection circuit layer 21, or may be disposed on two sides, three sides or around the protection circuit layer 21, which may be selected by a person skilled in the art according to the number of the second microstrip antennas 4 and the test position of the chip 2, and is not limited herein.

In some embodiments, the second microstrip antenna 4 may be a separate antenna element manufactured by a processing process, and the second microstrip antenna 4 may be provided on the surface of the circuit protection layer 21 of the chip 2 by means of conductive adhesive bonding or the like, or provided inside the circuit protection layer 21, for example, by etching a groove in the circuit protection layer 21 by an etching process, and embedding the second microstrip antenna 4 into the groove.

In the above-described embodiments, the two cases where the second microstrip antenna 4 is provided on the surface of the chip or the inside of the chip, i.e., one is provided on the surface of the chip 2 closer to the metal pad 22 or the inside, and the other is provided on the surface of the circuit protection layer 21 of the chip 2 farther from the metal pad 22.

In some embodiments, the second microstrip antenna 4 may also be provided on the metal pad 22.

In some embodiments, the second microstrip antenna 4 may be disposed on a surface of the metal pad 22, and the second microstrip antenna 4 may be connected to the surface of the metal pad 22, for example, by using a conductive adhesive, so that the second microstrip antenna 4 is electrically connected to the metal pad 22.

In some embodiments, a groove may be etched in the metal pad 22 using an etching process, and the second microstrip antenna 4 may be fixed in the groove by a conductive adhesive so that the second microstrip antenna 4 can be electrically connected to the metal pad 22, and the second microstrip antenna 4 may be exposed from the metal pad 22 to communicate with the outside. In other embodiments, the second microstrip antenna 4 may also be etched directly into the metal pad 22. The material of the metal pad 22 is the same as that of the second microstrip antenna 4, and the internal structure of the chip 2 is not affected during the etching process. The etching process is the same as that of the second microstrip antenna 4 formed inside the chip 2 in the above embodiment, and will not be described here again.

In some embodiments, as shown in fig. 1, multiple chips 2 in a single layer wafer 20 may be tested. The second microstrip antenna 4 is located in the circuit protection layer 21 or the metal pad 22 and does not protrude from the surface of the wafer 20. In such a single-layer wafer 20 test, the second microstrip antenna 4 may also be located on the circuit protection layer 21 or the metal pad 22 and protrude from the surface of the wafer 20.

In some embodiments, with continued reference to fig. 1, the die 2 has a plurality of dies 2 on the same wafer 20, and the distance between the second microstrip antennas 4 on adjacent dies 2 is 30 μm to 60 μm.

Specifically, the distance between the second microstrip antennas 4 on the adjacent chips 2 may be 40 μm, 45 μm, 50 μm, 55 μm in addition to the above two end values, and those skilled in the art may set according to actual test conditions, and is not particularly limited herein. The distance between the second microstrip antennas 4 on the adjacent chips 2 is set to be the above value, which is favorable for accurately transmitting the wireless signals transmitted by the second microstrip antennas 4 to the corresponding first microstrip antennas 3, and ensures the accuracy of the test results.

In some embodiments, the chip 2 has a plurality of chips 2 stacked such that the second microstrip antenna 4 located in the chip 2 or in the metal pad 22 is stacked.

As shown in fig. 6, since the first microstrip antenna 3 and the second microstrip antenna 4 of the embodiment of the present disclosure are wirelessly connected, the second microstrip antenna 4 can be disposed inside the wafer 20, i.e. not protruding from the surface of the wafer 20, so that a plurality of wafers 20 can be stacked for testing at the same time. A plurality of first microstrip antennas 3 are provided on the probe card 1 in one-to-one correspondence with the second microstrip antennas 4 to receive signals. Thus, the non-contact testing mode after stacking the wafers 20 is realized, the testing efficiency can be improved, and the surface of the chip 2 is not damaged.

As shown in fig. 1, a first microstrip antenna 3 is provided to the probe card 1. The first microstrip antenna 3 may be disposed on a surface of the probe card 1 facing the chip 2, or may be disposed inside the probe card 1, for example, by adhering the first microstrip antenna 3 to the probe card 1 through conductive adhesive, so as to electrically connect the first microstrip antenna 3 with a circuit of the probe card 1. The first microstrip antenna 3 is in one-to-one correspondence with the second microstrip antenna 4, that is, the first microstrip antenna 3 transmits a wireless signal to the second microstrip antenna 4 corresponding thereto or receives a wireless signal transmitted by the second microstrip antenna 4 corresponding thereto.

The structure of the first microstrip antenna 3 may be identical to or different from the structure of the second microstrip antenna 4, and the volume of the first microstrip antenna 3 may be set to be larger than that of the second microstrip antenna 4, so that the first microstrip antenna 3 may be manufactured and the first microstrip antenna 3 may receive a wireless signal sent by the second microstrip antenna 4, that is, as long as the first microstrip antenna 3 and the second microstrip antenna 4 corresponding to the first microstrip antenna 3 may implement wireless transmission, which is not limited herein.

In some embodiments, as shown in FIG. 1, the test pitch d between the probe card 1 and the chip 2 is 30 μm to 60 μm

Specifically, the test pitch d between the probe card 1 and the chip 2, i.e., the distance by which the probe card 1 and the chip 2 are spaced in the vertical direction Y, can also be understood as the distance between the first microstrip antenna 3 and the second microstrip antenna 4 in the vertical direction Y. As shown in fig. 1, the first microstrip antenna 3 and the second microstrip antenna 4 are disposed in one-to-one correspondence, and the distance therebetween may be 40 μm, 45 μm, 50 μm, or 55 μm in addition to the above two end values, and may be set by those skilled in the art according to actual test conditions, which is not particularly limited herein. By setting the distance between the first microstrip antenna 3 and the second microstrip antenna 4 to the above value, it is possible to ensure that the second microstrip antenna 4 and the first microstrip antenna 3 smoothly transmit wireless signals, and when the wireless signals transmitted by the second microstrip antenna 4 are inclined in the vertical direction Y, they can be smoothly received by the first microstrip antenna 3, so as to ensure the integrity of signal transmission.

In some embodiments, the frequency band of the wireless signal transmitted between the first microstrip antenna 3 and the second microstrip antenna 4 is 5GHz to 10GHz.

Specifically, in addition to the above two end values, 6GHz, 7GHz, 8GHz, 9GHz may be used, and the present invention is not limited thereto. By setting the wireless signal to be transmitted in the above frequency band, smooth transmission of the signal between the second microstrip antenna 4 and the first microstrip antenna 3 corresponding thereto can be ensured, ensuring accurate transmission of the wireless signal.

In some embodiments, the gain decibel value between the first microstrip antenna 3 and the second microstrip antenna 4 is-56 dB to-32 dB.

Specifically, the gain decibel values between the first microstrip antenna 3 and the second microstrip antenna 4 may be-55 dB, -50dB, -44dB, -35dB in addition to the above two end values, and are not particularly limited here. The gain decibel values of the first microstrip antenna 3 and the second microstrip antenna 4 are set to the values, so that the signal receiving capability of the first microstrip antenna 3 can be improved, the signal to noise ratio is improved, and the signal is ensured to be accurately received. Moreover, the larger the gain decibel value (the larger the absolute value), the stronger the capability of receiving the signal and the higher the signal-to-noise ratio.

In the above embodiment, by setting the distance between the first microstrip antenna 3 and the second microstrip antenna 4, the distance between the adjacent second microstrip antennas 4 on the same wafer 20, the frequency band of wireless signal transmission, the effective lengths L of the first microstrip antenna 3 and the second microstrip antenna 4, and the gain decibel values between the first microstrip antenna 3 and the second microstrip antenna 4, it is possible to ensure that the second microstrip antenna 4 is in radio connection with the first microstrip antenna 3 in one-to-one correspondence, and ensure accurate transmission of signals.

In some embodiments, as shown in fig. 7, a rectifying circuit 23 is further disposed in the chip 2, and the rectifying circuit 23 is electrically connected to the second microstrip antenna 4 and is configured to convert a test signal received by the second microstrip antenna 4 into a first current signal, obtain a current signal of information to be tested of the chip 2 according to the first current signal, and the rectifying circuit 23 is further configured to convert the current signal of the test information into the signal to be tested and transmit the signal to be tested to the second microstrip antenna 4.

As shown in fig. 7, the rectifying circuit 23 includes a power rectifier (Power rectifier circuits) 231, the power rectifier 231 may be electrically connected to the ground plane 41 of the second microstrip antenna 4, when the first microstrip antenna 3 sends a test signal to the second microstrip antenna 4, the second microstrip antenna 4 receives the test signal, the test signal is in the form of Radio Frequency (RF), the test signal is transmitted to the power rectifier 231 in the rectifying circuit 23 through the second microstrip antenna 4, the power rectifier 231 converts the test signal into a first current signal, the current signal of the test information of the semiconductor device 26 is obtained through the metal pad 22 or the first lead 25 in the chip 2 and is transmitted to the power rectifier 231, and the current signal of the test information is rectified by the power rectifier 231, so that the current signal of the test information is converted into a signal to be tested in the form of Radio Frequency and is transmitted to the first microstrip antenna 3. Through the rectification circuit 23, the wireless signal and the current signal can be mutually converted, and the accuracy of transmission between the signals is ensured.

In some embodiments, as shown in fig. 8, the chip test system further includes a test board 5, where the test board 5 is electrically connected to the first microstrip antenna 3, the test board 5 is configured to send a control signal to the first microstrip antenna 3, so that the first microstrip antenna 3 sends a test signal to the second microstrip antenna 4, and after the first microstrip antenna 3 receives the signal to be tested, the first microstrip antenna 3 is configured to send the signal to be tested to the test board 5.

As shown in fig. 8, the test machine 5 is used for performing test analysis on the chip 2. As shown in fig. 9, after the first microstrip antenna 3 receives the control signal sent by the test machine 5, a test signal is sent to the second microstrip antenna 4, after the second microstrip antenna 4 receives the test signal, test information is obtained from the chip 2, a signal to be tested containing the test information is sent back to the first microstrip antenna 3, after the first microstrip antenna 3 receives the signal to be tested sent back by the second microstrip antenna 4, the signal to be tested containing the test information is transmitted to the test machine 5, so that the test machine 5 analyzes the signal to be tested to test the chip 2. Specifically, the probe card 1 is electrically connected to the test head 10, and the test head 10 is electrically connected to the test machine 5, so as to transmit the signal to be tested received by the first microstrip antenna 3 to the test machine 5 through the test head 10.

Before testing, the wafer 20 containing the chips 2 is placed on the probe stage 6, and the probe stage 6 is lifted to a preset height, so that a test space d is provided between the first microstrip antenna 3 on the probe card 1 and the surface of the wafer 20. During testing, the test machine 5 is opened, the first microstrip antenna 3 and the second microstrip antenna 4 can be started at the same time, a control signal is sent to the first microstrip antenna 3 through the test machine 5, the first microstrip antenna 3 can send a test signal to the second microstrip antenna 4, after the second microstrip antenna 4 receives the test signal, test information can be obtained from the chip 2, a signal to be tested containing the test information is sent to the first microstrip antenna 3, the first microstrip antenna 3 transmits the signal to be tested to the test machine 5, and the test machine 5 analyzes the test information in the signal to be tested to realize testing of the chip 2.

After the test is finished, the qualified chip 2 is packaged. Since the second microstrip antenna 4 cannot be started at this time, the second microstrip antenna 4 in the chip 2 does not have any influence on the chip 2, and normal use of the chip 2 is ensured.

In summary, in the chip test system provided in the embodiment of the present disclosure, by disposing the first microstrip antenna 3 on the probe card 1 and disposing the second microstrip antenna 4 on the chip 2, the first microstrip antenna 3 and the second microstrip antenna 4 may realize radio connection and mutually transmit signals, so as to realize a test on the chip 2, so that a probe does not need to be pricked into the metal pad 22 to obtain test information, damage to the metal pad 22 is avoided, so that subsequent packaging can be performed smoothly, and the abnormal packaging rate is reduced; although the product is different so that the positions of the chips are different, the probe card 1 can be not required to be replaced because the two antennas are in radio connection, thereby reducing the cost; in addition, in the embodiment of the disclosure, the wafer can be stacked and then tested, and the probe card 1 does not need to be preheated during testing, so that the testing efficiency is improved; because the probe is not needed, the periodic cleaning treatment of the probe is avoided, the labor and time cost are saved, the damage to the probe card 1 caused by long-term contact of the probe with the wafer is avoided, and the service life of the probe card 1 is prolonged.

The embodiment of the disclosure also provides a chip testing device. As shown in fig. 1, the chip test apparatus includes a probe card 1 and a first microstrip antenna 3. The probe card 1 is spaced from and opposite to the chip 2, and the chip 2 is provided with a second microstrip antenna 4. The first microstrip antenna 3 is arranged on the probe card 1, the first microstrip antenna 3 is used for sending a test signal to the second microstrip antenna 4 so that the second microstrip antenna 4 can receive the test signal, test information can be obtained from the chip 2 according to the test signal, and the first microstrip antenna is also used for receiving a signal to be tested containing the test information, which is returned by the second microstrip antenna 4.

The chip testing device may be a chip testing device in the chip testing system in any of the above embodiments, and for other structures of the chip testing device, reference may be made to the chip testing device described in any of the above embodiments, which is not described herein again.

According to the chip testing device in the embodiment of the disclosure, the first microstrip antenna 3 is arranged on the probe card 1, and is in wireless connection with the second microstrip antenna 4 arranged on the chip 2 and mutually transmits signals, so that the chip 2 is tested, a probe does not need to be pricked into the metal pad 22 to obtain testing information, damage to the metal pad 22 is avoided, subsequent packaging can be smoothly performed, and abnormal packaging rate is reduced; although the product is different so that the positions of the chips are different, the probe card 1 can be not required to be replaced because the two antennas are in radio connection, thereby reducing the cost; in addition, the probe card 1 does not need to be preheated during the test, so that the test efficiency is improved; because the probe is not needed, the periodic cleaning treatment of the probe is avoided, the labor and time cost are saved, the damage to the probe card 1 caused by long-term contact of the probe with the wafer is avoided, and the service life of the probe card 1 is prolonged.

The disclosed embodiment also provides a chip 2, as shown in fig. 1, where the chip 2 is spaced from and disposed opposite to the probe card 1, and the probe card 1 is provided with a first microstrip antenna 3. The chip 2 includes a second microstrip antenna 4, and the second microstrip antenna 4 is configured to receive the test information sent by the first microstrip antenna 3, and obtain the test information from the chip 2, so as to send a signal to be tested including the test information to the first microstrip antenna 3.

In some embodiments, as shown in fig. 7, the chip 2 further includes a rectifying circuit 23, configured to convert the test signal received by the second microstrip antenna 4 into a first current signal, and obtain a current signal of the test information of the chip 2 according to the first current signal, where the rectifying circuit 23 is further configured to convert the current signal of the test information into a signal to be tested, and transmit the signal to be tested to the second microstrip antenna 4.

As shown in fig. 7, the rectifier circuit 23 includes a power rectifier (Power rectifier circuits) 231, which can convert the wireless signal and the current signal to each other, and the accuracy of the transmission between the signals can be ensured by the rectifier circuit 23.

In some embodiments, as shown in fig. 1 and 2, the edge of the chip 2 has a circuit protection layer 21, and the second microstrip antenna 4 is disposed in the circuit protection layer 21. As shown in fig. 2, the protection circuit layer 21 is located around the chip 2, and protects the chip 2, and the circuit protection layer 21 does not contain any internal structure of the chip. The second microstrip antenna 4 is provided in the circuit protection layer 21, and thus, the influence on the internal structure of the chip can be avoided.

The chip 2 may be the chip 2 in the chip test system in any of the above embodiments, and for other structures of the chip 2, reference may be made to the chip 2 described in any of the above embodiments, which is not described herein.

As shown in fig. 10, the embodiment of the present disclosure further provides a chip testing method, which is applied to the chip testing system of any one of the above embodiments. The method comprises the following steps S101 to S103.

S101: the first microstrip antenna 3 is caused to transmit a test signal to the second microstrip antenna 4.

The wafer 20 containing the chips 2 is placed on the probe stage 6, and the probe stage 6 is raised to a predetermined height so that a test space d is provided between the first microstrip antenna 3 on the probe card 1 and the surface of the wafer 20. When the test starts, the test machine 5 is turned on, and the first microstrip antenna 3 and the second microstrip antenna 4 are started at the same time, and the test machine 5 sends a control signal to the first microstrip antenna 3, so that the first microstrip antenna 3 sends a test signal to the second microstrip antenna 4 according to the control signal.

S102: the second microstrip antenna 4 receives the test signal, acquires test information from the chip 2 according to the test signal, and returns a signal to be tested containing the test information to the first microstrip antenna 3.

S103: the first microstrip antenna 3 receives a signal to be measured and analyzes the signal to be measured.

After the second microstrip antenna 4 receives the test signal, test information of the chip 2 is obtained, and a signal to be tested containing the test information is sent to the first microstrip antenna 3. After the first microstrip antenna 3 receives the signal to be tested, the signal to be tested is transmitted to the test machine 5, so that the test machine 5 analyzes the information to be tested, and the chip 2 is tested.

The chip test system is the system described in any of the above embodiments, and thus, for other structures of the chip test system, reference may be made to any of the above embodiments of the chip test system, which will not be described herein.

In summary, according to the chip testing method of the embodiment of the disclosure, due to the adoption of the wireless test, the damage to the metal pad 22 on the chip can be avoided, so that the subsequent packaging is performed smoothly, the cost is reduced, and in addition, the stacking test of a plurality of wafers is also performed, and the testing efficiency is improved.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (10)

1. A chip testing system, comprising:

the chip is provided with a second microstrip antenna;

chip testing device, comprising:

the probe card is spaced from the chip and is arranged opposite to the chip;

the first microstrip antenna is arranged on the probe card and is used for sending a test signal to the second microstrip antenna;

the second microstrip antenna is used for receiving the test signal, acquiring test information from the chip according to the test signal, returning a signal to be tested containing the test information to the first microstrip antenna, and the first microstrip antenna is also used for receiving the signal to be tested.

2. The system of claim 1, wherein the chip has a semiconductor device and a first lead therein, the first lead being electrically connected to the semiconductor device, the chip having a metal pad disposed thereon, the metal pad being electrically connected to the first lead.

3. The system of claim 2, wherein the second microstrip antenna is disposed on one side of the metal pad and is electrically connected to the metal pad; and/or the number of the groups of groups,

the second microstrip antenna is arranged on the surface of the chip or inside the chip.

4. The system of claim 2, wherein the second microstrip antenna is disposed on the metal pad; or alternatively, the first and second heat exchangers may be,

the chip further comprises a circuit protection layer, the circuit protection layer is located at the edge of the chip, and the second microstrip antenna is arranged on the circuit protection layer and is electrically connected with any one of the metal pad, the first lead and the semiconductor device through a second lead.

5. The system of claim 2, wherein the chip has a plurality of the chip stacks such that the second microstrip antenna stack is located in the chip or in the metal pad.

6. The system according to any one of claims 1 to 5, wherein a rectifying circuit is further provided in the chip, and the rectifying circuit is electrically connected to the second microstrip antenna, and is configured to convert the test signal received by the second microstrip antenna into a first current signal, and obtain a current signal of test information of the chip according to the first current signal, and the rectifying circuit is further configured to convert the current signal of the test information into the signal to be tested, and transmit the signal to be tested to the second microstrip antenna.

7. The system of any one of claims 1 to 5, wherein the chip testing device further comprises a testing station electrically connected to the first microstrip antenna, the testing station configured to send a control signal to the first microstrip antenna such that the first microstrip antenna sends the test signal to the second microstrip antenna, and after the first microstrip antenna receives the signal under test, the first microstrip antenna is configured to send the signal under test to the testing station.

8. A chip testing apparatus, comprising:

the probe card is arranged at intervals and opposite to the chip, and the chip is provided with a second microstrip antenna;

the first microstrip antenna is arranged on the probe card and is used for sending a test signal to the second microstrip antenna so that the second microstrip antenna can receive the test signal conveniently, test information is acquired from the chip according to the test signal, and the first microstrip antenna is also used for receiving a signal to be tested containing the test information, which is returned by the second microstrip antenna.

9. The chip is characterized in that the chip is arranged at intervals and opposite to a probe card, and a first microstrip antenna is arranged on the probe card;

the chip comprises a second microstrip antenna, wherein the second microstrip antenna is used for receiving the test signal sent by the first microstrip antenna and acquiring test information from the chip so as to send a signal to be tested containing the test information to the first microstrip antenna.

10. A chip testing method, characterized by being applied to the chip testing system of any one of claims 1 to 7, the method comprising:

transmitting a test signal from the first microstrip antenna to the second microstrip antenna;

the second microstrip antenna receives the test signal, acquires test information from the chip according to the test signal, and returns a signal to be tested containing the test information to the first microstrip antenna;

the first microstrip antenna receives the signal to be detected so as to analyze the signal to be detected.

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