CN116318008A - Semi-packaging structure with sealed air resonant cavity, module and electronic equipment - Google Patents

Abstract

The invention discloses a semi-packaging structure with a sealed air resonant cavity, a module and electronic equipment. The semi-packaging structure comprises: a chip body having an electrode surface, a back surface facing the electrode surface, and a side surface connecting the electrode surface and the back surface, the electrode surface having a plurality of electrodes formed thereon; a dielectric layer having a surface, a cavity formed between the surface and the electrode face for accommodating a plurality of electrodes; a plurality of bumps located within the cavity, surrounding the outer periphery of the electrode, and connecting the surface and the electrode face; the inner side of the near sealing ring is positioned in the surrounding range of the outline of the chip body to form an overlapping area; and the substrate solder mask covers the surface, the side surface and the back surface and is connected with the electrode surface and the near sealing ring. The invention has high production efficiency, simple flow and lower cost.

Description

Semi-packaging structure with sealed air resonant cavity, module and electronic equipment

Technical Field

The invention relates to a semi-packaging structure with a sealed air resonant cavity, and also relates to a module and electronic equipment comprising the semi-packaging structure, belonging to the technical field of semiconductor packaging.

Background

Currently, a surface acoustic wave filter (simply referred to as a SAW filter) is widely used in a radio frequency front end module. The SAW filter has many advantages including high working frequency, wide passband, good frequency selection characteristics, small volume, light weight, etc., and can be manufactured by adopting the same production process as an integrated circuit, and has the advantages of simple manufacture, low cost and good consistency of frequency characteristics.

The SAW filter is formed by evaporating a metal film on a material substrate having a piezoelectric effect, and then forming a pair of Interdigital (IDT) transducers at both ends thereof by photolithography. Therefore, packaging for SAW filters must ensure that the interdigital transducer surfaces cannot contact other substances, i.e., that their chip surfaces are cavity structures, which would otherwise affect signal transmission.

Currently, the most popular packaging method of SAW filters is to solder the filter on a substrate, then coat, encapsulate, singulate, and then secondarily package the filter on the substrate. Or, the manufacture of the sealing cover and the retaining wall is completed at the wafer end, and then the sealing cover and the retaining wall are packaged into the module. Such a process is relatively complex and costly.

Disclosure of Invention

The invention aims to provide a semi-packaging structure with an air resonant cavity.

Another technical problem to be solved by the present invention is to provide a module including the above-mentioned half-package structure.

Another technical problem to be solved by the present invention is to provide an electronic device including the above semi-packaging structure.

In order to achieve the technical purpose, the invention adopts the following technical scheme:

according to a first aspect of an embodiment of the present invention, there is provided a half-package structure having a sealed air resonator, including:

a chip body having an electrode surface, a back surface facing the electrode surface, and a side surface connecting the electrode surface and the back surface, wherein a plurality of electrodes are formed on the electrode surface;

a dielectric layer having a surface forming a cavity between the surface and the electrode face for accommodating a plurality of electrodes;

a plurality of bumps located within the cavity, surrounding the outer perimeter of the electrode, and connecting the surface and the electrode face;

the inner side of the near sealing ring is positioned in the surrounding range of the outline of the chip body to form an overlapping area;

and the substrate solder mask covers the surface, the side surface and the back surface and is connected with the electrode surface and the near sealing ring.

Preferably, the proximal seal ring extends into the overlap region and is located between the chip body and a surface of the proximal seal ring to seal a gap between the chip body and the proximal seal ring.

Wherein preferably, the near sealing ring is a discontinuous metal or insulating fence, and a gap exists.

Wherein preferably, the semi-packaging structure further comprises a blind hole positioned on the dielectric layer, a height difference is formed between the surface of the dielectric layer and the bottom of the blind hole,

a portion of the tab is confined within the blind bore.

Wherein preferably the near seal ring is comprised of a copper pillar and a second dielectric layer.

Preferably, the second dielectric layer is made of photo-cured or photo-thermal mixed cured dry film material, is sandwiched between the substrate solder mask layer and the surface of the dielectric layer, and is located at the periphery of the bump.

Wherein preferably the second dielectric layer surrounds the copper pillars and fills the areas between the copper pillars and the bumps.

Wherein preferably, the semi-encapsulated structure further comprises a shielding layer,

the surface of the near sealing ring is electrically connected with the shielding layer through the through hole, so that shielding is realized by the shielding layer, the through hole and the near sealing ring.

According to a second aspect of embodiments of the present invention, a module is provided, which includes the semi-encapsulated structure with a sealed air cavity as described above.

According to a third aspect of embodiments of the present invention, there is provided an electronic device comprising a semi-encapsulated structure with a sealed air cavity as described above.

Compared with the prior art, the invention has the following technical characteristics: 1) The cavity of the panel level is utilized to manufacture, so that the production efficiency is high; the filter welding is completed before the conventional flow of the substrate is performed, and the welding-resisting pressed film forms a cavity, so that the flow is simple and the cost is lower; 2) The discontinuous near sealing ring is utilized to ensure that welding impurities can pass through the gap in the cleaning process after the filter is welded, so that the performance of the filter is ensured; 3) The gap formed between the near sealing ring and the chip body is blocked by the substrate solder mask layer, so that the solder mask material cannot overflow to the surface of the interdigital electrode in the process of solder mask film pressing, and the performance of the filter is ensured; 4) The shielding layer can be arranged by adopting the conventional process of the substrate, so that signal interference is avoided; 5) The packaging structure is suitable for a single bare chip packaging structure, and can be directly covered for shipment.

Drawings

FIG. 1 is a schematic cross-sectional view of a half-package structure with a sealed air cavity in accordance with a first embodiment of the present invention;

FIG. 2 is a schematic top view of the semiconductor package shown in FIG. 1;

FIG. 3 is a schematic cross-sectional view of a half-package structure with a sealed air cavity in accordance with a second embodiment of the present invention;

FIG. 4 is a schematic top view of the semi-encapsulated structure shown in FIG. 3;

FIG. 5 is a schematic cross-sectional view of a half-package structure with a sealed air cavity in accordance with a third embodiment of the present invention;

FIG. 6 is a schematic top view of the semi-encapsulated structure of FIG. 5;

FIG. 7 is a schematic cross-sectional view of a semi-encapsulated structure with a sealed air cavity in accordance with a fourth embodiment of the present invention;

fig. 8 is a schematic top view of the semiconductor package shown in fig. 7.

Detailed Description

The technical contents of the present invention will be described in detail with reference to the accompanying drawings and specific examples.

(first embodiment)

As shown in fig. 1, the semi-packaging structure provided in the embodiment of the invention includes a chip body 1, a dielectric layer 2, and a plurality of bumps (bumps) 4 located in a cavity 3.

The chip body 1 will be described below using a SAW filter chip as an example. Chip body 1 is made of a wafer and has electrode surface 10A, back surface 10B opposite electrode surface 10, and side surface 10C connecting electrode surface 10A and back surface 10B. A plurality of electrodes (for example, interdigital electrodes) 12 and a plurality of bumps 4 are formed on the electrode surface 10A.

The number of the bumps 4 in the cavity may be plural, and may be copper pillars, solder, or the like. The height of the bump 4 (height after Reflow) is either high or low relative to the height of the cavity. The bump 4 is disposed around the outer periphery of the electrode 2 to form a cavity 3 between the chip body 1 and the dielectric layer 2 covering the electrode 2. If a bump 4 made of copper is provided around the electrode 2, the bump 4 can exert a supporting function while exerting a conductive function.

The back surface 10B and the side surface 10C of the chip body 1, and the surface 20 of the dielectric layer 2 adjacent to the side surface 10C are covered with a substrate solder resist layer 11. The substrate solder resist layer 11 is a continuous coating layer formed by applying a solder resist material to the back surface 10B, the side surface 10C, and the surface 20. The surface 20 is provided with conductive pads 21, which correspond in position to the bumps 4. Bump 4 connects surface 20 with electrode face 10A.

As shown in fig. 1 and 2, a near seal ring 31 is formed around the cavity 3. The proximal seal ring 31 is made of copper or of an insulating material. The proximal seal 31 may also be made of the same dielectric material as the dielectric layer 2. The inner side 312 of the near seal ring 31 is located within the peripheral area of the outer shape line of the chip body 1. In other words, the inner side 312 of the proximal seal ring 31 is located within the projection of the contour of the chip body 1 onto the surface 20 of the dielectric layer 2. Herein, "inner" refers to a direction toward the geometric center point of the chip; "external" refers to a direction away from the geometric center of the chip. In other words, the inner side 312 of the near seal ring 31 is located inside the projection line (shown by a broken line in fig. 2) of the side surface 10C of the chip body 1 on the dielectric layer 2. That is, in the vertical direction shown in fig. 2, the projection of the side surface 10C of the chip body 1 (shown by a broken line frame in fig. 2) partially overlaps the near seal ring 31, forming an overlapping region 100 shown by a broken line frame in fig. 1.

Further, since the near seal ring 31 surrounds the outer periphery of the projection 4, the horizontal distance from the near seal ring 31 to the electrode 2 is larger than the horizontal distance from the projection 4 to the electrode 2 in the cross-sectional view shown in fig. 1. Thus, when the solder resist is pressed, the solder resist material is shielded by the near seal ring 31 and does not overflow to the surface of the electrode 2, thereby ensuring the stable performance of the filter.

As shown in fig. 2, the proximal seal 31 is a discontinuous fence of metal or insulating material, i.e., there is a gap 310 in the proximal seal 31. Accordingly, after the chip body 1 is soldered, residues in the cavity 3 can be discharged through the gap 310 during cleaning of the chip.

The dielectric layer 2 serves as a substrate for carrying the chip body 1. A metal connection pad (pad) 21 is formed on the surface 20 of the dielectric layer 2. As shown in fig. 2, the connection pads 21 are connected to the bumps 4 to electrically connect the chip body 1 (filter chip) to the dielectric layer 2. The connection pads 21 may be in one-to-one correspondence with the bumps 4 and located inside projection lines (shown by dashed boxes in fig. 2) of the side surface 10C of the chip body 1 on the dielectric layer 2. The connection pad 21 is thus located inside the area enclosed by the proximal seal 31, but outside the projection of the electrode 2 onto the surface 20.

Also on the surface of the dielectric layer 2 remote from the chip body 1 are Solder Resist (SR) 23 and pads 29. The pads 29 are for electrical connection with the circuit board. Alternatively, the flux 23 may be absent. The pads 29 may be embedded in the dielectric layer 2 or may be on the surface of the dielectric layer 2.

In the present embodiment, the substrate solder mask layer 11 extends into the overlap region 100 and is located between the chip body 1 and the surface 311 of the proximal seal ring 31 to seal the gap between the chip body 1 and the proximal seal ring 31, thereby ensuring the sealing performance of the cavity 3. The substrate solder resist layer 11 is formed of a dry film material, and may be organic, inorganic, and resin series dry film materials. And thus is able to quickly solidify when pressed into the overlap region 100 and is thus confined to the overlap region without flowing to the inside of the near seal ring 31.

(second embodiment)

As shown in fig. 3 and 4, the semi-packaging structure with sealed air resonator provided in this embodiment is different from the first embodiment, and the metal bump 4 in this embodiment is located inside the blind VIA (VIA) 25 formed in the dielectric layer 2. A height difference is formed between the surface 20 of the dielectric layer 2 and the bottom of the blind via 25. Between the bumps 4 and the connection pads 21, there are bump connection pads 24. The connection pads 21 and the bump connection pads 24 are disposed entirely inside the blind holes 25, and there is a height difference between the bump connection pads 24 and the surface 20 of the dielectric layer so that a portion of the bump 4 can be confined within the blind holes 25. Such a height difference design, like the Solder Mask Defined (SMD) structure, facilitates the fixation of the solder shape of the bump 4 to reduce stress and reduce the risk of bump failure.

The height difference between the surface 20 of the dielectric layer 2 and the bottom of the blind via 25 may be formed by partially etching the dielectric support 2 at the blind via 25, or by laminating a dielectric layer having a via or via with a substrate, and then filling the via by electroplating.

(third embodiment)

As shown in fig. 5 and 6, unlike the first embodiment, the half-package structure with the sealed air resonator in the present embodiment has a second dielectric layer 5 added. The second dielectric layer 5 is made of photo-cured or photo-thermal mixed cured dry film material, is sandwiched between the substrate solder mask layer 11 and the surface 20 of the dielectric layer 2, and is located at the periphery of the bump 4. The space between the bump 4 and the second dielectric layer 5 should be empty, and the solder of the bump will flow and fill up during soldering.

Moreover, the near sealing ring 3 in this embodiment is composed of a copper pillar 34 and a second dielectric layer 5. The second dielectric layer 5 surrounds the copper pillars and fills the area between the copper pillars 34 and the bumps 4. Similar to the first embodiment, the near seal ring 33 is also a discontinuous ring structure (as shown in fig. 6), and the substrate solder resist 11 fills the overlapping region between the second dielectric layer 5 and the chip body 1 to ensure that the solder resist does not flow into the surface of the electrode (interdigital transducer) 12 during film lamination, thereby ensuring stable performance of the filter chip. Similar to the first embodiment, overlapping refers to the projection of the side 10C of the chip body onto the dielectric layer 2 (shown by the dashed box in fig. 6), overlapping with the projection of the second dielectric layer 5 onto the dielectric layer, but not overlapping with the projection of the copper pillars 34 onto the dielectric layer (the periphery of the dashed box in fig. 6).

The lower surface of the bump 4 is interconnected with a connection pad 21 inside the dielectric layer 2; the copper pillars 34 are interconnected with connection pads 21A outside the dielectric layer 2. The outer connection pad 21A encloses the inner connection pad 21 on a horizontal plane.

(fourth embodiment)

As shown in fig. 7 and 8, the present embodiment is to add a shielding layer 6 on the outer surface of the substrate solder resist layer 11 to realize the shielding between chips, as compared with the first embodiment. The shielding layer 6 can be a single-component metal such as copper, titanium, nickel, tin, cobalt and the like or a composite material formed by random superposition. The shielding layer 6 may be formed by electroplating, sputtering, or stacking.

In the present embodiment, a through hole (solid hole) 111 is formed in the substrate solder resist layer 11. The proximal seal ring 35 is made of a metal material and is wider than the proximal seal ring 31 in the first embodiment. That is, the surface 311 of the near seal ring 35 is large enough to be electrically connected to the shielding layer 6 through the through hole 111, so that shielding is achieved by the shielding layer 6, the through hole 111, and the near seal ring 35 together.

Further, in the dielectric layer 2, a shielding wall 28 is formed below the near seal ring 35. The shield wall 28 is a metal plated hole through the dielectric layer 2 to electrically connect the near seal ring 35 with the bond pad 29. Thus, the shielding layer 6, the through hole 111, the near seal ring 35, and the shielding wall 28 together form a shielding path to further enhance the shielding effect.

The invention discloses a method for welding filter chips and forming an air resonant cavity in the substrate processing process by the technology, which comprises the steps of preparing a dielectric layer into a cavity in a board-level system, forming a retaining wall by copper or a base material (combining copper and the base material), and completing the processing of a substrate solder mask layer (roof) while forming a solder mask. Therefore, the cavity manufacturing of the panel level is utilized, so that the production efficiency is high; the filter welding is completed before the conventional flow of the substrate is performed, and the welding-resisting pressed film forms a cavity, so that the flow is simple and the cost is lower.

The invention can be suitable for a single bare chip packaging structure and can be directly covered for shipment.

The discontinuous sealing ring formed by the copper column or the dielectric layer is arranged under the solder resist to ensure that welding impurities can pass through the gap in the process of cleaning the filter after welding, thereby ensuring the performance of the filter.

The gap formed between the copper column or the dielectric layer and the chip body can ensure that the solder resist material cannot overflow to the surface of the interdigital electrode in the process of solder resist film pressing, form a sealed air resonant cavity, and ensure the performance of SAW or BAW and other filters.

The substrate conventional process can be adopted on the substrate solder mask layer, and the shielding layer is arranged, so that signal interference between the filter chip and other chips can be avoided during module packaging.

The invention also provides a module, which comprises the semi-packaging structure with the sealed air resonant cavity. The invention is suitable for the module packaging of frequency module, film covering is carried out on the chip body area, and the traditional packaging flow is adopted in other areas. For example, the invention can be used to bond together (IDT on Cap Wafer) with interdigital electrodes and Carrier Wafer (Carrier Wafer) by Cu/Sn/Cu or the like, or with an adhesive to pre-form the cavity, so that the module package containing the filter die can be completed by using conventional packaging process.

The invention also provides electronic equipment, which comprises the semi-packaging structure with the sealed air resonant cavity. The electronic product can be a smart phone, a tablet personal computer, wearable electronic equipment, an intelligent internet-connected automobile and the like.

The semi-packaging structure with the sealed air resonant cavity, the module and the electronic equipment provided by the invention are described in detail. Any obvious modifications to the present invention, without departing from the spirit thereof, would constitute an infringement of the patent rights of the invention and would take on corresponding legal liabilities.

Claims (10)

1. A half-package structure having a sealed air cavity resonator, comprising:

a chip body having an electrode surface, a back surface facing the electrode surface, and a side surface connecting the electrode surface and the back surface, wherein a plurality of electrodes are formed on the electrode surface;

a dielectric layer having a surface forming a cavity between the surface and the electrode face for accommodating a plurality of electrodes;

a plurality of bumps located within the cavity, surrounding the outer perimeter of the electrode, and connecting the surface and the electrode face;

the inner side of the near sealing ring is positioned in the surrounding range of the outline of the chip body to form an overlapping area;

and the substrate solder mask covers the surface, the side surface and the back surface and is connected with the electrode surface and the near sealing ring.

2. The semi-encapsulated structure with sealed air resonator of claim 1 wherein:

the proximal seal ring extends into the overlap region and is positioned between the chip body and a surface of the proximal seal ring to seal a gap between the chip body and the proximal seal ring.

3. The semi-encapsulated structure with sealed air resonator of claim 2 wherein:

the near sealing ring is a discontinuous metal or insulating fence, and a gap exists.

4. The semi-encapsulated structure with hermetically sealed air cavity of claim 3 further comprising a blind via in said dielectric layer,

a height difference is formed between the surface of the dielectric layer and the bottom of the blind hole,

a portion of the tab is confined within the blind bore.

5. A semi-encapsulated structure with a sealed air cavity as defined in claim 3, wherein:

the near sealing ring consists of a copper column and a second dielectric layer.

6. The semi-encapsulated structure with sealed air resonator of claim 5 wherein:

the second dielectric layer is made of photo-curing or photo-thermal mixed curing dry film material, is clamped between the substrate solder mask layer and the surface of the dielectric layer, and is positioned at the periphery of the bump.

7. The semi-encapsulated structure with sealed air resonator of claim 1 wherein:

the second dielectric layer surrounds the copper pillars and fills the areas between the copper pillars and the bumps.

8. The semi-encapsulated structure with a hermetically sealed air cavity of claim 1 further comprising a shielding layer,

the surface of the near sealing ring is electrically connected with the shielding layer through the through hole, so that shielding is realized by the shielding layer, the through hole and the near sealing ring.

9. A module comprising a semi-encapsulated structure with a sealed air cavity as claimed in any one of claims 1 to 8.

10. An electronic device comprising a semi-encapsulated structure with a sealed air cavity as claimed in any one of claims 1 to 8.

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