CN116248076B - A low-power logic-controlled high-linearity digital step attenuator - Google Patents

Abstract

The invention provides a low-power logic-controlled, high-linearity digital step attenuator, which includes: an attenuator, which is composed of a six-bit attenuation unit; a logic control circuit, which is composed of a six-bit logic control unit; and the six-bit attenuation unit includes The first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit, the fifth attenuation unit and the sixth attenuation unit are connected in sequence. The six-bit logic control unit includes a first logic control unit and a second logic control unit. , the third logical control unit, the fourth logical control unit, the fifth logical control unit and the sixth logical control unit. The invention can significantly reduce the through current of the inverter circuit in the digital step attenuator logic control circuit, reduce the power consumption of the digital step attenuator, and can also achieve high linearity attenuation with an attenuation step of 0.5dB and an attenuation range of 0-31.5dBm. device.

Description

A low-power logic-controlled high-linearity digital step attenuator

Technical field

The present invention relates to the technical field of digital step attenuators, and in particular to a high linearity digital step attenuator controlled by low power consumption logic.

Background technique

In order to meet the requirements of radar detection range, data update rate, multi-target tracking and measurement accuracy, active phased array radar technology is currently developing rapidly. A typical active phased array radar T/R component includes a transmitting channel and a receiving channel, which can realize the integration of transmitting and receiving. The receiving channel includes a limiter, a low-noise amplifier, an attenuator, a power amplifier and a power module, as shown in Figure 1. The attenuator in the receiving channel mainly adjusts the channel amplitude to ensure the consistency of the channel amplitude, and is also used for dynamic adjustment of channel signal saturation. As the intermediate stage of the cascade circuit, it is usually required to have high linearity to ensure that the signal is not compressed, thereby ensuring the sensitivity of the receiver. In addition, it is also required to have good echo characteristics, high attenuation accuracy and low additional phase shift. Since entering the 21st century, reducing system power consumption has been one of the main topics of T/R components. In the power distribution of active phased array radar T/R components, the power consumption of the entire system is mainly distributed on the amplifier to ensure The linearity of the system, so the power consumption requirements on the attenuator are more stringent.

The power consumption of the attenuator mainly comes from the control circuit composed of the inverter integrated on the GaAs PHEMT. The typical MMIC DSA one-bit attenuation structure circuit is composed of a control circuit and a one-bit attenuation unit. There are currently two main methods to reduce the direct current power consumption of the inverter circuit. The first is to add a delay element to the gate of the inverter transistor to reduce the static current by delaying the switch switching time. In addition, when the inverter is connected in series using a delay element, the delay element will also consume current and increase additional power consumption. When two complementary inverters are working, one output is low level and the other output is high level. When the output is low level, the branch resistance is large and the static current is small; when the output is high level, the resistance is small and the static current is large. The total static current can be approximately equal to the current of the inverter with a high output level, that is, VDD/(RonD+RoffE), RonD is the on-resistance of the depletion transistor, and RoffE is the off-resistance of the enhancement transistor. Therefore, another method is to add an equivalent resistance to the DC path of the inverter to reduce the current and reduce DC power consumption.

The traditional method to reduce the power consumption of the inverter is to connect a delay element to the gate of the inverter. By affecting the delay of the input signal level, the rise time of the output signal (Vin drops from the input high level to Low level to the time required for the output signal Vn to transition from low level to high level) and fall time (Vin to rise from the input low level to high level to the output signal transition from high level to low level) time) has an impact. The impedance element is used as a delay element. When the impedance value of the impedance element increases, the delay time from the input level Vin to the gate of the transistor increases because the rise time of the output terminal Vn becomes longer. Similarly, the falling time of the output Vp becomes longer. Power consumption is reduced by controlling the turn-on and turn-off times of the inverter. However, this method does not significantly reduce the quiescent current of the inverter.

Another method is to reduce the quiescent DC current by increasing the equivalent resistance of the DC path of the inverter. The on-resistance of a transistor is inversely proportional to the transistor size W/L (W is the transistor gate width, L is the transistor gate length). Reducing the size of the transistor can effectively increase the on-resistance, reduce the DC current, and reduce power consumption. Therefore, the size of the inverter of the logic control circuit is generally designed according to the limit of the process. Currently, the minimum size gate width of the GaAs 250nm process transistor is 5um. At this size, the quiescent current of a 1-bit logic control circuit is 1.6mA. However, for a 6-bit digital step attenuator, the quiescent current of the control circuit will be as much as 9.6mA. This is still unacceptable for a low-power radar system.

Contents of the invention

The invention provides a high linearity digital step attenuator controlled by low power consumption logic, which can significantly reduce the through current of the inverter circuit in the logic control circuit of the digital step attenuator, reduce the power consumption of the digital step attenuator, and also It can realize a high linearity attenuator with an attenuation step of 0.5dB and an attenuation range of 0-31.5dBm.

The embodiment of the present invention discloses a low-power logic-controlled high-linearity digital step attenuator, which includes:

Attenuator, composed of six attenuation units;

The logic control circuit is composed of six-bit logic control units;

Wherein, the six-bit attenuation unit includes a first attenuation unit, a second attenuation unit, a third attenuation unit, a fourth attenuation unit, a fifth attenuation unit and a sixth attenuation unit connected in sequence, and the six-bit logic control unit includes The first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit, the first logic control unit, the second logic control unit, The third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit are respectively connected with the first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit and the fifth attenuation unit. The unit and the sixth attenuation unit are connected in one-to-one correspondence to achieve attenuation of 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB respectively.

In some embodiments, the first attenuation unit includes a switch SW1, an inductor L1, a capacitor C10, a resistor R22, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R28, a switch SW7 and a capacitor C1. One end of the inductor L1 serves as the radio frequency input terminal RFin, and the other end is connected to one end of the capacitor C10. The other end of the capacitor C10 is connected to one end of the resistor R1, one end of the resistor R2, one end of the resistor R22 and the source of the switch SW1. After the terminals are connected, the voltage terminal VDD is externally connected through a resistor. The gate of the switch SW1 is connected to the first logic control unit through a resistor. The drain of the switch SW1 is connected to the other end of the resistor R22 and the other end of the resistor R1. The other end, one end of the resistor R3 is connected to the second attenuation unit, the other end of the resistor R2 is connected to the other end of the resistor R3 and one end of the resistor R4, the other end of the resistor R4 is connected to the switch tube SW7 The source is connected to one end of the resistor R28, the gate of the switch SW7 is connected to the first logic control unit through the resistor, and the other end of the resistor R28 is connected to one end of the capacitor C1 and the drain of the switch SW7. connection, the other end of the capacitor C1 is connected to ground.

In some embodiments, the second attenuation unit includes a switch tube SW2, a resistor R23, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R29, a switch tube SW8 and a capacitor C2, one end of the resistor R5 is connected to one end of the resistor R6, one end of the resistor R23, the source of the switch tube SW2 and the drain of the switch tube SW1, the gate of the switch tube SW2 is connected to the second logic control unit through a resistor, the drain of the switch tube SW2 is connected to the other end of the resistor R23, the other end of the resistor R5, one end of the resistor R7 and the third attenuation unit, the other end of the resistor R6 is connected to the other end of the resistor R7 and one end of the resistor R8, the other end of the resistor R8 is connected to the source of the switch tube SW8 and one end of the resistor R29, the gate of the switch tube SW8 is connected to the second logic control unit through a resistor, the other end of the resistor R29 is connected to one end of the capacitor C2 and the drain of the switch tube SW8, and the other end of the capacitor C2 is grounded.

In some embodiments, the third attenuation unit includes a switch SW3, a resistor R24, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R39, a switch SW9 and a capacitor C3. One end of the resistor R9 is connected to the resistor R9. One end of the resistor R10, one end of the resistor R24, the source of the switch SW3 and the drain of the switch SW2 are connected. The gate of the switch SW3 is connected to the third logic control unit through a resistor. The switch The drain of SW3 is connected to the other end of the resistor R24, the other end of the resistor R9, one end of the resistor R11 and the fourth attenuation unit. The other end of the resistor R10 is connected to the other end of the resistor R11 and one end of the resistor R12. The other end of the resistor R12 is connected to the source of the switch SW9 and one end of the resistor R39. The gate of the switch SW9 is connected to the third logic control unit through a resistor. The resistor R39 The other end is connected to one end of the capacitor C3 and the drain of the switch SW9, and the other end of the capacitor C3 is connected to the ground.

In some embodiments, the fourth attenuation unit includes switch SW4, resistor R25, resistor R13, resistor R14, resistor R15, resistor R30, resistor R31, switch SW10, switch SW11, capacitor C4 and capacitor C5, so One end of the resistor R13 is connected to one end of the resistor R14, one end of the resistor R25, the source of the switch SW4 and the drain of the switch SW3. The gate of the switch SW4 is connected to the fourth logic control through a resistor. The drain of the switch SW4 is connected to the other end of the resistor R25, the other end of the resistor R13, one end of the resistor R15 and the fifth attenuation unit. The other end of the resistor R14 is connected to the other end of the resistor R30. One end of the resistor R15 is connected to the source of the switch SW10. The other end of the resistor R15 is connected to one end of the resistor R31 and the source of the switch SW11. The gate of the switch SW10 is connected to the fourth logic control through a resistor. The gate of the switch SW11 is connected to the fourth logic control unit through a resistor. The other end of the resistor R30 is connected to one end of the capacitor C4 and the drain of the switch SW10. The resistor R31 The other end is connected to one end of the capacitor C5 and the drain of the switch tube SW11, and the other end of the capacitor C4 and the other end of the capacitor C5 are both grounded.

In some embodiments, the fifth attenuation unit includes a switch tube SW5, a resistor R26, a resistor R16, a resistor R17, a resistor R18, a resistor R32, a resistor R33, a switch tube SW12, a switch tube SW13, a capacitor C6 and a capacitor C7, one end of the resistor R16 is connected to one end of the resistor R17, one end of the resistor R26, the source of the switch tube SW5 and the drain of the switch tube SW4, the gate of the switch tube SW5 is connected to the fifth logic control unit through a resistor, the drain of the switch tube SW5 is connected to the other end of the resistor R26, the other end of the resistor R16, one end of the resistor R18 and the sixth attenuation unit, the The other end of the resistor R17 is connected to one end of the resistor R32 and the source of the switch tube SW12, the other end of the resistor R18 is connected to one end of the resistor R33 and the source of the switch tube SW13, the gate of the switch tube SW12 is connected to the fifth logic control unit through a resistor, the gate of the switch tube SW13 is connected to the fifth logic control unit through a resistor, the other end of the resistor R32 is connected to one end of the capacitor C6 and the drain of the switch tube SW12, the other end of the resistor R33 is connected to one end of the capacitor C7 and the drain of the switch tube SW13, and the other end of the capacitor C6 and the other end of the capacitor C7 are both grounded.

In some embodiments, the sixth attenuation unit includes a switch SW6, a resistor R27, a resistor R19, a resistor R20, a resistor R21, a resistor R34, a resistor R35, a switch SW14, a switch SW15, a capacitor C8, a capacitor C11, and an inductor. L2 and capacitor C9, one end of the resistor R19 is connected to one end of the resistor R20, one end of the resistor R27, the source of the switch SW6 and the drain of the switch SW5. The gate of the switch SW6 is connected to The sixth logic control unit is connected. The drain of the switch SW6 is connected to the other end of the resistor R27, the other end of the resistor R19, one end of the resistor R21 and one end of the capacitor C11. The other end of the capacitor C11 is connected. Connected to one end of the inductor L2, the other end of the inductor L2 serves as the radio frequency output terminal RFout. The other end of the resistor R20 is connected to one end of the resistor R34 and the source of the switch SW14. The resistor R21 The other end is connected to one end of the resistor R35 and the source of the switch SW15. The gate of the switch SW14 is connected to the sixth logic control unit through a resistor. The gate of the switch SW15 is connected to the sixth logic control unit through a resistor. The sixth logical control unit is connected, the other end of the resistor R34 is connected to one end of the capacitor C8 and the drain of the switch SW14, the other end of the resistor R35 is connected to one end of the capacitor C9 and the drain of the switch SW15. The drain is connected, and the other ends of the capacitor C8 and the other end of the capacitor C9 are both grounded.

In some embodiments, the first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit have the same circuit structure, and all include Switch Mc1, switch Mc2, switch Mc3, switch Mc4, resistor Rc1, resistor Rc2, capacitor Cc1 and capacitor Cc2. The drain of switch Mc2 and the drain of switch Mc4 are both externally connected to the power supply terminal VDD, so The source of the switch Mc2 is connected to one end of the resistor Rc1, and the other end of the resistor Rc1 is connected to the drain of the switch Mc1. The gate of the switch Mc1 serves as the input terminal Vin. The switch The source of tube Mc1 is grounded, the source of switch tube Mc4 is connected to one end of resistor Rc2, the other end of resistor Rc2 is connected to the drain of switch tube Mc3, and the source of switch tube Mc3 The gate of the switching tube Mc2 is connected to one end of the capacitor Cc1 and the gate of the switching tube Mc3 as the output terminal Vn. The other end of the capacitor Cc1 is grounded. The gate of the switching tube Mc4 is connected to the gate of the switching tube Mc3. One end of the capacitor Cc2 is connected as the output terminal Vp, and the other end of the capacitor Cc2 is connected to ground; wherein, the output terminal Vn is connected to the gate of the corresponding switch tube SW1 or the gate or switch of the switch tube SW2 through a resistor. The gate of the switch SW3 or the gate of the switch SW4 or the gate of the switch SW5 or the gate of the switch SW6 is connected; the output terminal Vp is connected to the corresponding gate of the switch SW7 or the switch SW8 through a resistor. The gate of switch tube SW9 or the gate of switch tube SW10 and the gate of switch tube SW11 or the gate of switch tube SW12 and switch tube SW13 or the gate of switch tube SW14 and switch tube SW15 are connected.

To sum up, the present invention at least has the following beneficial effects:

The present invention sets the first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit, the fifth attenuation unit and the sixth attenuation unit that are connected in sequence, and then through the first logic control unit and the second logic control unit. , the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit respectively control the first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit and the fifth attenuation unit. unit and the sixth attenuation unit to achieve attenuation of 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB respectively; it can be applied to RF front-end transmission modules related to active phased array radar T/R components, which can not only significantly reduce digital The through-current of the inverter circuit in the step attenuator logic control circuit reduces the power consumption of the digital step attenuator, and can also realize a high linearity attenuator with an attenuation step of 0.5dB and an attenuation range of 0-31.5dBm.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the attenuator involved in the present invention.

FIG. 2 is a schematic diagram of a logic control circuit involved in the present invention.

Figure 3 is a schematic diagram of iip3 in the zero attenuation state of the DSA when the values of Rc1 and Rc2 involved in the present invention are 10KΩ.

Figure 4 is a schematic diagram of the changing trend of V1N with the output power Pout when the DSA involved in the present invention is in a zero-attenuation state.

FIG. 5 is a schematic diagram illustrating the changing trend of the attenuation amount (Pgain) with the output power Pout when the DSA involved in the present invention is in the zero-attenuation state.

FIG6 is a schematic diagram of iip3 of the DSA zero-decay state when Rc1 and Rc2 involved in the present invention are 10KΩ, Cc1 and Cc2 are 0.5pF.

Detailed ways

In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the embodiments of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

The following disclosure provides many different embodiments or examples for implementing different structures of embodiments of the invention. To simplify the disclosure of embodiments of the present invention, components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit embodiments of the present invention. Furthermore, embodiments of the present invention may repeat reference numbers and/or reference letters in different examples, such repetition being for purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in Figure 1, an embodiment of the present invention discloses a low-power logic-controlled, high-linearity digital step attenuator, which includes:

Attenuator, composed of six attenuation units;

The logic control circuit is composed of six-bit logic control units;

Among them, the six-bit attenuation unit includes a first attenuation unit, a second attenuation unit, a third attenuation unit, a fourth attenuation unit, a fifth attenuation unit and a sixth attenuation unit that are connected in sequence, and the six-bit logic control unit includes a first logic control unit. unit, second logical control unit, third logical control unit, fourth logical control unit, fifth logical control unit and sixth logical control unit, first logical control unit, second logical control unit, third logical control unit, The fourth logic control unit, the fifth logic control unit and the sixth logic control unit are respectively connected with the first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit, the fifth attenuation unit and the sixth attenuation unit. Corresponding connections are made to achieve 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB attenuation respectively.

In some embodiments, as shown in Figure 1, the first attenuation unit includes a switch SW1, an inductor L1, a capacitor C10, a resistor R22, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R28, a switch SW7 and a capacitor. C1, one end of the inductor L1 serves as the radio frequency input terminal RFin, and the other end is connected to one end of the capacitor C10. The other end of the capacitor C10 is connected to one end of the resistor R1, one end of the resistor R2, one end of the resistor R22, and the source of the switch SW1. The resistor is externally connected to the voltage terminal VDD. The gate of the switch SW1 is connected to the first logic control unit through the resistor. The drain of the switch SW1 is connected to the other end of the resistor R22, the other end of the resistor R1, one end of the resistor R3 and the second attenuation unit. The other end of the resistor R2 is connected to the other end of the resistor R3 and one end of the resistor R4. The other end of the resistor R4 is connected to the source of the switch tube SW7 and one end of the resistor R28. The gate of the switch tube SW7 is connected to the first terminal through the resistor. The logic control unit is connected, the other end of the resistor R28 is connected to one end of the capacitor C1 and the drain of the switch SW7, and the other end of the capacitor C1 is connected to the ground.

In some embodiments, as shown in Figure 1, the second attenuation unit includes a switch SW2, a resistor R23, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R29, a switch SW8 and a capacitor C2. One end of the resistor R5 It is connected to one end of the resistor R6, one end of the resistor R23, the source of the switch SW2 and the drain of the switch SW1. The gate of the switch SW2 is connected to the second logic control unit through the resistor. The drain of the switch SW2 is connected to the resistor. The other end of R23, the other end of resistor R5, and one end of resistor R7 are connected to the third attenuation unit. The other end of resistor R6 is connected to the other end of resistor R7 and one end of resistor R8. The other end of resistor R8 is connected to the switch SW8. The source is connected to one end of the resistor R29, the gate of the switch SW8 is connected to the second logic control unit through the resistor, the other end of the resistor R29 is connected to one end of the capacitor C2 and the drain of the switch SW8, and the other end of the capacitor C2 is connected to ground. .

In some embodiments, as shown in Figure 1, the third attenuation unit includes a switch SW3, a resistor R24, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R39, a switch SW9 and a capacitor C3. One end of the resistor R9 One end of the resistor R10, one end of the resistor R24, the source of the switch SW3 and the drain of the switch SW2 are connected. The gate of the switch SW3 is connected to the third logic control unit through the resistor. The drain of the switch SW3 is connected to the resistor. The other end of R24, the other end of resistor R9, and one end of resistor R11 are connected to the fourth attenuation unit. The other end of resistor R10 is connected to the other end of resistor R11 and one end of resistor R12. The other end of resistor R12 is connected to the switch tube SW9. The source is connected to one end of the resistor R39, the gate of the switch SW9 is connected to the third logic control unit through the resistor, the other end of the resistor R39 is connected to one end of the capacitor C3 and the drain of the switch SW9, and the other end of the capacitor C3 is connected to the ground. .

In some embodiments, as shown in Figure 1, the fourth attenuation unit includes a switch SW4, a resistor R25, a resistor R13, a resistor R14, a resistor R15, a resistor R30, a resistor R31, a switch SW10, a switch SW11, a capacitor C4 and Capacitor C5, one end of resistor R13 are connected to one end of resistor R14, one end of resistor R25, the source electrode of switch tube SW4 and the drain electrode of switch tube SW3. The gate electrode of switch tube SW4 is connected to the fourth logic control unit through the resistor. The switch The drain of tube SW4 is connected to the other end of resistor R25, the other end of resistor R13, one end of resistor R15 and the fifth attenuation unit. The other end of resistor R14 is connected to one end of resistor R30 and the source of switch tube SW10. Resistor R15 The other end of the resistor R31 is connected to the source of the switch SW11. The gate of the switch SW10 is connected to the fourth logic control unit through a resistor. The gate of the switch SW11 is connected to the fourth logic control unit through a resistor. The resistor The other end of R30 is connected to one end of capacitor C4 and the drain of switch SW10. The other end of resistor R31 is connected to one end of capacitor C5 and the drain of switch SW11. The other end of capacitor C4 and the other end of capacitor C5 are both grounded. .

In some embodiments, as shown in FIG. 1 , the fifth attenuation unit includes a switch tube SW5, a resistor R26, a resistor R16, a resistor R17, a resistor R18, a resistor R32, a resistor R33, a switch tube SW12, a switch tube SW13, a capacitor C6, and a capacitor C7. One end of the resistor R16 is connected to one end of the resistor R17, one end of the resistor R26, a source of the switch tube SW5, and a drain of the switch tube SW4. The gate of the switch tube SW5 is connected to the fifth logic control unit through the resistor. The drain of the switch tube SW5 is connected to the other end of the resistor R26, the other end of the resistor R16, one end of the resistor R18, and the sixth The attenuation unit is connected, the other end of the resistor R17 is connected to one end of the resistor R32 and the source of the switch tube SW12, the other end of the resistor R18 is connected to one end of the resistor R33 and the source of the switch tube SW13, the gate of the switch tube SW12 is connected to the fifth logic control unit through the resistor, the gate of the switch tube SW13 is connected to the fifth logic control unit through the resistor, the other end of the resistor R32 is connected to one end of the capacitor C6 and the drain of the switch tube SW12, the other end of the resistor R33 is connected to one end of the capacitor C7 and the drain of the switch tube SW13, and the other end of the capacitor C6 and the other end of the capacitor C7 are both grounded.

In some embodiments, as shown in Figure 1, the sixth attenuation unit includes a switch SW6, a resistor R27, a resistor R19, a resistor R20, a resistor R21, a resistor R34, a resistor R35, a switch SW14, a switch SW15, a capacitor C8, Capacitor C11, inductor L2, capacitor C9, one end of resistor R19 are connected to one end of resistor R20, one end of resistor R27, the source of switch tube SW6 and the drain of switch tube SW5. The gate of switch tube SW6 is connected to the sixth through the resistor. The logic control unit is connected. The drain of the switch SW6 is connected to the other end of the resistor R27, the other end of the resistor R19, one end of the resistor R21 and one end of the capacitor C11. The other end of the capacitor C11 is connected to one end of the inductor L2. The other end serves as the radio frequency output terminal RFout. The other end of the resistor R20 is connected to one end of the resistor R34 and the source of the switch tube SW14. The other end of the resistor R21 is connected to one end of the resistor R35 and the source of the switch tube SW15. The switch tube SW14 The gate is connected to the sixth logic control unit through a resistor. The gate of the switch SW15 is connected to the sixth logic control unit through a resistor. The other end of the resistor R34 is connected to one end of the capacitor C8 and the drain of the switch SW14. The resistor R35 The other end is connected to one end of the capacitor C9 and the drain of the switch SW15, and the other end of the capacitor C8 and the other end of the capacitor C9 are both grounded.

In some embodiments, as shown in Figure 2, the circuit structure of the first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit Consistent, including switch tube Mc1, switch tube Mc2, switch tube Mc3, switch tube Mc4, resistor Rc1, resistor Rc2, capacitor Cc1 and capacitor Cc2. The drain of switch Mc2 and the drain of switch Mc4 are both externally connected to the power supply terminal VDD. , the source of the switch Mc2 is connected to one end of the resistor Rc1, the other end of the resistor Rc1 is connected to the drain of the switch Mc1, the gate of the switch Mc1 is used as the input terminal Vin, the source of the switch Mc1 is grounded, and the switch Mc4 The source is connected to one end of the resistor Rc2, the other end of the resistor Rc2 is connected to the drain of the switch Mc3, the source of the switch Mc3 is grounded, the gate of the switch Mc2 is connected to one end of the capacitor Cc1 and the gate of the switch Mc3 After connection, it is used as the output terminal Vn, and the other end of the capacitor Cc1 is grounded. After the gate of the switch tube Mc4 is connected to one end of the capacitor Cc2, it is used as the output terminal Vp. The other end of the capacitor Cc2 is grounded; among them, the output terminal Vn is connected to the corresponding switch through a resistor. The gate of the switch SW1 or the gate of the switch SW2 or the gate of the switch SW3 or the gate of the switch SW4 or the gate of the switch SW5 or the gate of the switch SW6 is connected; the output terminal Vp is connected to the corresponding one through a resistor. The gate of the switch SW7 or the gate of the switch SW8 or the gate of the switch SW9 or the gate of the switch SW10 and the switch SW11 or the gate of the switch SW12 and the switch SW13 or the gate of the switch SW14 and the switch SW15 gate connection.

To sum up, as shown in Figure 2, the input terminals Vin of the first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit are respectively V1～V6, the output terminal Vn is V1N～V6N respectively, and the output terminal Vp is V1P～V6P respectively.

The principle of the present invention is as follows:

The high linearity digital step attenuator (DSA) controlled by low power consumption logic is composed of an attenuator (ATT) and a logic control circuit (logic circuit). The ATT is composed of six attenuation units (ATT1~ATT6). Each attenuation unit The unit attenuation amounts are 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB respectively. After being controlled by logic circult (six-digit logic control unit: logic circult1~6), the step of 0.5dB can be achieved, and the attenuation range is 0~31.5dB. The 0.5dB attenuation of the attenuation unit ATT1 is mainly determined by the resistor elements. The resistor elements R1, R2, R3 and R4 form a bridge T-shaped attenuation structure. The bridge T-shaped attenuation structure has high attenuation accuracy, good echo characteristics and small additional phase shift. The characteristics of the switch tube SW1 and switch tube SW2 and the bridge T-shaped attenuation structure form a 0.5dB switch embedded attenuation unit ATT1. ATT1 is controlled by the logic circuit1 circuit. The two complementary level output terminals of logiccircult1 are connected to the series branch switch SW1 and the parallel branch switch SW2 of ATT1. Specifically, the output terminal V1N of logic circuit1 (through a resistor) is connected to the switch SW1. , the output terminal V1P (through a resistor) is connected to the switch tube SW2, which can achieve 0dB and 0.5dB attenuation. The capacitive element C1 is a DC blocking capacitor, which can also reduce the impedance fluctuations of the two working states of the attenuation unit and adjust the additional phase shift. The resistive element R22 and R28 mainly ensure that the source-drain voltage of switch tube SW1 and switch tube SW2 is the same. In the same way, the attenuation unit ATT2 is controlled by the logic circuit2 circuit and can achieve 0dB and 1dB attenuation respectively; the attenuation unit ATT3 is controlled by the logic circuit3 circuit and can achieve 0dB and 2dB attenuation respectively. The resistive elements R13, R14 and R15 form a Π-shaped attenuation structure. The Π-shaped attenuation structure has two branches connected in parallel to the ground. The impedance to the ground is small, making it easier to achieve a wider range of amplitude attenuation. The Π-shaped attenuation structure composed of resistive elements R13, R14 and R15 and the switch tube SW4, switch tube SW10 and switch tube SW11 form the switch embedded attenuation unit ATT4. ATT4 is controlled by the logic circuit 4 circuit and can achieve 0dB and 4dB attenuation respectively. In the same way, ATT5 is controlled by the logic circuit5 circuit and can achieve 0dB and 8dB attenuation respectively; ATT6 is controlled by the logic circuit6 circuit and can achieve 0dB and 16dB attenuation respectively. The entire ATT circuit is connected to the power supply VDD, so that the switching source-drain voltage is 5V, and the central voltage value of the signal swing is the DC voltage VDD, improving linearity. C10 and C11 are DC blocking capacitors. The structure of logic circult1~6 is exactly the same as that of logic circut. Since there are 6 bits of the same logic control circuit (logic circult1~6), it consumes a lot of power. Reducing the quiescent current of each logic control unit can effectively reduce the power consumption of ATT. .

Specific analysis, when the control level V1~V6 is low level, V1N~V6N is high level, SW1~SW6 is turned on; V1P~V6P is low level, SW7~SW15 is turned off, at this time the ATT working state is the reference state ( Zero decay). (1) When there are no Rc1, Rc2, Cc1 and Cc2, the quiescent current of the MC1 and MC2 branches is small, and the quiescent current of the MC3 and MC4 branches is large. When the transistor size is 5um, the total current of the one-bit logic control circuit is 1.6 mA, the total current of the 6-bit logic control circuit is 9.6mA. (2) When there are only Rc1 and Rc2, the logic current decreases as Rc1 and Rc2 increase. When the values of Rc1 and Rc2 are 10KΩ, the total current of the one-bit logic control circuit is 85uA, and 6 is the control logic circuit. The total current is 510uA, which can effectively reduce the quiescent current and reduce the total power consumption. However, the addition of resistors will lead to increased nonlinearity when the inverter outputs large signals. As shown in Figure 3, when DSA is at zero attenuation, the worst input third-order intermodulation iip3 (iip3R is the intermodulation signal on the right side of the fundamental frequency, iip3L is the intermodulation signal on the left side of the fundamental frequency) is 35.6dB, resulting in signal generation Severe nonlinearity ultimately affects the quality of radar T/R component signals. The main reasons for this phenomenon are as follows. When a high-power signal passes through ATT, due to the existence of the parasitic capacitance Cgs and Cgd of the switching tube, the input signal is coupled to the gate of the switching tube through the parasitic capacitance. When the signal is greater than 10dBm, the switching tube will be degraded. The gate voltage causes the switch tube to not be fully opened, as shown in Figure 4. The output power is also compressed early, with P0.1dB being 12dBm, as shown in Figure 5. (3) When Rc1, Rc2, Cc1 and Cc2 all exist, it can not only reduce the static power consumption of the DSA, but also make the DSA have high linearity. The existence of Rc1 and Rc2 can reduce power consumption. The existence of Cc1 and Cc2 can provide AC ground for AC signals. Specifically, when a large signal is coupled to the gate of the switch through the parasitic capacitance Cgs and Cds of the switch, it can provide the gate with Provides a path to ground so that the output voltage of the inverter is constant, as shown in Figure 4. Specifically, Rc1 and Rc2 are 10KΩ, Cc1 and Cc2 are 0.5pF, and the output power P0.1dB is 30dbm@0.5-4GHz, as shown in Figure 6. The input third-order intermodulation iip3 of the DSA zero-attenuation state is at 49.6@0.5-4GHz. This structure has high linearity.

In summary, the inverter structure proposed by the present invention can effectively reduce the quiescent current of the inverter and reduce the power consumption of the attenuator logic control circuit. The invention can realize a digital step attenuator with a step of 0.5dB, an attenuation range of 0-31.5dB@0.5-4GHz, and has high linearity.

In view of the fact that the logic control circuit of the digital step attenuator integrated in GaAs PHEMT will have a large quiescent current, the present invention proposes to add a resistor to the inverter to reduce the quiescent current, and to add a capacitor to the ground support at the output end of the inverter. path to ensure the stability of the gate voltage of the switch tube. By adjusting the size of the resistor and capacitor, the power consumption of the digital step attenuator can be well reduced and high linearity can be ensured.

The structure of the invention is composed of 6-bit attenuation units with different attenuation amounts. By inputting 6-bit control levels, a step of 0.5dB and an attenuation range of 0-31.5dB can be achieved; also due to the addition of a DC blocking capacitor, the power supply VDD Providing voltage to the entire attenuator circuit can ensure high linearity and low additional phase shift, and can be fully used in RF front-end transmission modules related to active phased array radar T/R components.

The above-described embodiments are used to illustrate the present invention, but not to limit the present invention. Therefore, changes in the numerical values or replacement of equivalent components should still fall within the scope of the present invention.

From the above detailed description, those of ordinary skill in the art can understand that the present invention can indeed achieve the aforementioned objects and is in compliance with the provisions of the patent law.

Although the preferred embodiments of the invention have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the invention. The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. It should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall include within the protection scope of the present invention.

It should be noted that the above description of the relevant processes is only for example and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process under the guidance of this specification. However, such modifications and changes remain within the scope of this specification.

The basic concepts have been described above. It is obvious to those of ordinary skill in the art after reading this application that the above disclosure of the invention is only an example and does not constitute a limitation on this application. Although not explicitly stated herein, various modifications, improvements, and corrections to the present application may be made by those of ordinary skill in the art. Such modifications, improvements and corrections are suggested in this application, so such modifications, improvements and corrections still fall within the spirit and scope of the exemplary embodiments of this application.

At the same time, this application uses specific words to describe the embodiments of the application. For example, "one embodiment," "an embodiment," and/or "some embodiments" means a certain feature, structure, or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that “an embodiment” or “an embodiment” or “an alternative embodiment” mentioned twice or more at different places in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of the present application may be appropriately combined.

In addition, it will be appreciated by those skilled in the art that various aspects of the present application may be illustrated and described by a number of patentable categories or situations, including any new and useful combination of processes, machines, products or substances, or any new and useful improvements thereto. Therefore, various aspects of the present application may be implemented entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The above hardware or software may all be referred to as "units", "modules" or "systems". In addition, various aspects of the present application may take the form of a computer program product embodied in one or more computer-readable media, wherein computer-readable program code is contained therein.

The computer program code required for the operation of each part of this application can be written in any one or more programming languages, including object-oriented languages such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc. Programming languages, conventional programming languages such as C programming language, Visual Basic, Fortran2103, Perl, COBOL2102, PHP, ABAP, dynamic programming languages such as Python, Ruby and Groovy or other programming languages, etc. The program code may run entirely on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer can be connected to the user computer via any form of network, such as a local area network (LAN) or a wide area network (WAN), or to an external computer (e.g. via the Internet), or in a cloud computing environment, or as a service Use software as a service (SaaS).

In addition, unless expressly stated in the claims, the order of the processing elements and sequences described in this application, the use of alphanumeric characters, or the use of other names are not intended to limit the order of the processes and methods of this application. Although the above disclosure discusses some invention embodiments that are currently considered useful through various examples, it should be understood that such details are only for illustrative purposes, and the attached claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover all modifications and equivalent combinations that are consistent with the essence and scope of the embodiments of this application. For example, although the implementation of the various components described above can be embodied in a hardware device, it can also be implemented as a pure software solution, for example, installation on an existing server or mobile device.

Similarly, it should be noted that in order to simplify the description disclosed in this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of the application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this method of the application should not be interpreted as reflecting the intention that the claimed object requires more features than those explicitly stated in each claim. On the contrary, the subject of the invention should have fewer features than the single embodiment described above.

Claims (1)

1. A low power logic controlled high linearity digital step attenuator comprising:

the attenuator is composed of six-bit attenuation units;

the logic control circuit is composed of six-bit logic control units;

the six-bit attenuation unit comprises a first attenuation unit, a second attenuation unit, a third attenuation unit, a fourth attenuation unit, a fifth attenuation unit and a sixth attenuation unit which are sequentially connected, wherein the six-bit logic control unit comprises a first logic control unit, a second logic control unit, a third logic control unit, a fourth logic control unit, a fifth logic control unit and a sixth logic control unit, and the first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit are respectively connected with the first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit, the fifth attenuation unit and the sixth attenuation unit in a one-to-one correspondence manner so as to respectively realize 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB of attenuation;

The first attenuation unit comprises a switch tube SW1, an inductor L1, a capacitor C10, a resistor R22, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R28, a switch tube SW7 and a capacitor C1, wherein one end of the inductor L1 is used as a radio frequency input end RFin, the other end of the inductor L is connected with one end of the capacitor C10, the other end of the capacitor C10 is connected with one end of the resistor R1, one end of the resistor R2, one end of the resistor R22 and a source electrode of the switch tube SW1 through a resistor external voltage end VDD, a grid electrode of the switch tube SW1 is connected with the first logic control unit through a resistor, a drain electrode of the switch tube SW1 is connected with the other end of the resistor R22, the other end of the resistor R1, one end of the resistor R3 and a second attenuation unit, the other end of the resistor R2 is connected with the other end of the resistor R3 and one end of the resistor R4, the other end of the resistor R4 is connected with a source electrode of the switch tube SW7 and one end of the resistor R28, a grid electrode of the switch tube SW7 is connected with the other end of the capacitor C1 through the resistor control unit and the resistor C7;

the second attenuation unit comprises a switch tube SW2, a resistor R23, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R29, a switch tube SW8 and a capacitor C2, wherein one end of the resistor R5 is connected with one end of the resistor R6, one end of the resistor R23, a source electrode of the switch tube SW2 and a drain electrode of the switch tube SW1, a grid electrode of the switch tube SW2 is connected with the second logic control unit through the resistor, the drain electrode of the switch tube SW2 is connected with the other end of the resistor R23, the other end of the resistor R5, one end of the resistor R7 and a third attenuation unit, the other end of the resistor R6 is connected with the other end of the resistor R7 and one end of the resistor R8, the other end of the resistor R8 is connected with a source electrode of the switch tube SW8 and one end of the resistor R29, the grid electrode of the switch tube SW8 is connected with the second logic control unit through the resistor, the other end of the resistor R29 is connected with one end of the capacitor C2 and the drain electrode of the switch tube SW8, and the other end of the capacitor C2 is connected with the ground;

The third attenuation unit comprises a switch tube SW3, a resistor R24, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R39, a switch tube SW9 and a capacitor C3, wherein one end of the resistor R9 is connected with one end of the resistor R10, one end of the resistor R24, a source electrode of the switch tube SW3 and a drain electrode of the switch tube SW2, a grid electrode of the switch tube SW3 is connected with the third logic control unit through the resistor, the drain electrode of the switch tube SW3 is connected with the other end of the resistor R24, the other end of the resistor R9, one end of the resistor R11 and a fourth attenuation unit, the other end of the resistor R10 is connected with the other end of the resistor R11 and one end of the resistor R12, the other end of the resistor R12 is connected with a source electrode of the switch tube SW9 and one end of the resistor R39, the grid electrode of the switch tube SW9 is connected with the third logic control unit through the resistor, the other end of the resistor R39 is connected with one end of the capacitor C3 and the drain electrode of the switch tube SW9, and the other end of the capacitor C3 is connected with the ground;

the fourth attenuation unit comprises a switch tube SW4, a resistor R25, a resistor R13, a resistor R14, a resistor R15, a resistor R30, a resistor R31, a switch tube SW10, a switch tube SW11, a capacitor C4 and a capacitor C5, wherein one end of the resistor R13 is connected with one end of the resistor R14, one end of the resistor R25, a source electrode of the switch tube SW4 and a drain electrode of the switch tube SW3, a grid electrode of the switch tube SW4 is connected with the fourth logic control unit through a resistor, a drain electrode of the switch tube SW4 is connected with the other end of the resistor R25, the other end of the resistor R13, one end of the resistor R15 and a fifth attenuation unit, the other end of the resistor R14 is connected with one end of the resistor R30 and a source electrode of the switch tube SW10, the other end of the resistor R15 is connected with one end of the resistor R31 and a source electrode of the switch tube SW11, a grid electrode of the switch tube SW10 is connected with the fourth logic control unit through a resistor, a grid electrode of the switch tube SW11 is connected with the fourth logic control unit, one end of the other end of the switch tube SW10 is connected with the other end of the resistor C10 and the capacitor C5 and the other end of the resistor C10 is connected with the drain electrode of the capacitor C4;

The fifth attenuation unit comprises a switch tube SW5, a resistor R26, a resistor R16, a resistor R17, a resistor R18, a resistor R32, a resistor R33, a switch tube SW12, a switch tube SW13, a capacitor C6 and a capacitor C7, wherein one end of the resistor R16 is connected with one end of the resistor R17, one end of the resistor R26, a source electrode of the switch tube SW5 and a drain electrode of the switch tube SW4, a grid electrode of the switch tube SW5 is connected with the fifth logic control unit through a resistor, a drain electrode of the switch tube SW5 is connected with the other end of the resistor R26, the other end of the resistor R16, one end of the resistor R18 and a sixth attenuation unit, the other end of the resistor R17 is connected with one end of the resistor R32 and a source electrode of the switch tube SW12, the other end of the resistor R18 is connected with one end of the resistor R33 and a source electrode of the switch tube SW13, a grid electrode of the switch tube SW12 is connected with the fifth logic control unit through a resistor, a grid electrode of the switch tube SW13 is connected with the fifth logic control unit, the other end of the switch tube SW12 is connected with the other end of the resistor C12 and the capacitor C6 and the other end of the resistor C12 is connected with the drain electrode of the capacitor C6;

The sixth attenuation unit comprises a switch tube SW6, a resistor R27, a resistor R19, a resistor R20, a resistor R21, a resistor R34, a resistor R35, a switch tube SW14, a switch tube SW15, a capacitor C8, a capacitor C11, an inductor L2 and a capacitor C9, wherein one end of the resistor R19 is connected with one end of the resistor R20, one end of the resistor R27, a source of the switch tube SW6 and a drain of the switch tube SW5, a gate of the switch tube SW6 is connected with the sixth logic control unit through a resistor, a drain of the switch tube SW6 is connected with the other end of the resistor R27, the other end of the resistor R19, one end of the resistor R21 and one end of the capacitor C11, the other end of the capacitor C11 is connected with one end of the inductor L2, the other end of the inductor L2 is used as a radio frequency output end RFout, the other end of the resistor R20 is connected with one end of the resistor R34 and a source of the switch tube SW14, the other end of the resistor R21 is connected with one end of the resistor R35 and one end of the switch tube SW15, the drain of the switch tube SW14 is connected with the other end of the resistor C9 and the other end of the switch tube SW14 through the resistor C15, the drain of the switch tube SW14 is connected with the other end of the resistor C8 and the resistor C8;

The circuit structures of the first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit are consistent, each circuit structure comprises a switching tube Mc1, a switching tube Mc2, a switching tube Mc3, a switching tube Mc4, a resistor Rc1, a resistor Rc2, a capacitor Cc1 and a capacitor Cc2, the drain electrode of the switching tube Mc2 and the drain electrode of the switching tube Mc4 are externally connected with a power supply end VDD, the source electrode of the switching tube Mc2 is connected with one end of the resistor Rc1, the other end of the resistor Rc1 is connected with the drain electrode of the switching tube Mc1, the grid electrode of the switching tube Mc1 is used as an input end Vin, the source electrode of the switching tube Mc4 is connected with one end of the resistor Rc2, the other end of the resistor Rc2 is connected with the drain electrode of the switching tube Mc3, the source electrode of the switching tube Mc3 is grounded, the grid electrode of the switching tube Mc2 is connected with the other end of the capacitor Cc2 is used as an output end of the capacitor Cc2, and the other end of the switching tube Cc2 is grounded;

the output end Vn is connected with the corresponding grid electrode of the switch tube SW1 or the corresponding grid electrode of the switch tube SW2 or the corresponding grid electrode of the switch tube SW3 or the corresponding grid electrode of the switch tube SW4 or the corresponding grid electrode of the switch tube SW5 or the corresponding grid electrode of the switch tube SW6 through a resistor;

The output end Vp is connected with the corresponding grid electrode of the switch tube SW7 or the grid electrode of the switch tube SW8 or the grid electrode of the switch tube SW9 or the grid electrodes of the switch tube SW10 and the switch tube SW11 or the grid electrodes of the switch tube SW12 and the switch tube SW13 or the grid electrodes of the switch tube SW14 and the switch tube SW15 through resistors;

the first attenuation unit, the second attenuation unit, the third attenuation unit, the fourth attenuation unit, the fifth attenuation unit and the sixth attenuation unit are respectively controlled by the first logic control unit, the second logic control unit, the third logic control unit, the fourth logic control unit, the fifth logic control unit and the sixth logic control unit to realize stepping of 0.5dB and the attenuation range of 0-31.5 dB; the 0.5dB attenuation of the first attenuation unit is determined by a resistor element, the resistor elements R1, R2, R3 and R4 form a bridge T-shaped attenuation structure, and the switch tube SW1, the switch tube SW7 and the bridge T-shaped attenuation structure form a 0.5dB switch embedded first attenuation unit; the first attenuation unit is controlled by a first logic control unit, two complementary level output ends of the first logic control unit are connected with a first attenuation unit serial branch switching tube SW1 and a parallel branch switching tube SW7, specifically, an output end V1N of the first logic control unit is connected with the switching tube SW1, an output end V1P is connected with the switching tube SW7 to realize attenuation of 0dB and 0.5dB, a capacitance element C1 is a blocking capacitor, resistance elements R22 and R28 ensure that source-drain voltages of the switching tube SW1 and the switching tube SW7 are the same, a second attenuation unit is controlled by a second logic control unit to realize attenuation of 0dB and 1dB, and a third attenuation unit is controlled by a third logic control unit to realize attenuation of 0dB and 2 dB; the resistance elements R13, R14 and R15 form a pi-shaped attenuation structure, the pi-shaped attenuation structure is provided with two branches connected to the ground in parallel, the pi-shaped attenuation structure is formed by the resistance elements R13, R14 and R15, and a fourth attenuation unit embedded in a switch is formed by the switching tube SW4, the switching tube SW10 and the switching tube SW11, and the fourth attenuation unit is controlled by a fourth logic control unit to realize attenuation of 0dB and 4 dB; the fifth attenuation unit is controlled by the fifth logic control unit to realize attenuation of 0dB and 8 dB; the sixth attenuation unit is controlled by the sixth logic control unit to realize 0dB and 16dB attenuation; the whole circuit is connected with a power supply VDD to enable the source-drain voltage of the switch to be 5V, and the central voltage value of the signal swing is the direct-current voltage VDD; the capacitor C10 and the capacitor C11 are blocking capacitors;

The specific process is as follows:

when the control levels V1-V6 are low, V1N-V6N are high, and SW 1-SW 6 are opened; V1P-V6P are low level, SW 7-SW 15 are closed, and the working state is the reference state;

(1) When Rc1, rc2, cc1 and Cc2 are not present, the static current of the MC1 and MC2 branch circuits is small, the static current of the MC3 and MC4 branch circuits is large, when the transistor size is 5um, the total current of the one-bit logic control circuit is 1.6mA, and the total current of the 6-bit logic control circuit is 9.6mA;

(2) When Rc1 and Rc2 are only used, the logic current is reduced along with the increase of Rc1 and Rc2, and when the values of Rc1 and Rc2 are 10KΩ, the total current of the one-bit logic control circuit is 85uA, and the total current of the 6-bit logic control circuit is 510uA;

(3) When Rc1, rc2, cc1 and Cc2 are all present, the static power consumption of the DSA can be reduced, and the DSA can have high linearity; the presence of Rc1 and Rc2 can reduce power consumption, and the presence of Cc1 and Cc2 can provide ac ground for ac signals, specifically, when a large signal is coupled to the switching tube gate through the switching tube parasitic capacitances Cgs and Cds, can provide a path for the gate to ground, thereby making the output voltage of the inverter constant; specifically, rc1 and Rc2 are 10KΩ, cc1 and Cc2 are 0.5pF, and the output power P0.1dB is 30dbm@0.5-4GHz; the input third order intermodulation iip for the DSA zero decay state is at 49.6@0.5-4GHz.