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CN116230528B - Chip delamination method - Google Patents

Chip delamination method Download PDF

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Publication number
CN116230528B
CN116230528B CN202310297123.5A CN202310297123A CN116230528B CN 116230528 B CN116230528 B CN 116230528B CN 202310297123 A CN202310297123 A CN 202310297123A CN 116230528 B CN116230528 B CN 116230528B
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chip
layer
etching
grinding
level
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CN116230528A (en
Inventor
赵一成
邓龙
戴最初
宋健
李晓旻
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Shengke Nano Suzhou Co ltd
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Shengke Nano Suzhou Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

The invention provides a chip delamination method, which comprises the following steps: (1) Setting a compensation piece in a region outside the target chip to enable the target region to be positioned at the grinding center position, thereby obtaining a chip to be ground; (2) The chip to be ground is subjected to first grinding, and a first level is removed to obtain a first chip; (3) Slotting the periphery of the target area of the first chip to a substrate layer, performing second grinding, and removing a second level to obtain a second chip; (4) And (3) etching the second chip to remove the third level and finish the delamination. The chip delamination method provided by the invention can greatly improve the success rate of delamination aiming at advanced process chips.

Description

Chip delamination method
Technical Field
The invention relates to the technical field of chips, in particular to a chip delamination method.
Background
As the iterative chip minimum process of the prior process has come to the N4 node, the failure analysis technique associated therewith needs to be greatly improved. The chip failure analysis step generally comprises the following steps: a) Positioning the electric hot spot of the chip; b) Chip delamination-scanning electron microscope (Scanning electron microscope, SEM) layer by layer high-power observation of hot spot positions; c) The Nano probe (Nano-probe, NP) performs electrical inspection and analysis on the hot spot position; d) Performing structural inspection and characterization on the failure position with accurate positioning; e) And obtaining the failure reason.
Among the above 5 steps, b) the chip delamination is the most manually involved step, and the accuracy of the delamination operation is improved by performing multiple marking and prefabrication of the sample, which is required to be performed on the sample, in contrast to the failure analysis equipment, because the manual operation accuracy cannot reach the micrometer size.
With the continuous iteration of semiconductor processes, large-scale computing units and Systems On Chip (SOC) use 7nm and even more advanced 5nm processes, and for advanced processes above 7nm, no more sophisticated delamination process exists.
Disclosure of Invention
In view of the problems existing in the prior art, the invention provides a chip delamination method, in particular to a delamination method of an advanced process chip with the wavelength of more than 7nm, which can improve the delamination accuracy, reduce the corrosion risk of a metal interconnection layer in a target area and further improve the analysis success rate of the chip.
To achieve the purpose, the invention adopts the following technical scheme:
the invention provides a chip delamination method, which comprises the following steps:
(1) Setting a compensation piece in a region outside the target chip to enable the target region to be positioned at the grinding center position, thereby obtaining a chip to be ground;
(2) The chip to be ground is subjected to first grinding, and a first level is removed to obtain a first chip;
(3) Slotting the periphery of the target area of the first chip to a substrate layer, performing second grinding, and removing a second level to obtain a second chip;
(4) And (3) etching the second chip to remove the third level and finish the delamination.
Compared with the traditional delamination process, the chip delamination method provided by the invention has the advantages that firstly, the compensator is additionally arranged in the step (1), so that the target area (AimofInterest, AOI area) is positioned in the grinding center, the surface flatness of the target area after the first grinding is improved, the subsequent etching is more facilitated, secondly, the periphery of the target area is grooved in the step (3), the etching is introduced in the step (4), and the influence of water vapor in the manual grinding and the corrosion, extension and diffusion of copper metal lines generated in the grinding process are avoided on the third level; the important reason for using such a procedure is that at advanced processes above 7nm (i.e. sizes greater than 7nm, preferably 7nm to 14 nm), the metal interconnect line width, spacing and layer-to-layer spacing used in the third level are only between 10 and 20nm or even smaller, and the conventional manual grinding process is difficult to adapt to sample preparation at advanced processes above 7 nm.
The condition for layer-by-layer delamination using an etching apparatus at the third level is that the flatness of the target area is high when delamination is performed manually to the third level. The method comprises the steps of (1) setting a compensation piece to fill a target area to the center position, and further utilizing a laser window in the step (3) to position each layer of line to the center of the target area, wherein when the layer is manually ground to a third level, the middle position of the target area still has a larger part of a metal layer of the third level which is uniform and flat, so that the processing of etching equipment in the subsequent step is guaranteed.
The method provided by the invention can greatly improve the success rate of delamination to the third level, reduce the corrosion risk of the metal interconnection layer in the target area, and the used equipment is very common in a semiconductor test laboratory, is easy to operate after the process, and can improve the success rate of failure analysis experiments. The chip of the invention is especially an advanced process chip, and refers to a chip with a size of more than 7nm, such as a 7nm process chip and the like.
Preferably, the area of the target chip is more than or equal to 5mm 2 For example, it may be 5mm 2 、6mm 2 、7mm 2 、8mm 2 、9mm 2 、10mm 2 、11mm 2 、12mm 2 Or 15mm 2 And the like, but are not limited to the recited values, and other non-recited values within this range are equally applicable.
Preferably, the area of the target region is less than or equal to 100 μm 2 For example, it may be 100. Mu.m 2 、95μm 2 、93μm 2 、92μm 2 、90μm 2 、88μm 2 、87μm 2 、85μm 2 、80μm 2 、75μm 2 Or 70μm 2 And the like, but are not limited to the recited values, and other non-recited values within this range are equally applicable.
Preferably, the compensation member in step (1) includes a compensation chip.
Preferably, the first grinding in step (2) comprises manual grinding.
The first polishing method is preferably manual polishing to remove the layer (the periphery of the chip is provided with the compensation chip), and the removing method is to manually polish and remove the barrier layer on the surface of the chip on a polishing machine through polishing liquid, remove the dielectric layer by using a plasma etching machine (RIE), and simultaneously assist an acidic solution to remove the copper metal interconnection layer of the chip, so as to achieve the effect of removing the layer by layer. Preferably, the first ground slurry comprises a silica dispersion. Preferably, the silica dispersion is a nanoscale dispersion, i.e., the silica has a particle size of about 50nm.
Preferably, the solution for removing the metal layer in the first grinding comprises a dilute nitric acid solution.
Preferably, the concentration of the dilute nitric acid solution is 20-30 wt%, and may be 20wt%, 21wt%, 22wt%, 23wt%, 24wt%, 25wt%, 26wt%, 27wt%, 28wt%, 29wt%, 30wt%, or the like.
Preferably, the flatness of the first polished surface is 50 to 100nm, for example, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm or 100nm.
Preferably, the first level in step (2) comprises a metal layer having a thickness of 1-3 μm, for example, 1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2.0 μm, 2.5 μm or 3.0 μm.
Preferably, the metal line width in the first level is 10 to 30 μm, and may be, for example, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 30 μm, or the like.
Preferably, the slotting device in the step (3) comprises a laser unsealing machine.
Preferably, the side length of the area surrounded by the slot is 1.2-1.4 times of the side length of the target area, for example, 1.2, 1.21, 1.24, 1.25, 1.28, 1.30, 1.35 or 1.4 can be used.
Preferably, the width of the slot is 10 to 20 μm, for example, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, or the like.
Too wide a groove will cause accumulation of grinding fluid during the second grinding process, and also will cause a faster grinding speed at the edges of both sides of the groove, so that the desired flatness of the groove is difficult to achieve, whereas too narrow a groove cannot completely isolate the grinding areas, and cannot reduce the problem of too fast edge grinding, and also difficult to achieve the purpose of reducing flatness, therefore, the width of the groove is preferably 10-20 μm.
Preferably, the second grinding in step (3) comprises manual grinding.
Preferably, the second ground slurry comprises a silica dispersion.
Preferably, the second step layer includes a metal layer having a thickness of 30 to 70nm, and the thickness may be, for example, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, or the like.
Preferably, the line width of the metal in the second level is 20 to 40nm, for example, 20nm, 25nm, 27nm, 28nm, 30nm, 32nm, 35nm or 40nm, etc.
Preferably, the flatness of the second polished surface is 30-70 nm, for example, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm or 70nm, and the flatness of the second polished surface is not particularly limited by the present invention, and any polishing liquid which is known to those skilled in the art and can be used for chip polishing, for example, silicon oxide-based polishing liquid, etc., can be used, and the polishing machine is used for manual polishing.
Preferably, the third layer in step (4) comprises a metal layer having a thickness of 10-20 nm, for example, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm.
Preferably, the line width of the metal in the third level is 10 to 20nm, and may be, for example, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, or the like.
Preferably, the etching in the step (4) includes performing first etching to remove the first sub-layer in the third level, and performing a first electrical test; performing a second etching to remove a second sub-layer in the third level, and performing a second electrical test; and then carrying out third etching to remove a third sub-layer in the third layer and carrying out third electrical test.
The invention further preferably adopts a three-step etching and three-step electrical testing scheme to carry out subsequent delamination, so that electrical testing can be carried out on the metal layer in the third level, delamination can be carried out on the metal layer, SEMVC (Voltagerontast, VC, an electrical failure observation method can be accurately positioned to the failure position of a chip metal circuit) observation can be carried out layer by layer from the second sub-layer; and the electrical analysis of the nanoprobe can be carried out for the Via1 (Metal 1 Via) layer and the CT (Contact) layer respectively.
In the third level, because the thickness and line width of the metal are smaller, the better delamination effect is difficult to achieve by adopting a manual grinding mode.
Preferably, the first etching is a first plasma etching, an ion beam etching and a second plasma etching which are sequentially performed.
The invention preferably adopts the first plasma etching, the ion beam etching and the second plasma etching in sequence, wherein the first plasma etching can remove the silicon oxide layer between the metal wires, the ion beam etching can remove the metal layer of the layer, and the second plasma etching can slightly remove the interlayer oxide layer, so that the electrical test is conveniently carried out by the contact of the nano probe and the metal layer.
In theory, plasma beam etching can be adopted, but the method is only applicable to the situation that the upper layer and the lower layer of metal layers are few and the distance between the upper layer and the lower layer is small; in practical situations, the speed of ion beam etching is still a small difference between metal and oxide, and there is a difference of several nanometers per second, but the etching time is long because the thickness of the chip metal layer in the prior process reaches the thickness of the micrometer level, and an oxide layer is formed between the same level lines, so that the metal part of the current layer is etched completely by using ion beam etching, but the oxide between the metal lines still remains, and the residue remains until the next layer, so that the etching is uneven, and finally the complete inspection of the line is not performed, and the electrical correlation test of the nano probe is not performed.
If only plasma etching is adopted, the problem that the metal layer cannot be etched exists, if only ion beam etching is adopted, the current layer only needs to be etched by the ion beam, and the last layer of residual oxide can appear due to the fact that the metal layer on the surface of the chip is thick.
Preferably, the etching gas of the first plasma etching is CF 4 And O 2 。
Preferably, CF in the first plasma etching 4 And O 2 The gas flow rate ratio of (2) is 1 to 2:1, and may be, for example, 1:1, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, or 2:1, etc., but is not limited to the recited values, and other non-recited values within this range are equally applicable.
The power of the first plasma etching is preferably 50 to 100W, and may be, for example, 50W, 56W, 62W, 67W, 73W, 78W, 84W, 89W, 95W, or 100W, etc., but is not limited to the recited values, and other values not recited in the range are equally applicable.
Preferably, the time of the first plasma etching is 20 to 30s, for example, 20s, 22s, 23s, 24s, 25s, 26s, 27s, 28s, 29s or 30s, etc., but not limited to the recited values, and other non-recited values within the range are equally applicable.
Preferably, the first plasma etching removes the silicon oxide layer between the metal lines in the metal layer.
Preferably, the voltage of the ion beam etching is 300 to 600V, for example, 300V, 330V, 360V, 400V, 430V, 460V, 500V, 530V, 560V or 600V, etc., but the present invention is not limited to the recited values, and other non-recited values within the range are equally applicable.
The argon gas flow rate in the ion beam etching is preferably 15 to 35sccm, and may be, for example, 15sccm, 18sccm, 20sccm, 22sccm, 24sccm, 27sccm, 29sccm, 31sccm, 33sccm, 35sccm, or the like, but is not limited to the values recited, and other values not recited in the range are equally applicable.
Preferably, the beam current of the ion beam etching is 80-120 mA, for example, 80mA, 85mA, 89mA, 94mA, 98mA, 103mA, 107mA, 112mA, 116mA or 120mA, etc., but the ion beam etching method is not limited to the listed values, and other values not listed in the range are equally applicable.
Preferably, the ion beam etching time is 10 to 20s, for example, 10s, 12s, 13s, 14s, 15s, 16s, 17s, 18s, 19s or 20s, etc., but not limited to the recited values, and other non-recited values within the range are equally applicable.
Preferably, the ion beam etching removes the bulk layer in the metal layer.
Preferably, the etching gas of the second plasma etching is CHF 3 And O 2 。
Preferably, CHF in the second plasma etch 3 And O 2 The gas flow rate ratio of (2) is 0.6 to 2.5:1, and may be, for example, 0.6:1, 0.9:1, 1.1:1, 1.3:1, 1.5:1, 1.7:1, 1.9:1, 2.1:1, 2.3:1, or 2.5:1, etc., but is not limited to the recited values, and other non-recited values within this range are equally applicable.
The power of the second plasma etching is preferably 100 to 150W, and may be, for example, 100W, 106W, 112W, 117W, 123W, 128W, 134W, 139W, 145W, 150W, or the like, but is not limited to the values recited, and other values not recited in the range are equally applicable.
Preferably, the second plasma etching time is 5 to 10s, for example, 5s, 6s, 7s, 8s, 9s or 10s, but not limited to the recited values, and other non-recited values within the range are equally applicable.
Preferably, the second plasma etching removes an oxide layer between the metal layer and the next layer.
Preferably, the first electrical test comprises a scanning electron microscope voltage contrast test.
Preferably, the second etching and the third etching are each independently the same as the etching sequence of the first etching. Preferably, the second electrical test comprises a scanning electron microscope voltage contrast test and a nanoprobe test.
Preferably, the third etching is removed to the contact layer.
Preferably, the third electrical test comprises a scanning electron microscope voltage contrast test and a nanoprobe test.
As a preferable technical scheme of the invention, the chip delamination method comprises the following steps:
(1) Setting a compensation chip in a region outside the target chip to enable the target region to be positioned at the grinding center position, thereby obtaining a chip to be ground;
(2) Step (1) the chip to be ground is subjected to first grinding, wherein the first grinding is performed manually, a first level is removed, and the flatness of the surface of the first ground chip is 50-100 nm, so that a first chip is obtained;
(3) Slotting the periphery of the target area of the first chip to a substrate layer, wherein the slotting width is 10-20 mu m, the side length of an area surrounded by slotting is 1.2-1.4 times of the side length of the target area, and performing second grinding, wherein the second grinding is manual grinding, the second layer is removed, and the flatness of the surface of the second ground is 30-70 nm, so that the second chip is obtained;
(4) Step (3), the second chip is subjected to first etching, a first sub-layer in a third level is removed, and a first electrical test is performed; performing a second etching to remove a second sub-layer in the third level, and performing a second electrical test; and then carrying out third etching to remove the third sub-layer in the third layer to the contact layer, and carrying out a third electrical test to finish the delamination. The invention has no special requirement on the specific structure of the chip in the process, and the chip structure well known to the person skilled in the art can be adopted, and the chip structure can be adjusted according to the actual process.
Compared with the prior art, the invention has at least the following beneficial effects:
(1) The chip delamination method provided by the invention can be well applied to advanced process chips, and solves the chip delamination problem of 7 nm-14 nm;
(2) The chip delamination method provided by the invention reduces the corrosion risk of the metal interconnection layer in the target area, has high success rate of testing, and can reach more than 60%, preferably 100%;
(3) The device adopted by the chip delamination method provided by the invention is very common in a semiconductor test laboratory, is simple and convenient to operate after the process, obviously improves the success rate and is beneficial to the performance of failure analysis.
Drawings
FIG. 1 is a schematic diagram of a chip stack to be delaminated according to the present invention.
Fig. 2 is a schematic structural diagram of the present invention after the compensation chip is disposed.
Fig. 3 is a schematic structural view of the embodiment 1 of the present invention after grooving.
In the figure: 1-a target chip; 2-target area; 3-compensating chip; 4-silicon wafer; 5-slotting; 61-first level; 62-second level; 63-third level.
Detailed Description
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
The present invention will be described in further detail below. The following examples are merely illustrative of the present invention and are not intended to represent or limit the scope of the invention as defined in the claims.
It is to be understood that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
For the purpose of the experiments, the polishing liquids used in the following examples and comparative examples were commercial Allied50nm silica dispersion, but it is not intended to represent that the present invention can only be used with the following polishing liquids, and other polishing liquids that can be used for chip polishing can be used in the present invention.
Also for the convenience of experiments, the stacked structure of the chips used in the following examples and comparative examples is shown in fig. 1, and it can be seen from fig. 1 that M1 to M11 in fig. 1 represent 11 metal layers; the chip comprises a polysilicon layer, a first level 61, a second level 62 and a third level 63 which are sequentially overlapped; the first level comprises M11-M9 metal layers; the second level comprises four metal layers M8-M5; the third level comprises 4 metal layers from M4 to M1; wherein the first sub-layer is an M4 layer and an M3 layer; the second sub-layer is an M2 layer; the first sub-layer is an M1 layer. The Metal layer is not represented as a Metal copper layer, but each layer only contains Metal copper, and can be implemented by referring to a chip structure conventional in the art, and the Metal layer further comprises an oxide layer between the Metal layers, a silicon oxide layer between the Metal wires, and other materials, which are not particularly limited.
Example 1
The embodiment provides a chip delamination method, which comprises the following steps:
(1) The target chip 1 is arranged on the silicon wafer 4, and the compensation chip 3 is arranged in the area outside the target chip 1, so that the target area 2 is positioned at the grinding center, as shown in fig. 2, to obtain a chip to be ground;
(2) Step (1) the chip to be ground is subjected to first grinding, wherein the first grinding is performed manually, a first level is removed, and the flatness of the surface of the first ground chip is 55nm, so that a first chip is obtained;
(3) The periphery of the target area 2 of the first chip is grooved to a substrate layer, as shown in fig. 3, the width of the groove 5 is 15 μm, the side length of the area surrounded by the groove 5 is 1.25 times of the side length of the target area 2, and a second grinding is performed, wherein the second grinding is manual grinding, the second layer is removed, and the flatness of the surface after the second grinding is 35 μm, so that the second chip is obtained;
(4) Step (3), the second chip is subjected to first etching, a first sub-layer in a third level is removed, and a first electrical test is performed; the first electrical test comprises a scanning electron microscope voltage contrast test;
specifically, the first etching is a first plasma etching, an ion beam etching and a second plasma etching which are sequentially performed, and the etching gas of the first plasma etching is CF 4 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the CF in the first plasma etching 4 And O 2 The gas flow ratio of (2) is 1.1:1; the power of the first plasma etching is 50W; the time of the first plasma etching is 25s; removing the silicon oxide layer between the metal wires in the metal layer by the first plasma etching; the voltage of the ion beam etching is 500V; the argon flow of the ion beam etching is 25sccm; the beam current of the ion beam etching is 90mA; the etching time of the ion beam is 15s; removing a main body layer in the metal layer by ion beam etching; the etching gas of the second plasma etching is CHF 3 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the CHF in the second plasma etch 3 And O 2 The gas flow ratio of (2) is 1.0:1; the power of the second plasma etching is 120W; the second plasma etching time is 8s;
performing a second etching to remove a second sub-layer in the third level, wherein the process of the second etching is the same as that of the first etching (specific process parameters can be adjusted according to the layer thickness), and performing a second electrical test, wherein the second electrical test comprises a scanning electron microscope voltage contrast test and a nano probe test; and then carrying out third etching, wherein the process of the third etching is the same as that of the first etching (specific process parameters can be adjusted according to the layer thickness), removing a third sub-layer in a third layer to the contact layer, and carrying out a third electrical test, wherein the third electrical test comprises a scanning electron microscope voltage contrast test and a nano probe test, so as to finish the layer removal.
Example 2
The embodiment provides a chip delamination method, which comprises the following steps:
(1) Setting a compensation chip in a region outside the target chip, so that the target region is positioned at the grinding center, as shown in fig. 2, to obtain a chip to be ground;
(2) Step (1) the chip to be ground is subjected to first grinding, wherein the first grinding is performed manually, a first level is removed, and the flatness of the surface of the first ground chip is 60nm, so that a first chip is obtained;
(3) Slotting the periphery of the target area of the first chip to a substrate layer, wherein the slotting width is 20 mu m, the side length of an area surrounded by slotting is 1.3 times of the side length of the target area, and performing second grinding, wherein the second grinding is manual grinding, the second layer is removed, and the flatness of the surface of the second ground is 40nm, so that a second chip is obtained;
(4) Step (3), the second chip is subjected to first etching, a first sub-layer in a third level is removed, and a first electrical test is performed; the first electrical test comprises a scanning electron microscope voltage contrast test;
specifically, the first etching is a first plasma etching, an ion beam etching and a second plasma etching which are sequentially performed, and the etching gas of the first plasma etching is CF 4 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the CF in the first plasma etching 4 And O 2 The gas flow ratio of (2) is 1.2:1; the power of the first plasma etching is 100W; the time of the first plasma etching is 20s; removing the silicon oxide layer between the metal wires in the metal layer by the first plasma etching; the voltage of the ion beam etching is 600V; the argon flow of the ion beam etching is 35sccm; the beam current of the ion beam etching is 120mA; the etching time of the ion beam is 10s; removing a main body layer in the metal layer by ion beam etching; the etching gas of the second plasma etching is CHF 3 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the CHF in the second plasma etch 3 And O 2 The gas flow ratio of (2) is 2.5:1; the power of the second plasma etching is 150W; the second plasma etching time is 10s;
performing a second etching to remove a second sub-layer in the third level, wherein the process of the second etching is the same as that of the first etching (specific process parameters can be adjusted according to the layer thickness), and performing a second electrical test, wherein the second electrical test comprises a scanning electron microscope voltage contrast test and a nano probe test; and then carrying out third etching, wherein the process of the third etching is the same as that of the first etching (specific process parameters can be adjusted according to the layer thickness), removing a third sub-layer in a third layer to the contact layer, and carrying out a third electrical test, wherein the third electrical test comprises a scanning electron microscope voltage contrast test and a nano probe test, so as to finish the layer removal.
Example 3
The embodiment provides a chip delamination method, which comprises the following steps:
(1) Setting a compensation chip in a region outside the target chip, so that the target region is positioned at the grinding center, as shown in fig. 2, to obtain a chip to be ground;
(2) Step (1) the chip to be ground is subjected to first grinding, wherein the first grinding is performed manually, a first level is removed, and the flatness of the surface of the first ground chip is 55nm, so that a first chip is obtained;
(3) Slotting the periphery of the target area of the first chip to a substrate layer, wherein the slotting width is 10 mu m, the side length of an area surrounded by slotting is 1.4 times of the side length of the target area, and performing second grinding, wherein the second grinding is manual grinding, the second layer is removed, and the flatness of the surface of the second ground is 30nm, so that a second chip is obtained;
(4) Step (3), the second chip is subjected to first etching, a first sub-layer in a third level is removed, and a first electrical test is performed; the first electrical test comprises a scanning electron microscope voltage contrast test;
specifically, the describedThe first etching is sequentially performed by first plasma etching, ion beam etching and second plasma etching, and the etching gas of the first plasma etching is CF 4 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the CF in the first plasma etching 4 And O 2 The gas flow ratio of (2) is 0.8:1; the power of the first plasma etching is 50W; the time of the first plasma etching is 30s; removing the silicon oxide layer between the metal wires in the metal layer by the first plasma etching; the voltage of the ion beam etching is 300V; the argon flow of the ion beam etching is 15sccm; the beam current of the ion beam etching is 80mA; the etching time of the ion beam is 20s; removing a main body layer in the metal layer by ion beam etching; the etching gas of the second plasma etching is CHF 3 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the CHF in the second plasma etch 3 And O 2 The gas flow ratio of (2) is 0.6:1; the power of the second plasma etching is 100W; the second plasma etching time is 5s;
performing a second etching to remove a second sub-layer in the third level, wherein the process of the second etching is the same as that of the first etching (specific process parameters can be adjusted according to the layer thickness), and performing a second electrical test, wherein the second electrical test comprises a scanning electron microscope voltage contrast test and a nano probe test; and then carrying out third etching, wherein the process of the third etching is the same as that of the first etching (specific process parameters can be adjusted according to the layer thickness), removing a third sub-layer in a third layer to the contact layer, and carrying out a third electrical test, wherein the third electrical test comprises a scanning electron microscope voltage contrast test and a nano probe test, so as to finish the layer removal.
Example 4
The present embodiment provides a chip delamination method, which is the same as that of embodiment 1 except that the width of the slot in step (3) is only 5 μm.
Example 5
The present embodiment provides a chip delamination method, which is the same as that of embodiment 1 except that the width of the slot in step (3) is 30 μm.
Example 6
The present embodiment provides a method for removing a chip, which is the same as that of embodiment 1 except that all etching in step (4) is performed by plasma etching.
Example 7
The present embodiment provides a method for removing a chip, which is the same as that of embodiment 1 except that all etching in step (4) is performed by ion beam etching.
Comparative example 1
This comparative example provides a chip delamination method which is the same as in example 1 except that no compensation chip is provided in step (1).
In this comparative example, since the compensation chip was not provided, the surface flatness value of the target area in the process of manual polishing was high, and the flatness (i.e., the difference between the maximum value and the minimum value of the heights after 5 test points were selected for testing) was 89nm, which was inferior to that in example 1.
Comparative example 2
This comparative example provides a chip delamination method which is the same as in example 1 except that no slot is formed in step (3).
The comparative example had a higher surface flatness value for the target area during the second grinding process due to the lack of grooves, and the flatness (i.e., the difference between the maximum value and the minimum value of the heights after 5 test points were selected for testing) was 180nm, which was inferior to that in example 1.
Comparative example 3
The present comparative example provides a method for removing a chip, which is the same as example 1 except that in step (1), a compensation chip is not provided, the periphery of the target area is directly grooved to the substrate layer, and then the first polishing and the second polishing in example 1 are sequentially performed.
The purpose of using the compensation chip in the invention is to keep the target area in a flat state even if the target area is close to the edge of the chip; if the compensation chip is not arranged, grooving can occur at the beginning, the grooving area can be longer than the method in the embodiment 1 due to the fact that grinding by using grinding agents is used, so that uneven grinding can be caused due to the fact that excessive grinding can occur on two sides of the grooving, and the flatness of the target area after second grinding is 160nm and is worse than that of the embodiment 1.
Comparative example 4
This comparative example provides a method of removing a chip, which is the same as example 1 except that the etching method is not used in step (4), and the polishing method is still used (the parameters of polishing refer to the first polishing).
For the above examples and comparative examples, 20 chip samples were selected for testing, the chip was a 5nm process chip, and the area of the target chip was 10000 μm 2 The area of the target region was 100. Mu.m 2 And (5) counting the success rate of the test.
The test results of the above examples and comparative examples are shown in table 1.
TABLE 1
Success rate (%)
Example 1 100
Example 2 100
Example 3 100
Example 4 90
Example 5 95
Example 6 60
Example 7 65
Comparative example 1 10
Comparative example 2 15
Comparative example 3 20
Comparative example 4 0
From table 1, the following points can be seen:
(1) As can be seen from comprehensive examples 1-3, the chip delamination method provided by the invention has high success rate of delamination for chips of 7 nm-14 nm, which is basically 100%;
(2) It can be seen from the combination of examples 1 and examples 4 to 5 that the width of the slot in example 1 is 15 μm, the success rate of the delamination in example 1 is 100% compared with the width of the slot in examples 4 to 5 being 5 μm and 30 μm, respectively, and the success rate of the delamination in examples 4 to 5 being only 90% and 95%, respectively, thus showing that the invention further improves the success rate of the delamination by controlling the width of the slot in a specific range;
(3) As can be seen from the combination of embodiment 1 and embodiments 6 to 7, in embodiment 1, the etching method of combining plasma etching and ion beam etching is adopted for the third level, and compared with the etching method of only one etching method in embodiments 6 to 7, the success rate in embodiment 1 is significantly higher than that in embodiments 6 to 7, so that the success rate of etching is improved by adopting the etching method of combining ion etching and ion beam etching;
(4) As can be seen from the comprehensive examples 1 and comparative examples 1 to 4, the success rates in comparative examples 1 to 4 are only 10%, 15%, 20% and 0 respectively, which is far lower than 100% in example 1, so that it is shown that the invention improves the success rate of delamination by adopting the compensation chip and grooving mode to make the flatness of the first grinding and the second grinding higher, and at the same time, by adopting the mode of combining grinding and etching to adopt different delamination methods for different layers, the success rate of delamination is significantly improved.
The applicant declares that the above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and it should be apparent to those skilled in the art that any changes or substitutions that are easily conceivable within the technical scope of the present invention disclosed by the present invention fall within the scope of the present invention and the disclosure.

Claims (39)

1. A chip delamination method, characterized in that the chip delamination method comprises:
(1) Setting a compensation piece in a region outside the target chip to enable the target region to be positioned at the grinding center position, thereby obtaining a chip to be ground;
(2) The chip to be ground is subjected to first grinding, and a first level is removed to obtain a first chip;
(3) Slotting the periphery of the target area of the first chip to a substrate layer, performing second grinding, and removing a second level to obtain a second chip;
(4) Step (3) the second chip is etched to remove a third level, and the layer removal is completed, wherein the etching in step (4) comprises the steps of firstly performing first etching to remove a first sub-layer in the third level, and performing first electrical test; performing a second etching to remove a second sub-layer in the third level, and performing a second electrical test; then third etching is carried out to remove a third sub-layer in a third hierarchy and third electrical testing is carried out; the first etching is first plasma etching, ion beam etching and second plasma etching which are sequentially carried out; the second etching and the third etching are respectively and independently the same as the etching sequence of the first etching;
the target chip is a chip of 7 nm-14 nm process.
2. The method of claim 1, wherein the compensator in step (1) comprises a compensator chip.
3. The method of claim 1, wherein the first grinding in step (2) comprises manual grinding.
4. The method of claim 1, wherein the first abrasive slurry comprises a silica dispersion.
5. The method of claim 1, wherein the solution for removing the metal layer in the first grinding comprises a dilute nitric acid solution.
6. The method for removing a layer of a chip according to claim 5, wherein the concentration of the dilute nitric acid solution is 20-30wt%.
7. The method for removing a layer of a chip according to claim 1, wherein the flatness of the surface after the first polishing is 50-100 nm.
8. A method according to any one of claims 1 to 3, wherein the first level in step (2) comprises a metal layer having a thickness of 1 to 3 μm.
9. The method of claim 1, wherein the metal line width in the first level is 10-30 μm.
10. The method for removing a layer of a chip according to any one of claims 1 to 4, wherein the slotting device in the step (3) comprises a laser opener.
11. The method for removing a layer of a chip according to claim 1, wherein the side length of the area surrounded by the slot is 1.2-1.4 times the side length of the target area.
12. The method for removing a layer of a chip according to claim 11, wherein the width of the slot is 10-20 μm.
13. The method of claim 1, wherein the second grinding in step (3) comprises manual grinding.
14. The method of claim 1, wherein the second abrasive slurry comprises a silica dispersion.
15. The method for removing a layer of a chip according to claim 1, wherein the second step comprises a metal layer with a thickness of 30-70 nm.
16. The method of claim 1, wherein the metal line width in the second level is 20-40 nm.
17. The method for removing a layer of a chip according to claim 1, wherein the flatness of the second polished surface is 30-70 nm.
18. The method of claim 1-6, wherein the third level in step (4) comprises a metal layer having a thickness of 10-20 nm.
19. The method of claim 1, wherein the line width of the metal in the third level is 10-20 nm.
20. The method of claim 1, wherein the etching gas of the first plasma etching is CF 4 And O 2 。
21. The method of claim 1, wherein the CF in the first plasma etch 4 And O 2 The gas flow ratio of (2) is 0.8-1.2:1.
22. The method for removing a layer of a chip according to claim 1, wherein the power of the first plasma etching is 50-100 w.
23. The method for removing a layer of a chip according to claim 1, wherein the time of the first plasma etching is 20-30 s.
24. The method of claim 1, wherein the first plasma etch removes a silicon oxide layer between metal lines in the metal layer.
25. The method of claim 1, wherein the ion beam etching voltage is 300-600 v.
26. The method for removing a chip layer according to claim 1, wherein the argon flow of the ion beam etching is 15-35 sccm.
27. The method of claim 1, wherein the ion beam etching beam current is 80-120 ma.
28. The method of claim 1, wherein the ion beam etching time is 10-20 s.
29. The method of claim 1, wherein the ion beam etching removes a bulk layer from the metal layer.
30. The method of claim 1, wherein the etching gas of the second plasma etching is CHF 3 And O 2 。
31. The method of claim 1, wherein CHF in the second plasma etch 3 And O 2 The gas flow ratio of (2) is 1-2:1.
32. The method for removing a layer of a chip according to claim 1, wherein the power of the second plasma etching is 100-150 w.
33. The method for removing a layer of a chip according to claim 1, wherein the time of the second plasma etching is 5-10 s.
34. The method of claim 1, wherein the second plasma etch removes an oxide layer between a metal layer and a next layer.
35. The method of claim 1, wherein the first electrical test comprises a scanning electron microscope voltage contrast test.
36. The method of claim 1, wherein the second electrical test comprises a scanning electron microscope voltage contrast test and a nanoprobe test.
37. The method of claim 1, wherein the third etch is removed to the contact layer.
38. The method of claim 1, wherein the third electrical test comprises a scanning electron microscope voltage contrast test and a nanoprobe test.
39. The chip delamination method according to any one of claims 1 to 7, wherein the chip delamination method comprises the steps of:
(1) Setting a compensation chip in a region outside the target chip to enable the target region to be positioned at the grinding center position, thereby obtaining a chip to be ground;
(2) Step (1) the chip to be ground is subjected to first grinding, wherein the first grinding is performed manually, a first level is removed, and the flatness of the surface of the first ground is 50-100 nm, so that a first chip is obtained;
(3) Slotting the periphery of the target area of the first chip to a substrate layer, wherein the slotting width is 10-20 mu m, the side length of an area surrounded by slotting is 1.2-1.4 times of the side length of the target area, and performing second grinding, wherein the second grinding is manual grinding, the second layer is removed, and the flatness of the surface of the second ground is 30-70 nm, so that the second chip is obtained;
(4) Step (3), the second chip is subjected to first etching, a first sub-layer in a third level is removed, and a first electrical test is performed; performing a second etching to remove a second sub-layer in the third level, and performing a second electrical test; and then carrying out third etching to remove the third sub-layer in the third layer to the contact layer, and carrying out a third electrical test to finish the delamination.
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