CN116203808A - Overlay error measurement method and overlay mark - Google Patents
Overlay error measurement method and overlay mark Download PDFInfo
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- CN116203808A CN116203808A CN202310425677.9A CN202310425677A CN116203808A CN 116203808 A CN116203808 A CN 116203808A CN 202310425677 A CN202310425677 A CN 202310425677A CN 116203808 A CN116203808 A CN 116203808A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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Abstract
The embodiment of the disclosure provides a method for measuring overlay error and an overlay mark, wherein the method for measuring the overlay error comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of chip areas and cutting channel areas positioned between adjacent chip areas, and each chip area comprises an array area and a peripheral area positioned at the periphery of the array area; providing a first overlay mark, wherein the first overlay mark corresponds to the peripheral area, and comprises a plurality of first sub-marks which are arranged in a regular array; performing multiple pattern transfer steps, wherein in each pattern transfer step, the first overlay mark is transferred to the peripheral area so as to form a front layer first overlay mark and a current layer first overlay mark in the peripheral area; and acquiring a first overlay error based on the relative position relation between the first overlay mark of the front layer and the first overlay mark of the current layer. The overlay error measurement method provided by the embodiment of the disclosure can at least improve the overlay error measurement precision.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductor manufacturing, in particular to a measurement method of overlay error and an overlay mark.
Background
Photolithography is a process of transferring a mask pattern onto a wafer through a series of steps such as alignment, exposure, etc., and in the process of manufacturing semiconductor chips, the entire manufacturing process is completed through a multi-layer photolithography process.
With the development of semiconductor manufacturing technology and the development of integrated circuit design and manufacturing, photolithography processes have been developed accordingly, and the feature sizes of semiconductor devices have been continuously reduced. In order to achieve good product performance and high yield, how to control the alignment of the layer pattern with the front layer pattern (pattern on the substrate) to meet the overlay accuracy (overlay) requirement, which is a critical step in the multi-layer lithography process, refers to the alignment error of the layer of the substrate with respect to the lithographic pattern of the layer. In order to improve the overlay accuracy, a system for measuring the position alignment error between the current layer lithography pattern and the previous layer lithography pattern is proposed, which is called a lithography overlay measurement system. When the overlay mark (overlay mark) is arranged in each of the layer lithography pattern and the front layer lithography pattern, the overlay accuracy is obtained by measuring the position difference between the overlay marks.
However, the current method for measuring overlay marks needs to be improved.
Disclosure of Invention
The embodiment of the disclosure provides a method for measuring overlay error and an overlay mark, which are at least beneficial to improving the measurement accuracy of the overlay error.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for measuring overlay error, including: providing a substrate, wherein the substrate comprises a plurality of chip areas and cutting channel areas positioned between adjacent chip areas, and each chip area comprises an array area and a peripheral area positioned at the periphery of the array area; providing a first overlay mark, wherein the first overlay mark corresponds to the peripheral area, and comprises a plurality of first sub-marks which are regularly arranged in an array; performing a plurality of pattern transfer steps, wherein each pattern transfer step transfers the first overlay mark into the peripheral area to form a front layer first overlay mark and a current layer first overlay mark in the peripheral area; and acquiring a first overlay error based on the relative position relation between the first overlay mark of the front layer and the first overlay mark of the current layer.
In some embodiments, the performing multiple pattern transfer steps includes: forming a front-layer mask layer on the substrate, wherein the front-layer mask layer is provided with the first overlay mark; performing a first etching process on the substrate by taking the front layer mask layer as a mask so as to form a front layer first overlay mark in the peripheral region; removing the front mask layer; forming a current layer mask layer on the substrate, wherein the current layer mask layer is provided with the first overlay mark; taking the current layer mask layer as a mask, and performing a second etching process on the substrate to form a first overlay mark of the current layer in the peripheral region; and removing the mask layer of the current layer.
In some embodiments, the metrology method further includes obtaining a post-development overlay error corresponding to the peripheral region based on the front layer first overlay mark and the first overlay mark in the current layer mask layer.
In some embodiments, in the step of providing the first overlay mark, a second overlay mark is further provided, and the second overlay mark includes a plurality of second sub-marks arranged in a regular array, where the second overlay mark corresponds to the array region; the step of performing multiple pattern transfer includes: transferring the second overlay mark to the array region in each pattern transferring step to form a front layer second overlay mark and a current layer second overlay mark in the array region; and acquiring a second overlay error corresponding to the array region based on the relative position relation between the front layer second overlay mark and the current layer second overlay mark.
In some embodiments, in the step of providing the first overlay mark, at least one of the first overlay marks corresponds to the scribe line region; the step of performing multiple pattern transfer includes: and transferring the first overlay mark into the cutting channel region in each pattern transferring step so as to form the front layer first overlay mark and the current layer first overlay mark in the cutting channel region.
In some embodiments, the method of obtaining the first overlay error includes: obtaining a first relative position relation between the first overlay mark of the front layer and the first overlay mark of the current layer by adopting an IDM measurement mode; acquiring a preliminary overlay error based on the first relative position relationship; acquiring a second relative position relationship based on the first overlay mark of the front layer and the first overlay mark of the current layer by adopting an electron beam scanning mode; and calibrating the preliminary overlay error based on the second relative position relationship to obtain the first overlay error.
According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure provides an overlay mark for overlay error measurement, applied to a substrate including a plurality of chip regions and scribe line regions between adjacent chip regions, each chip region including an array region and a peripheral region located at a periphery of the array region; the overlay mark includes: the first overlay mark corresponds to the peripheral area, and comprises a plurality of first sub-marks which are arranged in a regular array.
In some embodiments, further comprising: and the second overlay mark corresponds to the array region and comprises a plurality of second sub-marks which are regularly arranged in an array.
In some embodiments, at least one of the first overlay marks further corresponds to the scribe line region.
In some embodiments, the first sub-mark includes a plurality of first stripe patterns spaced apart along a first direction and a second direction, wherein the plurality of first stripe patterns spaced apart along the first direction and the second direction intersect at a center of the first sub-mark.
In some embodiments, the first sub-mark comprises a plurality of first stripe patterns, including at least a first stripe pattern located in a central region of the first sub-mark, the first stripe pattern located in an edge region of the first sub-mark.
In some embodiments, the first sub-mark includes a plurality of second stripe patterns and a plurality of third stripe patterns, a part of the second stripe patterns are arranged along a first direction in a central area of the first sub-mark, another part of the second stripe patterns are located in edge areas on two opposite sides of the central area along a second direction, the plurality of third stripe patterns are located in edge areas on two opposite sides of the central area along the first direction, wherein the second stripe patterns of the central area and the third stripe patterns of the edge areas extend along the second direction, the second stripe patterns of the edge areas extend along the first direction, the second stripe patterns and the third stripe patterns have different sizes, and the first direction and the second direction are mutually perpendicular.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
the method for measuring the overlay error provided by the embodiment of the disclosure provides a first overlay mark corresponding to a peripheral area of a substrate, and transfers the first overlay mark into the peripheral area through a plurality of pattern transfer steps to form a front layer first overlay mark and a current layer first overlay mark in the peripheral area, and obtains the first overlay error based on the relative position relation between the front layer first overlay mark and the current layer first overlay mark, wherein the first overlay mark is composed of a plurality of first sub-marks arranged in a regular array, and the front layer first overlay mark and the current layer first overlay mark are also composed of a plurality of first sub-marks arranged in a regular array.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a flowchart corresponding to a method for measuring overlay error according to an embodiment of the disclosure;
FIG. 2 is a schematic top view of an overlay mark according to one embodiment of the present disclosure;
FIG. 3 is a first schematic top view of a first overlay mark according to one embodiment of the present disclosure;
FIG. 4 is a second schematic top view of a first overlay mark according to one embodiment of the present disclosure;
FIG. 5 is a first schematic top view of a first sub-mark according to one embodiment of the present disclosure;
FIG. 6 is a third schematic top view of a first overlay mark according to one embodiment of the present disclosure;
FIG. 7 is a second top view schematic of a first sub-marking provided in an embodiment of the present disclosure;
FIG. 8 is a fourth schematic top view of a first overlay mark according to an embodiment of the present disclosure;
FIG. 9 is a third schematic top view of a first sub-mark according to one embodiment of the present disclosure;
FIG. 10 is a fifth schematic top view of a first overlay mark according to an embodiment of the present disclosure;
FIG. 11 is a first schematic top view of a second overlay mark according to an embodiment of the present disclosure;
fig. 12 is a second schematic top view of a second overlay mark according to an embodiment of the disclosure.
Detailed Description
As known from the background art, the current overlay error measurement method needs to be improved.
Analysis finds that the IDM technique (In Die Measurement, novel diffraction measurement technique) is generally applied to post-etching detection, wherein the post-etching detection is to measure overlay errors between different layers of a substrate after patterns in different mask layers on the substrate are sequentially transferred to different layers of the substrate, and the overlay errors can be measured by using the IDM technique without setting specific measurement marks in the process of measuring the overlay errors, but using the original patterns of a semiconductor structure, however, because patterns of structures of each layer in a peripheral region are irregular, the measured result errors are larger in the process of measuring the overlay errors between layers of the peripheral region by using the IDM technique; in the related art, an electron beam device (E-beam) is used to measure overlay errors in the peripheral area, however, the electron beam device has a slower Throughput (Throughput), which is not beneficial to reducing the measurement time of the overlay errors and affects the measurement efficiency.
The embodiment of the disclosure provides a method for measuring an overlay error, which comprises the steps of providing a first overlay mark, and performing multiple pattern transfer steps, wherein the first overlay mark is transferred to a peripheral area in each pattern transfer step to form a front layer first overlay mark and a current layer first overlay mark in the peripheral area, the front layer first overlay mark is formed in the peripheral area before the current layer first overlay mark, and the formed front layer first overlay mark and the current layer first overlay mark are also formed by a plurality of first sub-marks arranged in a regular array as the first overlay mark comprises a plurality of first sub-marks arranged in the regular array; and acquiring a first overlay error based on the relative positions of the front layer first overlay mark and the current layer first overlay mark, wherein the front layer first overlay mark and the current layer first overlay mark are formed by a plurality of first sub-marks arranged in a regular array, so that the front layer first overlay mark and the current layer overlay mark with regular patterns are favorable for improving the accuracy of the first overlay error.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 1 is a flowchart corresponding to a method for measuring overlay error according to an embodiment of the present disclosure, fig. 2 is a schematic top view of an overlay mark according to an embodiment of the present disclosure, fig. 3 is a schematic top view of a first overlay mark according to an embodiment of the present disclosure, and fig. 11 is a schematic top view of a second overlay mark according to an embodiment of the present disclosure.
Referring to fig. 1 and 2, S10: a substrate 100 is provided, the substrate 100 including a plurality of chip regions 101 and scribe line regions 102 between adjacent chip regions 101, each chip region 101 including an array region 103 and a peripheral region 104 located at a periphery of the array region 103. In fig. 2, a large dashed box illustrates a chip area 101, a small dashed box illustrates an array area 103, and a region where the large dashed box does not overlap with the small dashed box illustrates a peripheral area 104.
The substrate 100 may be a semiconductor substrate or a silicon-on-insulator substrate 100. In some embodiments, the substrate 100 may be a silicon substrate. In some embodiments, the substrate 100 may also be a germanium substrate, a silicon carbide substrate, or the like.
Referring to fig. 1 and 3, S11: providing a first overlay mark 105, wherein the first overlay mark 105 corresponds to the peripheral region 104, and the first overlay mark 105 comprises a plurality of first sub-marks 106 arranged in a regular array, so that after forming a corresponding front layer first overlay mark and a current layer first overlay mark according to the first overlay mark 105, the front layer first overlay mark and the current layer first overlay mark also have a plurality of first sub-marks 106 arranged in a regular array, and the overlay mark with the sub-marks arranged in a regular array is beneficial to improving the overlay error accuracy measured by adopting the overlay mark, so that the overlay error accuracy of the peripheral region 104 measured in a subsequent manner is higher.
In some embodiments, the at least one first overlay mark 105 further corresponds to the scribe line region 102, and is used for forming corresponding first overlay marks of the front layer and the first overlay mark of the current layer in the scribe line region 102 later, so as to measure an overlay error of the scribe line region 102 based on a relative positional relationship between the first overlay mark of the front layer and the first overlay mark of the current layer, and since the first overlay mark of the front layer and the first overlay mark of the current layer also have a plurality of first sub-marks 106 arranged in a regular array, the overlay marks with the sub-marks arranged in a regular array are beneficial to improving an overlay error accuracy measured by using the overlay mark amount, so that the overlay error accuracy of the scribe line region 102 measured later is higher.
Referring to fig. 11, in some embodiments, in the step of providing the first overlay mark 105, a second overlay mark 107 is further provided, where the second overlay mark 107 includes a plurality of second sub-marks 109 arranged in a regular array, the second overlay mark 107 corresponds to the array area 103, and the second overlay mark 107 is used to form a front layer second overlay mark and a current layer second overlay mark that are subsequently located in the array area 103, and the front layer second overlay mark and the current layer second overlay mark also have a plurality of second sub-marks 109 arranged in a regular array, which is beneficial to improving the accuracy of the overlay error of the array area 103 measured subsequently.
Referring to fig. 1, 2 and 3, S12: the pattern transfer steps are performed multiple times, and the first overlay mark 105 is transferred to the peripheral region 104 in each pattern transfer step, so as to form a front layer first overlay mark and a current layer first overlay mark in the peripheral region 104, wherein the front layer first overlay mark is formed in the substrate 100 before the current layer first overlay mark.
In some embodiments, the step of performing multiple pattern transfers may include: forming a front mask layer on the substrate 100, the front mask layer having a first overlay mark 105; performing a first etching process on the substrate 100 by using the previous mask layer as a mask to form a previous first overlay mark in the peripheral region 104; removing the front mask layer; forming a current layer mask layer on the substrate 100, the current layer mask layer having a first overlay mark 105; performing a second etching process on the substrate 100 by using the current layer mask layer as a mask, so as to form a current layer first overlay mark in the peripheral region 104; and removing the mask layer of the current layer.
The materials of the front layer mask layer and the current layer mask layer can be photoresist.
In some embodiments, based on the first overlay mark of the front layer and the first overlay mark 105 in the current layer mask layer, a post-development overlay error corresponding to the peripheral region 104 is obtained, and according to the obtained overlay error, it is determined whether the pattern in the current layer mask layer in the peripheral region 104 is aligned with the pattern in the front layer (the pattern in the front layer is the pattern formed in the peripheral region 104 in synchronization with the first overlay mark of the front layer), if not, the current layer mask layer may be replaced, or related parameters of the second etching process may be adjusted, so as to ensure that the pattern in the front layer in the peripheral region 104 and the pattern in the current layer mask layer can be aligned, thereby ensuring that the subsequent corresponding formation is properly connected with the device in the substrate 100.
Because the at least one first overlay mark 105 corresponds to the scribe line region 102, in some embodiments, performing multiple pattern transfer steps may include: in each pattern transferring step, the first overlay mark 105 is transferred to the scribe line region 102 to form a front layer first overlay mark and a current layer first overlay mark in the scribe line region 102, so as to measure the overlay error of the scribe line region 102 by the overlay mark of the scribe line region 102.
The foregoing steps may further provide a second overlay mark 107, and in some embodiments, in performing multiple pattern transfer steps, the second overlay mark 107 is further transferred into the array region 103 in each pattern transfer step, so as to form a front layer second overlay mark and a current layer second overlay mark in the array region 103, and the overlay error between the front layer and the current layer of the array region is measured by the front layer second overlay mark and the current layer second overlay mark.
Referring to fig. 1, S13: and acquiring a first overlay error based on the relative position relation between the first overlay mark of the front layer and the first overlay mark of the current layer. The first overlay error of the front layer and the first overlay error of the current layer are formed by a plurality of first sub-marks 106 arranged in a regular array, which is beneficial to improving the accuracy of the overlay error measured by the first overlay mark of the front layer and the first overlay mark of the current layer, i.e. improving the accuracy of the first overlay error.
The foregoing steps may further form at least one first overlay mark of the front layer and at least one first overlay mark of the current layer in the scribe line region 102, and in some embodiments, the first overlay error of the peripheral region 104 may be obtained based on the relative position relationship between the first overlay mark of the front layer and the first overlay mark of the current layer in the peripheral region 104, and the first overlay error of the scribe line region 102 may be obtained based on the relative position relationship between the first overlay mark of the front layer and the first overlay mark of the current layer in the scribe line region 102.
In some embodiments, a method of obtaining a first overlay error may include: obtaining a first relative position relation between a first overlay mark of a front layer and a first overlay mark of a current layer by adopting an IDM measurement mode; based on the first relative position relationship, a preliminary overlay error is obtained, and because the first overlay mark of the front layer and the first overlay mark of the current layer are formed by the first sub-marks 106 which are arranged in a regular array, the phenomenon that the error of the result measured by adopting the IDM technology is larger due to irregular mark patterns of the peripheral region 104 can be avoided, and the accuracy of the preliminary overlay error is improved; acquiring a second relative position relation based on the first overlay mark of the front layer and the first overlay mark of the current layer by adopting an electron beam scanning mode; based on the second relative position relation, the preliminary overlay error is calibrated to obtain the first overlay error, so that the measurement error obtained by comparing the two measurement methods is beneficial to reducing the deviation of the measurement result caused by the limitation of the measurement machine, thereby being beneficial to improving the precision of the first overlay error.
In some embodiments, only the IDM measurement mode may be adopted to obtain the first relative positional relationship between the first overlay mark of the front layer and the first overlay mark of the current layer, and the overlay error is obtained based on the first relative positional relationship, where the overlay error is the first overlay error, and because the IDM measurement mode has a relatively large throughput, the measurement efficiency can be improved, and the method is favorable for mass production of subsequently formed semiconductor structures.
In some embodiments, before the second relative position is obtained, the obtained preliminary overlay error may be further checked to determine whether the preliminary overlay error obtained by using the IDM technique is within a normal numerical range, so as to determine whether the first overlay mark of the previous layer and the first overlay mark of the current layer have defects, so as to avoid affecting the subsequent measurement result.
It can be appreciated that if the first overlay error value is too large, connection of the corresponding devices manufactured later will be affected, which is not beneficial to improving the yield of semiconductor manufacturing. In some embodiments, the first overlay error may be-5 nm to 5nm, for example, the first overlay error may be-5 nm, -3.2nm, -1.6nm, 1.2nm, 3.5nm or 5nm, where the value of the first overlay error is smaller, so that stable connection between corresponding devices manufactured later can be ensured.
Subsequent steps may also include: and confirming error compensation values of patterns of a front layer mask layer and a current layer mask layer of the next batch according to the obtained first overlay error to improve alignment accuracy between patterns in a front layer and patterns in a current layer (patterns in the current layer are patterns formed in the peripheral region 104 and the cutting channel region 102 synchronously with the first overlay mark of the current layer) correspondingly formed in the peripheral region 104 and the cutting channel region 102, or adjusting relevant parameters of a pattern transferring step of the next batch according to the obtained first overlay error to reduce overlay error values of the peripheral region 104 and the cutting channel region 102 and improve alignment accuracy between patterns in the front layer and patterns in the current layer correspondingly formed in the peripheral region 104 and the cutting channel region 102.
The foregoing step further forms a front layer second overlay mark and a current layer second overlay mark in the array region 103, and in some embodiments, the second overlay error corresponding to the array region 103 may also be obtained based on the relative positional relationship between the front layer second overlay mark and the current layer second overlay mark. The first overlay error and the second overlay error of the current layer are formed by a plurality of second sub-marks 109 arranged in a regular array, which is beneficial to improving the accuracy of the overlay error measured by the first overlay mark and the second overlay mark of the current layer, i.e. improving the accuracy of the second overlay error.
In the method for measuring the overlay mark provided in the above embodiment, the first overlay mark 105 is provided, the first overlay mark 105 includes a plurality of first sub-marks 106 arranged in a regular array, and a plurality of pattern transfer steps are performed, each pattern transfer step transfers the first overlay mark 105 into the peripheral region 104 to form a front layer first overlay mark and a current layer first overlay mark, wherein the front layer first overlay mark is formed in the peripheral region 104 before the current layer first overlay mark, and the front layer first overlay mark and the current layer first overlay mark have the same pattern as the first overlay mark 105, that is, the front layer first overlay mark and the current layer first overlay mark each include a plurality of first sub-marks 106 arranged in a regular array; acquiring a corresponding first overlay error of the peripheral region 104 based on the relative position relationship between the front layer first overlay mark and the current layer first overlay mark, wherein the front layer first overlay mark and the current layer first overlay mark with a plurality of first sub-marks 106 arranged in a regular array are beneficial to improving the accuracy of the measured first overlay mark 105 in the peripheral region 104;
in addition, a front layer first overlay mark and a current layer first overlay mark can be formed in the scribe line region 102, and based on the formation of the front layer first overlay mark and the current layer first overlay mark in the scribe line region 102, a first overlay error of the scribe line region 102 is obtained, the front layer first overlay mark and the current layer first overlay mark each include a plurality of first sub-marks 106 arranged in a regular array, which is favorable for improving the first overlay error accuracy of the scribe line region 102, and a front layer second overlay mark and a current layer second overlay mark can also be formed in the array region 103, and the front layer second overlay mark and the current layer second overlay mark each include a plurality of second sub-marks 109 arranged in a regular array, and based on the relative positional relationship of the front layer second overlay mark and the current layer second overlay mark, a corresponding second overlay error of the array region 103 is obtained, which is favorable for improving the second overlay error accuracy of the array region 103. In this way, the embodiment of the present disclosure can integrally improve the alignment accuracy of the front layer pattern and the current layer pattern in the substrate 100, thereby being beneficial to improving the yield and performance of the correspondingly manufactured semiconductor structure.
Correspondingly, another embodiment of the present disclosure further provides an overlay mark for measuring an overlay error, and the overlay mark provided in another embodiment of the present disclosure may be applied to the overlay error measuring method provided in the foregoing embodiment. The overlay mark provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be described in detail below.
Fig. 4 is a second schematic top view of a first overlay mark provided by an embodiment of the present disclosure, fig. 5 is a first schematic top view of a first sub-mark provided by an embodiment of the present disclosure, fig. 6 is a third schematic top view of a first overlay mark provided by an embodiment of the present disclosure, fig. 7 is a second schematic top view of a first sub-mark provided by an embodiment of the present disclosure, fig. 8 is a fourth schematic top view of a first overlay mark provided by an embodiment of the present disclosure, fig. 9 is a third schematic top view of a first sub-mark provided by an embodiment of the present disclosure, fig. 10 is a fifth schematic top view of a first overlay mark provided by an embodiment of the present disclosure, fig. 11 is a first schematic top view of a second overlay mark provided by an embodiment of the present disclosure, fig. 12 is a second schematic top view of a second overlay mark provided by an embodiment of the present disclosure, wherein the first overlay mark shown in fig. 6 is formed by an array of a plurality of first sub-marks shown in fig. 5, the first overlay mark shown in fig. 8 is formed by an array of a plurality of first sub-marks shown in fig. 7 is formed by an array of a plurality of first alignment marks shown in fig. 9.
Referring to fig. 2, an overlay mark is applied to a substrate 100 including a plurality of chip regions 101 and scribe line regions 102 between adjacent chip regions 101, each chip region 101 includes an array region 103 and a peripheral region 104 located at the periphery of the array region 103, the overlay mark may include a first overlay mark 105, the first overlay mark 105 corresponds to the peripheral region 104, and the first overlay mark 105 includes a plurality of first sub-marks 106 arranged in a regular array. In fig. 2, a large dashed box illustrates a chip area 101, a small dashed box illustrates an array area 103, and a region where the large dashed box does not overlap with the small dashed box illustrates a peripheral area 104.
The first overlay mark 105 is used for forming a front layer first overlay mark and a current layer first overlay mark in the array region through a pattern transferring step, and the front layer first overlay mark is formed in the peripheral region 104 before the current layer first overlay mark, so that the formed front layer first overlay mark and the current layer first overlay mark have the same pattern as the first overlay mark 105, that is, the front layer first overlay mark and the current layer first overlay mark are both composed of a plurality of first sub-marks 106 arranged in a regular array, and the first sub-marks 106 arranged in the regular array are beneficial to improving the precision of the corresponding measured overlay error, that is, the precision of the overlay error measured based on the relative position relation of the front layer first overlay mark and the current layer first overlay mark is higher.
The pattern of the first overlay mark 105 may be regular, and the pattern of the first overlay mark 105 may be a polygon such as a rectangle, triangle, etc. The side length of each side of the first overlay mark 105 may be less than 150um, for example, the side length may be 145um, 138um, 134um, 121um or 113um, so as to match the size of the peripheral region, and avoid that the first overlay mark 105 affects the normal manufacturing of the pattern of the corresponding semiconductor structure of the peripheral region.
The first sub-mark 106 may be regular, and the first sub-mark 106 having a regular shape is beneficial to improving the accuracy of the overlay error measured by the first overlay mark 105. In some embodiments, the first sub-mark 106 may be rectangular in shape, which may have an area of 20um 2 ~30um 2 For example, the area of the rectangle may be 20um 2 、22um 2 、24um 2 、27um 2 Or 30um 2 . In some embodiments, the pattern of the first sub-marks 106 may also be a regular pattern of triangles, hexagons, and the like.
The first sub-mark 106 may include a plurality of patterns of different sizes and different shapes, or the first sub-mark 106 may be formed of patterns of the same size and shape, and the patterns in the first sub-mark 106 may be configured to match the patterns of the corresponding structures in the peripheral region 104 that are subsequently used to form the device.
In some embodiments, the first sub-mark 106 may include a plurality of first stripe patterns 110 arranged at intervals along the first direction X and the second direction Y, wherein the plurality of first stripe patterns arranged at intervals along the first direction X and the second direction Y intersect at a center of the first sub-mark 106, the first stripe patterns 110 arranged along the first direction X may be used to measure an overlay error in the first direction X, and the first stripe patterns 110 arranged along the second direction Y may be used to measure an overlay error in the second direction Y. That is, one of the plurality of first stripe patterns spaced apart along the first direction X and one of the plurality of first stripe patterns spaced apart along the second direction Y may have an overlapping portion at the center of the first sub-mark 106. Alternatively, referring to fig. 5 and 6, two rows of first stripe patterns are arranged at intervals along the first direction X and the second direction Y, respectively, and the extending directions of the two rows of first stripe patterns intersect at the center of the first sub-mark. The first direction X and the second direction Y may be perpendicular to each other, or the first direction X and the second direction Y may not be perpendicular to each other.
Referring to fig. 7 and 8, in some embodiments, the first sub-mark 106 may include a plurality of first stripe patterns 110, where the plurality of first stripe patterns 110 includes at least a first stripe pattern 110 located in a central area of the first sub-mark 106 and a first stripe pattern 110 located in an edge area of the first sub-mark 106, so that overlay error measured by the first stripe pattern 110 located in the central area and the edge area of the first sub-mark 106 can be comprehensively considered, which is beneficial to improving accuracy of overlay error measured by the first overlay mark 105 formed by the first sub-mark 106.
Referring to fig. 9 and 10, in some embodiments, the first sub-mark may include a plurality of second stripe patterns 111 and a plurality of third stripe patterns 112, a portion of the second stripe patterns 111 may be arranged along the first direction X in a central region of the first sub-mark 106, another portion of the second stripe patterns 111 may be located at edge regions of opposite sides of the central region along the second direction Y, the plurality of third stripe patterns 112 may be located at edge regions of opposite sides of the central region along the first direction X, wherein the second stripe patterns 111 of the central region and the third stripe patterns 112 of the edge regions each extend along the second direction, the second stripe patterns 111 of the edge regions and the third stripe patterns 112 have different sizes, for example, a length of a short side of the second stripe patterns 111 may be smaller than a length of a long side of the third stripe patterns 112, and the length of a long side of the second stripe patterns 111 may be smaller than a length of a long side of the third stripe patterns 112, and the first direction X and the second direction Y may be perpendicular to each other. In this way, by adjusting the sizes of the second stripe pattern 111 and the third stripe pattern 112 in the first sub-mark 106, the second stripe pattern 111 and the third stripe pattern 112 are further arranged to have different arrangement directions and be located in different areas, which is beneficial to improving the accuracy of the overlay error measured by the first overlay mark 105 formed by the first sub-mark 106.
It is understood that during the process of transferring the first overlay mark 105 to the substrate 100 through the pattern transferring step, collapse or the like may occur in the first overlay mark 105 transferred to the substrate 100. Referring to fig. 4, in some embodiments, the periphery of the first sub-mark 106 may further be provided with a first protection layer 108 surrounding the first sub-mark 106, where the first protection layer 108 makes a distance between adjacent first sub-marks 106, prevents the adjacent first sub-marks 106 from affecting each other in the pattern transferring step, resulting in a collapse of a portion of the first sub-marks 106, and can avoid the collapsed first sub-marks 106 from affecting the formation of the adjacent first sub-marks 106, which is beneficial to ensuring the accuracy of the overlay error measured by the first overlay mark 105 formed by the first sub-marks 106.
Referring to fig. 2, in some embodiments, at least one first overlay mark 105 further corresponds to the scribe line region 102, so as to manufacture a front layer first overlay mark and a current layer first overlay mark in the scribe line region 102 by the first overlay mark 105 corresponding to the scribe line region 102, where the front layer first overlay mark is formed in the scribe line region 102 before the current layer first overlay mark, and obtain an overlay error of the scribe line region based on the front layer first overlay mark and the current layer first overlay mark, which is advantageous for improving the overall overlay error accuracy of the substrate, thereby being advantageous for improving the yield and performance of the correspondingly manufactured semiconductor structure.
Referring to fig. 2 and 11, in some embodiments, the overlay mark further includes a second overlay mark 107, where the second overlay mark 107 corresponds to the array region 103 and includes a plurality of second sub-marks 109 arranged in a regular array, where the second overlay mark 107 is used to form a front layer second overlay mark and a current layer second overlay mark in the array region through a pattern transferring step, and the front layer second overlay mark is formed in the array region 103 before the current layer second overlay mark, so that the formed front layer second overlay mark and the current layer second overlay mark have the same pattern as the second overlay mark 107, that is, the front layer second overlay mark and the current layer second overlay mark are each formed by a plurality of second sub-marks 109 arranged in a regular array, where the second sub-marks 109 arranged in a regular array are beneficial to improving the accuracy of the overlay error measured correspondingly, that is, the overlay error accuracy measured based on the relative position relationship between the front layer second overlay mark and the current layer second overlay mark is higher.
The second sub-mark 109 may be a regular-shaped pattern, and the first sub-mark 106 with a regular shape is beneficial to improving the accuracy of the overlay error measured by the first overlay mark 105. For example, the pattern of the second sub-marks 109 may be rectangular, triangular, hexagonal, or the like.
In some embodiments, the second sub-mark 109 may have the same pattern and size as the first sub-mark 106, which may be advantageous in reducing the process complexity of manufacturing the mask layer having the first and second overlay marks 105, 107. For example, the second sub-mark 109 may include a first stripe pattern, and the plurality of first stripe patterns includes at least a first stripe pattern located in a central region of the first sub-mark 106 and a first stripe pattern located in an edge region of the second sub-mark 109.
Referring to fig. 12, in some embodiments, the second sub-marks 109 may be provided with a second protection layer 113 surrounding the second sub-marks 109, where the second protection layer 113 makes a distance between adjacent second sub-marks 109, avoids the adjacent second sub-marks 109 from affecting each other in the pattern transferring step, resulting in a collapse of a portion of the second sub-marks 109, and can avoid a situation that the collapsed second sub-marks 109 affect the formation of the adjacent second sub-marks 109, which is beneficial to ensure the accuracy of the overlay error measured by the second overlay mark 107 made of the second sub-marks 109.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed as that of the appended claims.
Claims (12)
1. The method for measuring the overlay error is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a plurality of chip areas and cutting channel areas positioned between adjacent chip areas, and each chip area comprises an array area and a peripheral area positioned at the periphery of the array area;
providing a first overlay mark, wherein the first overlay mark corresponds to the peripheral area, and comprises a plurality of first sub-marks which are regularly arranged in an array;
performing a plurality of pattern transfer steps, wherein each pattern transfer step transfers the first overlay mark into the peripheral area to form a front layer first overlay mark and a current layer first overlay mark in the peripheral area;
and acquiring a first overlay error based on the relative position relation between the first overlay mark of the front layer and the first overlay mark of the current layer.
2. The overlay error measurement method of claim 1, wherein the performing the pattern transfer step multiple times comprises:
forming a front-layer mask layer on the substrate, wherein the front-layer mask layer is provided with the first overlay mark;
performing a first etching process on the substrate by taking the front layer mask layer as a mask so as to form a front layer first overlay mark in the peripheral region;
removing the front mask layer;
forming a current layer mask layer on the substrate, wherein the current layer mask layer is provided with the first overlay mark;
taking the current layer mask layer as a mask, and performing a second etching process on the substrate to form a first overlay mark of the current layer in the peripheral region;
and removing the mask layer of the current layer.
3. The overlay error measurement method of claim 2, further comprising:
and acquiring a post-development overlay error corresponding to the peripheral region based on the first overlay mark of the front layer and the first overlay mark in the current layer mask layer.
4. The method for measuring overlay error according to claim 1, wherein in the step of providing the first overlay mark, a second overlay mark is further provided, and the second overlay mark includes a plurality of second sub-marks arranged in a regular array, and the second overlay mark corresponds to the array region;
the step of performing multiple pattern transfer includes: transferring the second overlay mark to the array region in each pattern transferring step to form a front layer second overlay mark and a current layer second overlay mark in the array region;
and acquiring a second overlay error corresponding to the array region based on the relative position relation between the front layer second overlay mark and the current layer second overlay mark.
5. The method according to claim 1, wherein in the step of providing the first overlay mark, at least one of the first overlay marks corresponds to the scribe line region;
the step of performing multiple pattern transfer includes: and transferring the first overlay mark into the cutting channel region in each pattern transferring step so as to form the front layer first overlay mark and the current layer first overlay mark in the cutting channel region.
6. The method for measuring overlay error according to any one of claims 1 to 5, wherein the method for obtaining the first overlay error comprises:
obtaining a first relative position relation between the first overlay mark of the front layer and the first overlay mark of the current layer by adopting an IDM measurement mode;
acquiring a preliminary overlay error based on the first relative position relationship;
acquiring a second relative position relationship based on the first overlay mark of the front layer and the first overlay mark of the current layer by adopting an electron beam scanning mode;
and calibrating the preliminary overlay error based on the second relative position relationship to obtain the first overlay error.
7. An overlay mark for overlay error measurement, which is characterized by being applied to a substrate comprising a plurality of chip areas and cutting channel areas positioned between adjacent chip areas, wherein each chip area comprises an array area and a peripheral area positioned at the periphery of the array area; the overlay mark includes:
the first overlay mark corresponds to the peripheral area, and comprises a plurality of first sub-marks which are arranged in a regular array.
8. The overlay mark of claim 7, further comprising: and the second overlay mark corresponds to the array region and comprises a plurality of second sub-marks which are regularly arranged in an array.
9. The overlay mark of claim 7, wherein at least one of the first overlay marks further corresponds to the scribe line region.
10. The overlay mark of any one of claims 7-9, wherein the first sub-mark comprises a plurality of first stripe patterns spaced apart along a first direction and a second direction, wherein the plurality of first stripe patterns spaced apart along the first direction and the second direction intersect at a center of the first sub-mark.
11. The overlay mark of any one of claims 7-9, wherein the first sub-mark comprises a plurality of first stripe patterns, the plurality of first stripe patterns comprising at least a first stripe pattern located in a central region of the first sub-mark, the first stripe pattern located in an edge region of the first sub-mark.
12. The overlay mark of any one of claims 7-9, wherein the first sub-mark comprises a plurality of second stripe patterns and a plurality of third stripe patterns, a portion of the second stripe patterns are arranged along a first direction in a center region of the first sub-mark, another portion of the second stripe patterns are located in edge regions on opposite sides of the center region along a second direction, the plurality of third stripe patterns are located in edge regions on opposite sides of the center region along the first direction, wherein the second stripe patterns of the center region and the third stripe patterns of the edge regions each extend along the second direction, the second stripe patterns of the edge regions and the third stripe patterns have different sizes, and the first direction and the second direction are mutually perpendicular.
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