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CN116206642A - Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell - Google Patents

Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell Download PDF

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Publication number
CN116206642A
CN116206642A CN202211374124.7A CN202211374124A CN116206642A CN 116206642 A CN116206642 A CN 116206642A CN 202211374124 A CN202211374124 A CN 202211374124A CN 116206642 A CN116206642 A CN 116206642A
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China
Prior art keywords
transistor
pole
sense amplifier
input
output
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CN202211374124.7A
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Chinese (zh)
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CN116206642B (en
Inventor
朱正勇
康卜文
刘铭旭
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The application discloses a semiconductor memory device, including: the first bit line and the second bit line are respectively arranged to be connected with the corresponding memory cells; a first sense amplifier; the first sense amplifier is configured to amplify input data; the device comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the second output end, and the second input end is connected with the first output end; a first input control transistor and a second input control transistor configured to control signals on corresponding bit lines to be input or not input to corresponding input terminals of the first sense amplifier, respectively; the first output control transistor and the second output control transistor are configured to control signals at the output ends of the sense amplifier to be output to the corresponding bit lines or not, respectively.

Description

Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor memory device.
Background
An amplifier circuit for amplifying input data is used in various fields including a communication field, a semiconductor field, and the like. For example, a semiconductor memory device of a DRAM amplifies memory cell data using a bit line sense amplifier. Specifically, if a word line is activated, data of a plurality of memory cells connected to the word line is transferred to a bit line, and a bit line sense amplifier senses and amplifies a voltage difference between two bit lines included in a bit line pair.
In the 1T1C technology, as shown in fig. 1, data access is performed through a sense amplifier SA (cross-coupled inverter). The data stored in the capacitance of the memory cell is the same as the signal generated in the sense amplifier, so that the I/O data can be connected to the input and output terminals in the sense amplifier through the switching transistors controlled by the column select lines. Also, the input data for the write operation does not require a full swing signal, as the sense amplifier can help generate and amplify a partial swing signal, which will help to improve write speed and save consumption.
In the 2T0C technology, since the data stored in SN (as shown in fig. 2) is opposite to the signal generated in the bit line BL (e.g., BL will be low because the read transistor is on for high levels), this presents many access problems. For example, BL cannot be connected to the output of SA (unlike in 1T 1C). Furthermore, this reduces the write speed and also causes power consumption problems, since full swing data is typically required for the write operation.
Disclosure of Invention
The application provides a semiconductor memory device capable of amplifying memory data of a 2T0C memory cell.
The present application provides a semiconductor memory device including:
A first bit line connected to a first memory cell;
a second bit line connected to the second memory cell;
a first sense amplifier arranged to amplify a differential input signal when the differential input signal is sensed; the device comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the second output end, and the second input end is connected with the first output end;
a first input control transistor configured to control signal input or non-input on a first bit line to a first input terminal of the first sense amplifier;
a second input control transistor configured to control signal input or non-input on a second bit line to a second input terminal of the first sense amplifier;
a first output control transistor configured to control a signal of a first output terminal of the first sense amplifier to be output to or not output from the first bit line, respectively;
a second output control transistor configured to control signal output or non-output of the second output terminal of the first sense amplifier to the second bit line;
the first memory cell and the second memory cell are 2T0C memory cells.
In an exemplary embodiment, a first pole of the first input control transistor is connected to a first bit line, and a second pole of the first input control transistor is connected to a first input terminal of the first sense amplifier; a first pole of the first output control transistor is connected with the first bit line, and a second pole of the first output control transistor is connected with a first output end of the first sense amplifier; the grid electrode of the first input control transistor is connected with the first input control end; the grid electrode of the first output control transistor is connected with the first output control end;
a first pole of the second input control transistor is connected with a second bit line, and a second pole of the second input control transistor is connected with a second input end of the first sense amplifier; a first end of the second output control transistor is connected with the second bit line, and a second pole of the second output control transistor is connected with a second output end of the first sense amplifier; the grid electrode of the second input control transistor is connected with the second input control end; and the grid electrode of the second output control transistor is connected with the second output control end.
In one exemplary embodiment, the first sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first ground control transistor;
the second pole of the first PMOS transistor is connected with the first pole of the first NMOS transistor; the second pole of the second PMOS transistor is connected with the first pole of the second NMOS transistor; the grid electrode of the first PMOS transistor is connected with the second pole of the second PMOS transistor, and the grid electrode of the second PMOS transistor is connected with the second pole of the first PMOS transistor; the first poles of the first PMOS transistor and the second PMOS transistor are connected and then connected to VDD; the second poles of the first NMOS transistor and the second NMOS transistor are connected and grounded through a first grounding control transistor;
a gate of the first NMOS transistor serves as a first input terminal of the first sense amplifier; a gate of a second NMOS transistor serves as a second input terminal of the first sense amplifier; a second pole of the first PMOS transistor serves as a first output terminal of the first sense amplifier; the second pole of the second PMOS transistor serves as the second output terminal of the first sense amplifier.
In one exemplary embodiment, the first sense amplifier includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a second ground control transistor;
The third PMOS transistor, the third NMOS transistor and the fourth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the third PMOS transistor and the third NMOS transistor are connected;
the fourth PMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the fourth PMOS transistor and the fifth NMOS transistor are connected;
the first poles of the third PMOS transistor and the fourth PMOS transistor are connected and then connected to VDD; the second poles of the fourth NMOS transistor and the sixth NMOS transistor are connected and grounded through a second grounding control transistor;
a grid electrode of the fourth NMOS transistor is used as a first input end of the first sense amplifier, and a grid electrode of the sixth NMOS transistor is used as a second input end of the first sense amplifier; the second pole of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor to be used as a first output end of the first sense amplifier; the second pole of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor to serve as a second output end of the first sense amplifier.
In an exemplary embodiment, the memory device further includes a first column selection unit corresponding to each memory cell; each first column selection unit includes a first column selection transistor; a first pole of each first column select transistor is connected to a corresponding I/O terminal; the second pole of each first column selection transistor is connected with the corresponding output end of the first sense amplifier; the gate of each first column select transistor is connected to a corresponding column select line.
In an exemplary embodiment, the method further includes a first restarting unit and a first pre-charging unit corresponding to the first storage unit, and a second restarting unit and a second pre-charging unit corresponding to the second storage unit;
each restart unit includes a restart transistor; the first poles of the restarting transistors are respectively connected with the bit lines corresponding to the corresponding memory cells; the second pole of each restarting transistor is connected with a corresponding maintaining power supply; the grid electrode of each restarting transistor is connected with a corresponding restarting signal end;
each of the precharge units includes a precharge transistor; the first pole of the pre-charge transistor is connected with the bit line corresponding to the corresponding memory cell; the second pole of the pre-charge transistor is connected with a corresponding pre-charge source; the grid electrode of the pre-charging transistor is connected with the corresponding pre-charging signal terminal.
The present application provides a semiconductor memory device including:
a first read bit line and a first write bit line, the first read bit line configured to be connected to a read transistor connected to a third memory cell; the first write bit line is arranged to be connected to a write transistor of a third memory cell;
a second read bit line and a second write bit line, the second read bit line configured to be connected to a read transistor connected to a fourth memory cell; the second write bit line is arranged to be connected to a write transistor of a fourth memory cell;
A second sense amplifier; the second sense amplifier is arranged to amplify the differential input signal when the differential input signal is sensed; the device comprises a third input end, a fourth input end, a third output end and a fourth output end, wherein the third input end is connected with the fourth output end, and the fourth input end is connected with the third output end;
the third input end is connected with the first read bit line, the third output end is connected with the first write bit line, the fourth input end is connected with the second read bit line, and the fourth output end is connected with the second write bit line;
a third input control transistor configured to control signal input or non-input on the first read bit line to a third input terminal of the second sense amplifier;
a third output control transistor configured to control signal output or non-output of the third output terminal of the second sense amplifier to the first write bit line;
a fourth input control transistor configured to control signal input or non-input on the second read bit line to a fourth input terminal of the second sense amplifier;
a fourth output control transistor configured to control signal output or non-output of the fourth output terminal of the second sense amplifier to the second write bit line;
The third memory cell and the fourth memory cell are 2T0C memory cells.
In an exemplary embodiment, a first pole of the third input control transistor is connected to the first read bit line; a second pole of the third input control transistor is connected with a third input end of the second sense amplifier; the grid electrode of the third input control transistor is connected with the third input control end;
a first pole of the third output control transistor is connected to the first write bit line; a second pole of the third output control transistor is connected with a third output end of the second sense amplifier; the grid electrode of the third output control transistor is connected with a third output control end;
a first pole of the fourth input control transistor is connected with a fourth input end of the second sense amplifier; a second pole of the fourth input control transistor is connected with the second read bit line; the grid electrode of the fourth input control transistor is connected with the fourth input control end;
a first pole of the fourth output control transistor is connected with a fourth output end of the second sense amplifier; a second pole of the fourth output control transistor is connected with the second write bit line; and the grid electrode of the fourth output control transistor is connected with the fourth output control end.
In an exemplary embodiment, the second sense amplifier further includes a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a third ground control transistor;
the second pole of the seventh PMOS transistor is connected to the first pole of the seventh NMOS transistor; the second pole of the eighth PMOS transistor is connected to the first pole of the eighth NMOS transistor; a grid electrode of the seventh PMOS transistor is connected with a second electrode of the eighth PMOS transistor, and a grid electrode of the eighth PMOS transistor is connected with the second electrode of the seventh PMOS transistor; the first poles of the seventh PMOS transistor and the eighth PMOS transistor are connected and then connected to VDD; the second poles of the seventh NMOS transistor and the eighth NMOS transistor are connected and grounded through a first grounding control transistor;
a gate of a seventh NMOS transistor serves as a third input terminal of the second sense amplifier; a gate of the eighth NMOS transistor serves as a fourth input terminal of the second sense amplifier; a second pole of a seventh PMOS transistor serves as a third output terminal of the second sense amplifier; the second pole of the eighth PMOS transistor serves as the fourth output of the second sense amplifier.
In an exemplary embodiment, the second sense amplifier further includes a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a fourth ground control transistor;
The ninth PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the ninth PMOS transistor and the ninth NMOS transistor are connected;
the tenth PMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the tenth PMOS transistor and the eleventh NMOS transistor are connected;
the first poles of the ninth PMOS transistor and the tenth PMOS transistor are connected and then connected to the VDD; the tenth NMOS transistor and the twelfth NMOS transistor are connected through a fourth grounding control transistor to the ground after the second poles of the tenth NMOS transistor and the twelfth NMOS transistor are connected;
a gate of the tenth NMOS transistor is used as a third input terminal of the second sense amplifier, and a gate of the twelfth NMOS transistor is used as a fourth input terminal of the second sense amplifier; a second pole of the ninth PMOS transistor is connected with a grid electrode of the tenth PMOS transistor to be used as a third output end of the second sense amplifier; a second pole of the tenth PMOS transistor is connected to a gate of the ninth PMOS transistor as a fourth output terminal of the second sense amplifier.
In an exemplary embodiment, a second column selection unit corresponding to each memory cell is further included; each second column selection unit includes a column selection transistor; a first pole of each column select transistor is connected to a corresponding I/O terminal; a second pole of each column selection transistor is connected with a corresponding output end of the second sense amplifier; the gate of each column select transistor is connected to a corresponding column select line.
In one exemplary embodiment, the method further includes a third restart unit and a third precharge unit corresponding to the first read bit line, a fourth restart unit and a fourth precharge unit corresponding to the first write bit line, a fifth restart unit and a fifth precharge unit corresponding to the second read bit line, and a sixth restart unit and a sixth precharge unit corresponding to the second write bit line;
each restart unit includes a restart transistor; the first poles of the restarting transistors are respectively connected with the corresponding read bit lines of the corresponding memory cells; the second pole of the restarting transistor is connected with a corresponding maintenance power supply; the grid electrode of the restarting transistor is connected with the corresponding restarting signal end;
each precharge unit includes a precharge transistor; the first pole of the pre-charge transistor is connected with the read bit line corresponding to the corresponding memory cell; the second pole of the pre-charge transistor is connected with a corresponding pre-charge source; the grid electrode of the pre-charging transistor is connected with the corresponding pre-charging signal terminal.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a schematic diagram of a prior art sense amplifier;
FIG. 2 is a schematic diagram of a 2T0C memory cell according to an embodiment of the present application;
fig. 3 is a schematic diagram of a semiconductor memory device according to an embodiment of the present application;
fig. 4 is a schematic diagram of another semiconductor memory device according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a circuit for accessing a memory cell according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an SA according to embodiments of the present application;
FIG. 7 is a schematic diagram of another SA according to embodiments of the present application;
FIG. 8 is a timing waveform diagram corresponding to the circuit of FIG. 5 according to an embodiment of the present application;
FIG. 9 is a timing waveform diagram corresponding to the circuit of FIG. 5 according to an embodiment of the present application;
FIG. 10 is a timing waveform diagram corresponding to the circuit of FIG. 5 according to an embodiment of the present application;
FIG. 11 is a schematic circuit diagram of another embodiment of an access memory cell.
Detailed Description
Fig. 3 is a schematic diagram of a semiconductor memory device according to an embodiment of the present application, and as shown in fig. 3, a semiconductor memory device includes:
A first bit line and a second bit line, the first bit line being connected to a first memory cell; the second bit line is connected with the second storage unit;
a first sense amplifier; the first sense amplifier is configured to amplify input data; the device comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the second output end, and the second input end is connected with the first output end;
a first input control transistor configured to control signal input or non-input on a first bit line to a first input terminal of the first sense amplifier;
a second input control transistor configured to control signal input or non-input on a second bit line to a second input terminal of the first sense amplifier;
a first output control transistor configured to control a signal of a first output terminal of the first sense amplifier to be output to or not output from the first bit line, respectively;
a second output control transistor configured to control signal output or non-output of the second output terminal of the first sense amplifier to the second bit line;
the first memory cell and the second memory cell are 2T0C memory cells.
The first input control transistor and the first output control transistor may be turned on or off as required, or may be turned off at the same time as required. And when the first sense amplifier is turned off, the connection between the first sense amplifier and the first memory cell is disconnected. The second input control transistor and the second output control transistor may be turned on or off as needed, or may be turned off at the same time as needed. And when the first sense amplifier is turned off, the connection between the first sense amplifier and the second memory cell is disconnected. After disconnecting the first sense amplifier from the memory cells on one side, the first sense amplifier may still amplify the signal of the memory cells on the other side.
In an exemplary embodiment, a first pole of the first input control transistor is connected to a first bit line, and a second pole of the first input control transistor is connected to a first input terminal of the first sense amplifier; a first pole of the first output control transistor is connected with the first bit line, and a second pole of the first output control transistor is connected with a first output end of the first sense amplifier; the grid electrode of the first input control transistor is connected with the first input control end; the grid electrode of the first output control transistor is connected with the first output control end;
a first pole of the second input control transistor is connected with a second bit line, and a second pole of the second input control transistor is connected with a second input end of the first sense amplifier; a first end of the second output control transistor is connected with the second bit line, and a second pole of the second output control transistor is connected with a second output end of the first sense amplifier; the grid electrode of the second input control transistor is connected with the second input control end; and the grid electrode of the second output control transistor is connected with the second output control end.
In one exemplary embodiment, the first sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first ground control transistor;
the second pole of the first PMOS transistor is connected with the first pole of the first NMOS transistor; the second pole of the second PMOS transistor is connected with the first pole of the second NMOS transistor; the grid electrode of the first PMOS transistor is connected with the second pole of the second PMOS transistor, and the grid electrode of the second PMOS transistor is connected with the second pole of the first PMOS transistor; the first poles of the first PMOS transistor and the second PMOS transistor are connected and then connected to VDD; the second poles of the first NMOS transistor and the second NMOS transistor are connected and grounded through a first grounding control transistor;
a gate of the first NMOS transistor serves as a first input terminal of the first sense amplifier; a gate of a second NMOS transistor serves as a second input terminal of the first sense amplifier; a second pole of the first PMOS transistor serves as a first output terminal of the first sense amplifier; the second pole of the second PMOS transistor serves as the second output terminal of the first sense amplifier.
In one exemplary embodiment, the first sense amplifier includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a second ground control transistor;
The third PMOS transistor, the third NMOS transistor and the fourth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the third PMOS transistor and the third NMOS transistor are connected;
the fourth PMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the fourth PMOS transistor and the fifth NMOS transistor are connected;
the first poles of the third PMOS transistor and the fourth PMOS transistor are connected and then connected to VDD; the second poles of the fourth NMOS transistor and the sixth NMOS transistor are connected and grounded through a second grounding control transistor;
a grid electrode of the fourth NMOS transistor is used as a first input end of the first sense amplifier, and a grid electrode of the sixth NMOS transistor is used as a second input end of the first sense amplifier; the second pole of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor to be used as a first output end of the first sense amplifier; the second pole of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor to serve as a second output end of the first sense amplifier.
In one exemplary embodiment, the semiconductor memory device further includes a first column selection unit corresponding to each memory cell; each first column selection unit includes a first column selection transistor; a first pole of each first column select transistor is connected to a corresponding I/O terminal; the second pole of each first column selection transistor is connected with the corresponding output end of the first sense amplifier; the gate of each first column select transistor is connected to a corresponding column select line.
In an exemplary embodiment, the method further includes a first restarting unit and a first pre-charging unit corresponding to the first storage unit, and a second restarting unit and a second pre-charging unit corresponding to the second storage unit;
each restart unit includes a restart transistor; the first poles of the restarting transistors are respectively connected with the bit lines corresponding to the corresponding memory cells; the second pole of each restarting transistor is connected with a corresponding maintaining power supply; the grid electrode of each restarting transistor is connected with a corresponding restarting signal end;
each of the precharge units includes a precharge transistor; the first pole of the pre-charge transistor is connected with the bit line corresponding to the corresponding memory unit; the second pole of the pre-charge transistor is connected with a corresponding pre-charge source; the grid electrode of the pre-charging transistor is connected with the corresponding pre-charging signal terminal.
According to the embodiment of the application, the control transistor is added between the bit line and the SA, when the bit line signal is large enough, the input control transistor is turned off, and the output control transistor on the same side is turned on, so that the output signal of the SA reaches the bit line to realize refresh operation. When the input control transistor on one side is turned on, since the input terminal on one side of the SA is connected to the output terminal on the other side, the output on the other side helps to hold the input signal so that a stable output is provided for read and refresh operations. Also, the SA is capable of amplifying the data signal, so the full swing signal is not required for writing data.
Fig. 4 is a schematic diagram of a semiconductor memory device according to an embodiment of the present application, and as shown in fig. 4, a semiconductor memory device includes:
a first read bit line and a first write bit line, the first read bit line configured to be connected to a read transistor connected to a third memory cell; the first write bit line is arranged to be connected to a write transistor of a third memory cell;
a second read bit line and a second write bit line, the second read bit line configured to be connected to a read transistor connected to a fourth memory cell; the second write bit line is arranged to be connected to a write transistor of a fourth memory cell;
a second sense amplifier arranged to amplify a differential input signal when the differential input signal is sensed; the device comprises a third input end, a fourth input end, a third output end and a fourth output end, wherein the third input end is connected with the fourth output end, and the fourth input end is connected with the third output end;
the third input end is connected with the first read bit line, the third output end is connected with the first write bit line, the fourth input end is connected with the second read bit line, and the fourth output end is connected with the second write bit line;
A third input control transistor configured to control signal input or non-input on the first read bit line to a third input terminal of the second sense amplifier;
a third output control transistor configured to control signal output or non-output of the third output terminal of the second sense amplifier to the first write bit line;
a fourth input control transistor configured to control signal input or non-input on the second read bit line to a fourth input terminal of the second sense amplifier;
a fourth output control transistor configured to control signal output or non-output of the fourth output terminal of the second sense amplifier to the second write bit line;
the third memory cell and the fourth memory cell are 2T0C memory cells.
The third input control transistor and the third output control transistor may be turned on or off as needed, or may be turned off at the same time as needed. And when the second sense amplifier is turned off, the connection between the second sense amplifier and the third memory cell is disconnected. The fourth input control transistor and the fourth output control transistor may be turned on or off as needed, or may be turned off at the same time as needed. And when the second sense amplifier is turned off, the connection between the second sense amplifier and the fourth memory cell is disconnected. After disconnecting the second sense amplifier from the memory cell on one side, the second sense amplifier may still amplify the signal of the memory cell on the other side.
In an exemplary embodiment, a first pole of the third input control transistor is connected to the first read bit line; a second pole of the third input control transistor is connected with a third input end of the second sense amplifier; the grid electrode of the third input control transistor is connected with the third input control end;
a first pole of the third output control transistor is connected to the first write bit line; a second pole of the third output control transistor is connected with a third output end of the second sense amplifier; the grid electrode of the third output control transistor is connected with a third output control end;
a first pole of the fourth input control transistor is connected with a fourth input end of the second sense amplifier; a second pole of the fourth input control transistor is connected with the second read bit line; the grid electrode of the fourth input control transistor is connected with the fourth input control end;
a first pole of the fourth output control transistor is connected with a fourth output end of the second sense amplifier; a second pole of the fourth output control transistor is connected with the second write bit line; and the grid electrode of the fourth output control transistor is connected with the fourth output control end.
In an exemplary embodiment, the second sense amplifier further includes a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a third ground control transistor;
the second pole of the seventh PMOS transistor is connected to the first pole of the seventh NMOS transistor; the second pole of the eighth PMOS transistor is connected to the first pole of the eighth NMOS transistor; a grid electrode of the seventh PMOS transistor is connected with a second electrode of the eighth PMOS transistor, and a grid electrode of the eighth PMOS transistor is connected with the second electrode of the seventh PMOS transistor; the first poles of the seventh PMOS transistor and the eighth PMOS transistor are connected and then connected to VDD; the second poles of the seventh NMOS transistor and the eighth NMOS transistor are connected and grounded through a first grounding control transistor;
a gate of a seventh NMOS transistor serves as a third input terminal of the second sense amplifier; a gate of the eighth NMOS transistor serves as a fourth input terminal of the second sense amplifier; a second pole of a seventh PMOS transistor serves as a third output terminal of the second sense amplifier; the second pole of the eighth PMOS transistor serves as the fourth output of the second sense amplifier.
In an exemplary embodiment, the second sense amplifier further includes a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a fourth ground control transistor;
The ninth PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the ninth PMOS transistor and the ninth NMOS transistor are connected;
the tenth PMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the tenth PMOS transistor and the eleventh NMOS transistor are connected;
the first poles of the ninth PMOS transistor and the tenth PMOS transistor are connected and then connected to the VDD; the tenth NMOS transistor and the twelfth NMOS transistor are connected through a fourth grounding control transistor to the ground after the second poles of the tenth NMOS transistor and the twelfth NMOS transistor are connected;
a gate of the tenth NMOS transistor is used as a third input terminal of the second sense amplifier, and a gate of the twelfth NMOS transistor is used as a fourth input terminal of the second sense amplifier; a second pole of the ninth PMOS transistor is connected with a grid electrode of the tenth PMOS transistor to be used as a third output end of the second sense amplifier; a second pole of the tenth PMOS transistor is connected to a gate of the ninth PMOS transistor as a fourth output terminal of the second sense amplifier.
In one exemplary embodiment, the semiconductor memory device further includes a second column selection unit corresponding to each memory cell; each second column selection unit includes a column selection transistor; a first pole of each column select transistor is connected to a corresponding I/O terminal; a second pole of each column selection transistor is connected with a corresponding output end of the second sense amplifier; the gate of each column select transistor is connected to a corresponding column select line.
In one exemplary embodiment, the semiconductor memory device further includes a third restart unit and a third precharge unit corresponding to the first read bit line, a fourth restart unit and a fourth precharge unit corresponding to the first write bit line, a fifth restart unit and a fifth precharge unit corresponding to the second read bit line, and a sixth restart unit and a sixth precharge unit corresponding to the second write bit line;
each restart unit includes a restart transistor; the first poles of the restarting transistors are respectively connected with the corresponding read bit lines of the corresponding memory cells; the second pole of the restarting transistor is connected with a corresponding maintenance power supply; the grid electrode of the restarting transistor is connected with the corresponding restarting signal end;
each precharge unit includes a precharge transistor; the first pole of the pre-charge transistor is connected with the corresponding read bit line of the corresponding memory unit; the second pole of the pre-charge transistor is connected with a corresponding pre-charge source; the grid electrode of the pre-charging transistor is connected with the corresponding pre-charging signal terminal.
In the embodiment of the application, each 2T0C memory cell comprises two bit lines, and the read-write and refresh control of the 2T0C memory cell is realized by connecting the write bit line of each memory cell with the output end of the sense amplifier and connecting the read bit line of each memory cell with the input end of the sense amplifier.
Fig. 5 is a schematic circuit diagram of an access memory cell according to an embodiment of the present application, where fig. 5 includes a sense amplifier SA, two 2T0C memory cells, two input control transistors re_con, two output control transistors Φ_we, two column selection transistors, two column selection lines CSL, two precharge transistors, and two restart transistors. The circuitry of the sense amplifier in fig. 5 is shown, for example, in fig. 6 and 7.
FIG. 8 illustrates a timing diagram for a write operation of the circuit of FIG. 5; the timing diagram of FIG. 8 shows the process of writing a "0" when a "1" is stored in the original first memory cell.
As shown in fig. 8, in the non-operating state (stand-by state, i.e., the maintenance state), the transistors (corresponding to the first input control transistor and the second input control transistor respectively) controlled by the left and right re_con (corresponding to the first input control transistor and the second input control transistor respectively) are in the on state, and the transistors (corresponding to the first output control transistor and the second output control transistor respectively) controlled by the left and right Φ_we (corresponding to the first output control transistor and the second output control transistor respectively) are in the off state. The potential of the RBL (read bit line) on both the left and right sides is maintained at the V1 potential (Reset controlled transistor on, pre_rd controlled transistor off). If a write operation is to be performed next on a cell of the left memory array, the left BL is first precharged to V2 (V2 is higher than V1). Then the transistors controlled by left and right Reset (corresponding to the above described restart signal terminal) and pre_rd (corresponding to the above described precharge signal terminal) are turned off (corresponding to the above described restart transistor and precharge transistor, respectively), and left and right RBL suspensions (floating), whose potentials are V2 and V1, respectively. Next, a read voltage VR is applied to the RWL of the storage single connection to be read (the voltage selection criteria of VR: the threshold voltages of the read transistors are VL and VH in the case of data "1" and data "0", respectively (back gate vs. threshold voltage adjustment effect, VL < VH), then VL < VR < VH, ensuring that the read transistors are turned on and off in the case of data "1" and "0", respectively). As shown in fig. 5, in the case where the initial data is "1", the BL potential is lowered from V2 (because the read transistor is turned on at data "1"). Since re_con remains on during this process, VIN & BLSO varies synchronously with the BL potential on the left side. When the left BL potential drops from V2 to a certain value (lower than V1 and the amplifier can accurately recognize), the sense amplifier may be activated to turn off the left re_con-controlled transistor and the RWL-controlled read transistor, and turn on the left Φ -WE-controlled transistor, and a plurality of memory cells connected to the RWL, and the CSL-controlled transistors corresponding to other cells except the cell where data is to be written remain in an off state, and the corresponding SA output signals (high/low potential, corresponding to stored data "1" and "0" respectively) are directly transferred to the BL through Φ -WE. At the same time, for the cell to which data is to be written, the transistors controlled by the corresponding CSL (corresponding to the column select line described above) are activated, I/O and I/O are activated (I/O and I/O are newly written as "0" as shown in fig. 8, and low and high voltages are respectively applied), the original SA signal (Vin and Vin are respectively low and high) is inverted by the I/O and I/O signals, and further amplified, so that Vin on the left side changes from low to high, blsa_o changes from high to low, and BL potential changes with blsa_o because Φ -WE is turned on. At the same time, the WWL controlled transistor is turned on and the SA output signal is written from BL into the storage node (i.e., SN) of the memory cell.
FIG. 9 illustrates a timing diagram for a read operation of the circuit of FIG. 5; the timing diagram of fig. 9 shows a process of reading data "1" from the memory cell.
As shown in fig. 9, in the non-operation state (stand-by state), the transistors controlled by re_con on the left and right sides are in the on state, and the transistors controlled by Φ -WE on the left and right sides are in the off state. The potential of the RBL on both the left and right sides is maintained at V1 potential (Reset controlled transistor on, pre_rd controlled transistor off). If a read operation is to be performed next on a cell of the left memory array, the left BL is first precharged to V2 (V2 is higher than V1, otherwise in the case of data "0", SA cannot effectively sense the differential input signal). The transistors controlled by left and right Reset and pre_rd are then turned off, left and right RBL suspensions (floating), whose potentials are V2 and V1, respectively. Next, a read voltage VR is applied to the RWL of the storage single connection to be read (the voltage selection criteria of VR: the threshold voltages of the read transistors are VL and VH in the case of data "1" and data "0", respectively (back gate vs. threshold voltage adjustment effect, VL < VH), then VL < VR < VH, ensuring that the read transistors are turned on and off in the case of data "1" and "0", respectively). As shown in fig. 8, in the case where the initial data is "1", the BL electric potential is lowered from V2 (because the read transistor is turned on at data "1"). Since re_con remains on during this process, VIN & BLSO varies synchronously with the BL potential on the left side. When the left BL potential drops from V2 to a certain value (lower than V1 and the amplifier can accurately recognize), the sense amplifier may be activated to turn off the left re_con-controlled transistor and the RWL-controlled read transistor, keep the left Φ -WE-controlled transistor and the right Φ -WE-controlled transistor turned off, connect to the RWL, have multiple memory cells, keep the CSL-controlled transistors corresponding to other cells in an off state except the cell where data needs to be read out, and the corresponding SA output signals (high/low potential, corresponding to stored data "1" and "0" respectively) are directly transferred to the I/O and I/O by the CSL-controlled transistors.
Fig. 10 shows a timing diagram of the refresh operation of the circuit of fig. 5. The timing diagram of fig. 10 shows a process of refreshing data "1" stored in the memory cell.
As shown in fig. 10, in the non-operation state (stand-by state), the transistors controlled by re_con on the left and right sides are in the on state, and the transistors controlled by Φ -WE on the left and right sides are in the off state. The potential of the RBL on both the left and right sides is maintained at V1 potential (Reset controlled transistor on, pre_rd controlled transistor off). If a refresh operation is to be performed next on a row of the memory array on the left, the BL on the left is first precharged to V2 (V2 is higher than V1). The transistors controlled by left and right Reset and pre_rd are then turned off, left and right RBL suspensions (floating), whose potentials are V2 and V1, respectively. Next, a read voltage VR is applied to the RWL of the storage single connection to be read (the voltage selection criteria of VR: the threshold voltages of the read transistors are VL and VH in the case of data "1" and data "0", respectively (back gate vs. threshold voltage adjustment effect, VL < VH), then VL < VR < VH, ensuring that the read transistors are turned on and off in the case of data "1" and "0", respectively). As shown in fig. 5, in the case where the initial data is "1", the BL potential is lowered from V2 (because the read transistor is turned on at data "1"). Since re_con remains on during this process, VIN & BLSO varies synchronously with the BL potential on the left side. When the left BL potential drops from V2 to a certain value (lower than V1 and the amplifier can accurately recognize), the sense amplifier can be started, the left Re_Con controlled transistor and the RWL controlled read transistor are turned off, the left phi-WE controlled transistor is turned on, the CSL controlled transistor is kept off, and the corresponding SA output signals (high/low potentials, corresponding to stored data "1" and "0" respectively) are directly transmitted to BL through phi-WE. At the same time, the WWL controlled transistor is turned on and the SA output signal is written from the BL refresh into the storage node of the memory cell.
In fig. 5 and 8 to 11, V1 represents a sustain potential and V2 represents a precharge potential. In the figure "//" indicates memory cells connected to the same bit line, which are not shown.
Fig. 11 is a schematic circuit diagram of another access memory cell according to an embodiment of the present application, where fig. 11 includes a sense amplifier SA, two 2T0C memory cells, two column select transistors, two column select lines CSL, two precharge transistors, and two restart transistors.
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
Any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (12)

1. A semiconductor memory device, comprising:
a first bit line connected to a first memory cell;
a second bit line connected to the second memory cell;
a first sense amplifier arranged to amplify a differential input signal when the differential input signal is sensed; the device comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the second output end, and the second input end is connected with the first output end;
a first input control transistor configured to control signal input or non-input on a first bit line to a first input terminal of the first sense amplifier;
a second input control transistor configured to control signal input or non-input on a second bit line to a second input terminal of the first sense amplifier;
a first output control transistor configured to control a signal of a first output terminal of the first sense amplifier to be output to or not output from the first bit line, respectively;
a second output control transistor configured to control signal output or non-output of the second output terminal of the first sense amplifier to the second bit line;
The first memory cell and the second memory cell are 2T0C memory cells.
2. The semiconductor memory device according to claim 1, wherein,
a first pole of the first input control transistor is connected with a first bit line, and a second pole of the first input control transistor is connected with a first input end of the first sense amplifier; a first pole of the first output control transistor is connected with the first bit line, and a second pole of the first output control transistor is connected with a first output end of the first sense amplifier; the grid electrode of the first input control transistor is connected with the first input control end; the grid electrode of the first output control transistor is connected with the first output control end;
a first pole of the second input control transistor is connected with a second bit line, and a second pole of the second input control transistor is connected with a second input end of the first sense amplifier; a first end of the second output control transistor is connected with the second bit line, and a second pole of the second output control transistor is connected with a second output end of the first sense amplifier; the grid electrode of the second input control transistor is connected with the second input control end; and the grid electrode of the second output control transistor is connected with the second output control end.
3. The semiconductor memory device according to claim 1, wherein,
the first sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first ground control transistor;
the second pole of the first PMOS transistor is connected with the first pole of the first NMOS transistor; the second pole of the second PMOS transistor is connected with the first pole of the second NMOS transistor; the grid electrode of the first PMOS transistor is connected with the second pole of the second PMOS transistor, and the grid electrode of the second PMOS transistor is connected with the second pole of the first PMOS transistor; the first poles of the first PMOS transistor and the second PMOS transistor are connected and then connected to VDD; the second poles of the first NMOS transistor and the second NMOS transistor are connected and grounded through a first grounding control transistor;
a gate of the first NMOS transistor serves as a first input terminal of the first sense amplifier; a gate of a second NMOS transistor serves as a second input terminal of the first sense amplifier; a second pole of the first PMOS transistor serves as a first output terminal of the first sense amplifier; the second pole of the second PMOS transistor serves as the second output terminal of the first sense amplifier.
4. The semiconductor memory device according to claim 1, wherein,
the first sense amplifier includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a second ground control transistor;
the third PMOS transistor, the third NMOS transistor and the fourth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the third PMOS transistor and the third NMOS transistor are connected;
the fourth PMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the fourth PMOS transistor and the fifth NMOS transistor are connected;
the first poles of the third PMOS transistor and the fourth PMOS transistor are connected and then connected to VDD; the second poles of the fourth NMOS transistor and the sixth NMOS transistor are connected and grounded through a second grounding control transistor;
a grid electrode of the fourth NMOS transistor is used as a first input end of the first sense amplifier, and a grid electrode of the sixth NMOS transistor is used as a second input end of the first sense amplifier; the second pole of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor to be used as a first output end of the first sense amplifier; the second pole of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor to serve as a second output end of the first sense amplifier.
5. The semiconductor memory device according to claim 1, wherein,
the first column selection unit is corresponding to each storage unit; each first column selection unit includes a first column selection transistor; a first pole of each first column select transistor is connected to a corresponding I/O terminal; the second pole of each first column selection transistor is connected with the corresponding output end of the first sense amplifier; the gate of each first column select transistor is connected to a corresponding column select line.
6. The semiconductor memory device according to claim 1, wherein,
the device further comprises a first restarting unit and a first pre-charging unit corresponding to the first storage unit, and a second restarting unit and a second pre-charging unit corresponding to the second storage unit;
each restart unit includes a restart transistor; the first poles of the restarting transistors are respectively connected with the bit lines corresponding to the corresponding memory cells; the second pole of each restarting transistor is connected with a corresponding maintaining power supply; the grid electrode of each restarting transistor is connected with a corresponding restarting signal end;
each of the precharge units includes a precharge transistor; the first pole of the pre-charge transistor is connected with the bit line corresponding to the corresponding memory cell; the second pole of the pre-charge transistor is connected with a corresponding pre-charge source; the grid electrode of the pre-charging transistor is connected with the corresponding pre-charging signal terminal.
7. A semiconductor memory device, comprising:
a first read bit line and a first write bit line, the first read bit line configured to be connected to a read transistor connected to a third memory cell; the first write bit line is arranged to be connected to a write transistor of a third memory cell;
a second read bit line and a second write bit line, the second read bit line configured to be connected to a read transistor connected to a fourth memory cell; the second write bit line is arranged to be connected to a write transistor of a fourth memory cell;
a second sense amplifier; the second sense amplifier is arranged to amplify the differential input signal when the differential input signal is sensed; the device comprises a third input end, a fourth input end, a third output end and a fourth output end, wherein the third input end is connected with the fourth output end, and the fourth input end is connected with the third output end;
the third input end is connected with the first read bit line, the third output end is connected with the first write bit line, the fourth input end is connected with the second read bit line, and the fourth output end is connected with the second write bit line;
a third input control transistor configured to control signal input or non-input on the first read bit line to a third input terminal of the second sense amplifier;
A third output control transistor configured to control signal output or non-output of the third output terminal of the second sense amplifier to the first write bit line;
a fourth input control transistor configured to control signal input or non-input on the second read bit line to a fourth input terminal of the second sense amplifier;
a fourth output control transistor configured to control signal output or non-output of the fourth output terminal of the second sense amplifier to the second write bit line;
the third memory cell and the fourth memory cell are 2T0C memory cells.
8. The semiconductor memory device according to claim 7, wherein,
a first pole of the third input control transistor is connected to the first read bit line; a second pole of the third input control transistor is connected with a third input end of the second sense amplifier; the grid electrode of the third input control transistor is connected with the third input control end;
a first pole of the third output control transistor is connected to the first write bit line; a second pole of the third output control transistor is connected with a third output end of the second sense amplifier; the grid electrode of the third output control transistor is connected with a third output control end;
A first pole of the fourth input control transistor is connected with a fourth input end of the second sense amplifier; a second pole of the fourth input control transistor is connected with the second read bit line; the grid electrode of the fourth input control transistor is connected with the fourth input control end;
a first pole of the fourth output control transistor is connected with a fourth output end of the second sense amplifier; a second pole of the fourth output control transistor is connected with the second write bit line; and the grid electrode of the fourth output control transistor is connected with the fourth output control end.
9. The semiconductor memory device according to claim 7, wherein,
the second sense amplifier further includes a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a third ground control transistor;
the second pole of the seventh PMOS transistor is connected to the first pole of the seventh NMOS transistor; the second pole of the eighth PMOS transistor is connected to the first pole of the eighth NMOS transistor; a grid electrode of the seventh PMOS transistor is connected with a second electrode of the eighth PMOS transistor, and a grid electrode of the eighth PMOS transistor is connected with the second electrode of the seventh PMOS transistor; the first poles of the seventh PMOS transistor and the eighth PMOS transistor are connected and then connected to VDD; the second poles of the seventh NMOS transistor and the eighth NMOS transistor are connected and grounded through a first grounding control transistor;
A gate of a seventh NMOS transistor serves as a third input terminal of the second sense amplifier; a gate of the eighth NMOS transistor serves as a fourth input terminal of the second sense amplifier; a second pole of a seventh PMOS transistor serves as a third output terminal of the second sense amplifier; the second pole of the eighth PMOS transistor serves as the fourth output of the second sense amplifier.
10. The semiconductor memory device according to claim 7, wherein,
the second sense amplifier further includes a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a fourth ground control transistor;
the ninth PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the ninth PMOS transistor and the ninth NMOS transistor are connected;
the tenth PMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are sequentially connected in series through the respective first pole or second pole; the gates of the tenth PMOS transistor and the eleventh NMOS transistor are connected;
the first poles of the ninth PMOS transistor and the tenth PMOS transistor are connected and then connected to the VDD; the tenth NMOS transistor and the twelfth NMOS transistor are connected through a fourth grounding control transistor to the ground after the second poles of the tenth NMOS transistor and the twelfth NMOS transistor are connected;
A gate of the tenth NMOS transistor is used as a third input terminal of the second sense amplifier, and a gate of the twelfth NMOS transistor is used as a fourth input terminal of the second sense amplifier; a second pole of the ninth PMOS transistor is connected with a grid electrode of the tenth PMOS transistor to be used as a third output end of the second sense amplifier; a second pole of the tenth PMOS transistor is connected to a gate of the ninth PMOS transistor as a fourth output terminal of the second sense amplifier.
11. The semiconductor memory device according to claim 7, wherein,
a second column selecting unit corresponding to each memory cell; each second column selection unit includes a column selection transistor; a first pole of each column select transistor is connected to a corresponding I/O terminal; a second pole of each column selection transistor is connected with a corresponding output end of the second sense amplifier; the gate of each column select transistor is connected to a corresponding column select line.
12. The semiconductor memory device according to claim 7, wherein,
the method further comprises a third restarting unit and a third pre-charging unit corresponding to the first read bit line, a fourth restarting unit and a fourth pre-charging unit corresponding to the first write bit line, a fifth restarting unit and a fifth pre-charging unit corresponding to the second read bit line, and a sixth restarting unit and a sixth pre-charging unit corresponding to the second write bit line;
Each restart unit includes a restart transistor; the first poles of the restarting transistors are respectively connected with the corresponding read bit lines of the corresponding memory cells; the second pole of the restarting transistor is connected with a corresponding maintenance power supply; the grid electrode of the restarting transistor is connected with the corresponding restarting signal end;
each precharge unit includes a precharge transistor; the first pole of the pre-charge transistor is connected with the read bit line corresponding to the corresponding memory cell; the second pole of the pre-charge transistor is connected with a corresponding pre-charge source; the grid electrode of the pre-charging transistor is connected with the corresponding pre-charging signal terminal.
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