CN116110894A - Digital Isolators and Electronics - Google Patents

Abstract

The invention provides a digital isolator and electronic equipment, which relate to the technical field of isolators, and can ensure the safety distance between a first coil and a second coil so as to improve the voltage-resistant capability of the digital isolator.

Description

Digital Isolators and Electronics

technical field

The invention relates to the technical field of isolators, in particular to a digital isolator and electronic equipment.

Background technique

Currently, there are two mainstream isolation technologies, digital isolators and optocouplers. There are generally two types of digital isolators: one is the tolerance digital isolator based on the on-chip isolation capacitor, and the other is the magnetic isolation digital isolator based on the on-chip transformer. These two types of isolators create a layer of insulating film on the surface of the integrated circuit to achieve isolation. The material of the insulating film is generally silicon dioxide or polyimide, and the thickness is generally between 10-30um DTI (distance through insulation). The optocoupler emits light through the light-emitting diode and works on the principle of receiving light from the phototransistor. It needs to provide a translucent plastic packaging material inside the package for light transmission. The distance DTI between the light-emitting diode of the optocoupler and the phototransistor is 100-1000um.

The advantage of the digital isolator is that the signal is transmitted through the modulated high-frequency signal, the transmission delay is low, and the transmission data rate is high (up to 100-500Mbps). However, due to the small DTI, the dielectric layer may be damaged under high-voltage impact. The ultra-wide DTI of the optocoupler provides additional security, but due to physical processes involving carrier recombination and light emission, its data rate is limited in principle. The data rate of the optocoupler is mainly concentrated in the range of 1k to several Mbps. On the other hand, since the material inside the package must be transparent, the manufacturing process of the optocoupler is relatively complicated.

Therefore, it is difficult for the isolators mainly used at present to achieve a balance between process safety and signal transmission, which reduces the use efficiency of the isolator.

Contents of the invention

In view of this, the object of the present invention is to provide a digital isolator and electronic equipment to alleviate the above technical problems.

In a first aspect, an embodiment of the present invention provides a digital isolator, the digital isolator includes: a first lead frame, a second lead frame, a first integrated circuit, a second integrated circuit, and a package; the first The lead frame includes a first base island and a preset number of exposed conductors connected to the first base island; the second lead frame includes a second base island and a preset number of exposed conductors connected to the second base island. frame exposed conductors; the frame exposed conductors of the first lead frame and the frame exposed conductors of the second lead frame extend to the outside of the package for soldering the digital isolator to a printed circuit board; the The vertical height of the first base island is smaller than the longitudinal height of the second base island, and the first base island and the second base island overlap in the longitudinal direction, and the upper surface of the first base island reaches the The lower surface of the second base island is provided with a preset height difference; the first integrated circuit is fixed on the upper surface of the first base island, and the second integrated circuit is fixed on the lower surface of the second base island; the The first integrated circuit is configured with a first coil, the second integrated circuit is configured with a second coil, and the longitudinal projections of the first coil and the second coil overlap according to a preset area; the first integrated circuit and the second integrated circuit are configured with a second coil. The second integrated circuit is used to control the first coil and the second coil respectively, so as to control signal transmission between the first coil and the second coil.

Further, in a possible embodiment, the first integrated circuit provided by the embodiment of the present invention is arranged on the first chip, and fixed on the upper surface of the first base island through the first chip; The second integrated circuit is arranged on the second chip, and fixed on the lower surface of the second base island through the second chip.

Further, in a possible embodiment, the first coil provided by the embodiment of the present invention is disposed on the first chip, and the second coil is disposed on the second chip.

Further, in a possible embodiment, the above-mentioned first coil provided by the embodiment of the present invention is fixed on the first coil chip, and fixed on the upper surface of the first base island through the first coil chip; The second coil is fixed on the second coil chip, and fixed on the lower surface of the second base island through the second coil chip.

Further, in a possible embodiment, the upper surface of the first integrated circuit provided by the embodiment of the present invention faces the lower surface of the second base island; the upper surface of the second integrated circuit faces the first integrated circuit. The upper surface of a base island; the first base island includes at least one set of first bonding wires, the first bonding wires are used for the pads on the upper surface of the first integrated circuit and the first wires An electrical coupling is formed between the frames; the second base island includes at least one set of second bonding wires, the second bonding wires are used for the pads on the upper surface of the second integrated circuit and the second wires An electrical coupling is formed between the frames.

Further, in a possible embodiment, the first chip provided by the embodiment of the present invention is electrically coupled to the first coil chip through a third bonding wire; the second chip is electrically coupled through a fourth bonding wire Form electrical coupling with the second coil chip.

Further, in a possible embodiment, the preset height difference between the upper surface of the first base island and the lower surface of the second base island provided by the embodiment of the present invention is expressed as: H= T1+T2+Ts; wherein, T1 represents the thickness of the first integrated circuit, T2 represents the thickness of the second integrated circuit, and Ts represents a preset safety distance.

Further, in a possible embodiment, the range of the safety distance provided by the embodiment of the present invention includes: 100um-1000um.

Further, in a possible embodiment, the area of the first base island provided by the embodiment of the present invention is larger than the area of the first chip; the area of the second base island is larger than the area of the second chip , the longitudinal projections of the first base island and the second base island overlap; the longitudinal projections of the first chip and the second chip overlap.

Further, in a possible embodiment, the above-mentioned first coil and the second coil provided by the embodiment of the present invention are helical coils, and the centers of the first coil and the second coil are longitudinally opposite to each other. standard; the area enclosed by the projected outer boundary of the first coil partially overlaps with the area enclosed by the projected outer boundary of the second coil, and the partially overlapped area accounts for more than the area enclosed by the projected outer boundary of the first coil A preset area threshold, and the partially overlapped area accounts for an area surrounded by the projected outer boundary of the second coil greater than the preset area threshold.

Further, in a possible embodiment, the above area threshold provided by the embodiment of the present invention is at least 40%.

Further, in a possible embodiment, the number of the first integrated circuits on the above-mentioned first base island provided by the embodiment of the present invention is multiple; the second integrated circuit on the second base island There are multiple circuits; each of the first integrated circuits is configured with one of the first coils, and each of the second integrated circuits is configured with one of the second coils.

Further, in a possible embodiment, the above-mentioned first integrated circuit provided by the embodiment of the present invention includes an encoding circuit and a coil driver connected in sequence, and the coil driver is also connected to the first coil; wherein, the The encoding circuit is used to receive an input signal, and the coil driver is used to drive the first coil to generate a magnetic field signal between the first coil and the second coil according to the input signal; the second integrated circuit includes A decoding circuit and a coil receiver connected in sequence; the coil receiver is connected to the second coil; wherein the coil receiver is used to receive the magnetic field signal, restore the magnetic field signal to a digital signal, and the decoding The circuit is used for transmitting the digital signal.

Further, in a possible embodiment, the first integrated circuit provided by the embodiment of the present invention includes a first coil driver and a first coil signal receiver; the first coil driver is connected to the first coil, The first coil signal receiver is also connected to the first coil; the second integrated circuit is provided with a second coil driver and a second coil signal receiver, and the second coil driver is connected to the second coil , the coil signal receiver is also connected to the second coil; the first integrated circuit controls the enabling state of the first coil driver and the first coil signal receiver through a preset state level; The second integrated circuit controls the enabling state of the second coil driver and the second coil signal receiver through a preset state level, so as to realize bidirectional transmission through the digital isolator; the first integrated circuit The state level of the circuit changes alternately between the first coil driver enabling state and the first coil signal receiver enabling state; the state level of the second integrated circuit is between the second coil driver enabling state and the second coil signal receiving state Alternate between the enable state of the device.

Further, in a possible embodiment, the first coil provided by the embodiment of the present invention includes a first winding and a second winding; the first coil driver is connected to the first winding, and the first coil The signal receiver is connected to the second winding; the second coil includes a third winding and a fourth winding; the second coil driver is connected to the third winding, and the second coil signal receiver is connected to the The fourth winding is connected.

Further, in a possible embodiment, the inductance value of the fourth winding provided in the embodiment of the present invention is greater than the inductance value of the first winding; the inductance value of the second winding is greater than that of the third winding inductance value.

Further, in a possible embodiment, the above-mentioned first winding and the second winding provided by the embodiment of the present invention are provided with preset overlapping wiring areas; the third winding and the fourth winding are provided There are trace areas that overlap by default.

Further, in a possible embodiment, the above-mentioned first winding and the second winding provided by the embodiment of the present invention are helical coils, and at least a part of the second winding is located between the first winding and the The inner side of the preset overlapping wiring area of the second winding; the third winding and the fourth winding are also spiral coils, and at least a part of the fourth winding is located in the third winding and the fourth winding The inner side of the routing area where the windings are preset to overlap.

Further, in a possible embodiment, the first integrated circuit provided by the embodiment of the present invention further includes a first signal conversion module; the first signal conversion module includes a multi-channel input interface, and the first The output end of the signal conversion module is connected to the encoding circuit; the second integrated circuit also includes a second signal conversion module; the second signal conversion module includes a multi-channel output interface, and the second signal conversion module The input terminal is connected to the decoding circuit; the first signal conversion module is used to convert multiple input signals into serial signals and transmit them to the second integrated circuit; the decoding circuit of the second integrated circuit is used for The serial signal is decoded, and the serial signal is recovered and output by the second signal conversion module.

Further, in a possible embodiment, the first integrated circuit provided by the embodiment of the present invention includes a first signal conversion module connected to the first coil driver, and a first signal conversion module connected to the first coil signal receiver. The second signal conversion module; the second integrated circuit includes a third signal conversion module connected to the second coil driver, and a fourth signal conversion module connected to the second coil signal receiver; wherein, the The first signal conversion module corresponds to the fourth signal conversion module, and the first signal conversion module is used to convert multiple input signals of the first integrated circuit into serial signals and transmit them to the second integrated circuit circuit; the decoding circuit of the second integrated circuit is used to decode the serial signal, and restore and output the serial signal through the fourth signal conversion module; the second signal conversion module and Corresponding to the third signal conversion module, the third signal conversion module is used to convert multiple input signals of the second integrated circuit into serial signals and transmit them to the first integrated circuit; the first integrated circuit The decoding circuit of the circuit is used for decoding the serial signal, and recovering and outputting the serial signal through the third signal conversion module, so as to realize bidirectional transmission of the digital isolator.

In a second aspect, an embodiment of the present invention further provides an electronic device configured with the digital isolator described in the first aspect.

Embodiments of the present invention bring the following beneficial effects:

A digital isolator and electronic equipment provided by an embodiment of the present invention include a first lead frame, a second lead frame, a first integrated circuit, a second integrated circuit, and a package in the digital isolator; the first lead frame includes a first A base island and a preset number of frame exposed conductors connected to the first base island; the second lead frame includes a second base island and a preset number of frame exposed conductors connected to the second base island; the frame of the first lead frame The exposed conductor and the exposed conductor of the frame of the second lead frame extend to the outside of the package body, and are used for soldering the digital isolator to the printed circuit board; the longitudinal height of the first base island is smaller than the longitudinal height of the second base island, and the first The base island and the second base island overlap vertically, and a preset height difference is set from the upper surface of the first base island to the lower surface of the second base island; the first integrated circuit is fixed on the upper surface of the first base island, and the second integrated circuit The circuit is fixed on the lower surface of the second base island; the first integrated circuit is configured with a first coil, the second integrated circuit is configured with a second coil, and the longitudinal projections of the first coil and the second coil overlap according to a preset area; the first The integrated circuit and the second integrated circuit are respectively used to drive the first coil and the second coil to control the signal transmission between the first coil and the second coil, since the upper surface of the first base island is connected to the second base island The lower surface is provided with a preset height difference, therefore, a safe distance between the first coil and the second coil can be ensured, thereby improving the withstand voltage capability of the digital isolator. At the same time, the first coil and the second coil pass through the first integrated circuit Driven with the second integrated circuit, no photosensitive device is required to achieve optical isolation. Therefore, there is no special requirement for the material of the package body, which reduces the process requirements, not only helps to achieve a balance between process and signal transmission, but also helps to improve isolator usage efficiency and reduces application cost.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the specific implementation or description of the prior art. Obviously, the accompanying drawings in the following description The drawings show some implementations of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without creative work.

FIG. 1 is a schematic structural diagram of a digital isolator provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a three-dimensional structure of a digital isolator provided by an embodiment of the present invention;

Fig. 3 is a top view of a digital isolator provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another digital isolator provided by an embodiment of the present invention;

FIG. 5 is a top view of another digital isolator provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of a coil provided by an embodiment of the present invention;

FIG. 7 is a top view of another digital isolator provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of signal transmission provided by an embodiment of the present invention;

FIG. 9 is another schematic diagram of signal transmission provided by an embodiment of the present invention;

FIG. 10 is a timing diagram provided by an embodiment of the present invention;

Fig. 11 is a schematic diagram of a coil provided by an embodiment of the present invention;

Fig. 12 is a schematic diagram of a winding provided by an embodiment of the present invention;

FIG. 13 is another schematic diagram of signal transmission provided by an embodiment of the present invention;

FIG. 14 is another schematic diagram of signal transmission provided by an embodiment of the present invention.

Icons: 11-first lead frame; 12-second lead frame; 13-first integrated circuit; 14-second integrated circuit; 10-package body; 111-first base island; 111a-frame of first lead frame 121-the second base island; 121a-the frame exposed conductor of the second lead frame; 132-the first coil; 142-the second coil; 13a-the first chip; 14a-the second chip; 161-the first coil Chip; 171 - second coil chip; 151 - first bonding wire; 152 - second bonding wire; 181 - third bonding wire; 191 - fourth bonding wire.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. the embodiment. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

The advantage of the digital isolator is that the signal is transmitted through the modulated high-frequency signal, the transmission delay is low, and the transmission data rate is high (up to 100-500Mbps). However, due to the small DTI, the dielectric layer may be damaged under high-voltage impact. An optocoupler is also a kind of isolator, and its ultra-wide DTI provides additional security. However, since the optocoupler involves physical processes such as carrier recombination and light emission, its data rate is limited in principle, and the data rate of the optocoupler is mainly concentrated. In the 1k to several Mbps range. On the other hand, since the material inside the package must be transparent, the manufacturing process of the optocoupler is relatively complicated.

Based on this, the embodiment of the present invention provides a digital isolator and electronic equipment, so that the digital isolator not only has the advantages of high data transmission and low power consumption of the traditional on-chip insulating film type isolator; Reliable advantages; at the same time, there is no need to use transparent materials for secondary packaging, which significantly simplifies the complexity of the manufacturing process of digital isolators.

To facilitate the understanding of this embodiment, a digital isolator disclosed in this embodiment of the present invention is firstly introduced in detail.

In a possible implementation, an embodiment of the present invention provides a digital isolator, specifically, a schematic structural diagram of a digital isolator as shown in FIG. 1 , where FIG. 1 shows a digital isolator As shown in FIG. 1 , the digital isolator in the embodiment of the present invention includes: a first lead frame 11 , a second lead frame 12 , a first integrated circuit 13 , a second integrated circuit 14 and a package body 10 .

For ease of description, corresponding to the side view shown in FIG. 1 , FIG. 2 also shows a schematic three-dimensional structural diagram of a digital isolator, and FIG. 3 also shows a top view of a digital isolator.

Further, it can be seen from FIG. 2 and FIG. 3 that the first lead frame includes a first base island 111 and a preset number of frame exposed conductors 111a communicating with the first base island 111, and the second lead frame includes a second base island 121 and A preset number of frame exposed conductors 121a communicated with the second base island 121; the frame exposed conductors of the first lead frame and the frame exposed conductors of the second lead frame extend to the outside of the package body 10 for soldering the digital isolator to A printed circuit board.

The exposed conductor of the frame refers to the conductor exposed outside the molded package plastic package, which is used to electrically couple the external circuit and the internal chip circuit, such as the gull-wing pin in the SOP package, and the in-line pin in the DIP package. type leads, or pads in "leadless" packages such as DFN/QFN, etc.

Further, it can be seen from Fig. 1 and Fig. 2 that the longitudinal height of the first base island 111 is smaller than the longitudinal height of the second base island 121, and the first base island 111 and the second base island 121 overlap in the longitudinal direction, the first base island 111 There is a preset height difference from the upper surface of the base island 111 to the lower surface of the second base island 121;

The first integrated circuit 13 is fixed on the upper surface of the first base island, and the second integrated circuit 14 is fixed on the lower surface of the second base island;

The first integrated circuit 13 is configured with a first coil 132, the second integrated circuit 14 is configured with a second coil 142, and the longitudinal projections of the first coil 132 and the second coil 142 overlap according to a preset area;

The first integrated circuit 13 and the second integrated circuit 14 are respectively used to control the first coil 132 and the second coil 142 to control signal transmission between the first coil and the second coil.

In actual use, the above-mentioned longitudinal direction in the embodiment of the present invention refers to the direction indicated by the arrow 21 in Fig. 1 and Fig. 2, when the digital isolator is soldered to the printed circuit board, the longitudinal direction and the plane of the printed circuit board vertical.

Further, in the embodiment of the present invention, the first base island and the second base island have different vertical heights, wherein, and in the embodiment of the present invention, the vertical height of the first base island is smaller than the longitudinal height of the second base island as an example , in other embodiments, it can also be set so that the longitudinal height of the first base island is greater than the longitudinal height of the second base island, as long as the longitudinal heights of the first base island and the second base island meet the preset height difference, specifically The actual use shall prevail, and this embodiment of the present invention shall not limit it.

Moreover, the digital isolator provided by the embodiment of the present invention can ensure the safety between the first coil and the second coil because there is a preset height difference between the upper surface of the first base island and the lower surface of the second base island. distance, thereby improving the withstand voltage capability of the digital isolator. At the same time, the first coil and the second coil are controlled by the first integrated circuit and the second integrated circuit, and no photosensitive device is required to achieve optical isolation. Therefore, the material of the package There are no special requirements for light transmission, which reduces the process requirements, not only helps to achieve a balance between process and signal transmission, but also helps to improve the use efficiency of the isolator and reduce application costs.

In actual use, the above-mentioned first integrated circuit is usually arranged on the first chip, and is fixed on the upper surface of the first base island through the first chip; further, the above-mentioned second integrated circuit is also arranged on the second chip, through the second The chip is fixed on the lower surface of the second base island.

For example, an adhesive may be used to bond the substrate (back) of the first chip to the upper surface of the first base island, and an adhesive to bond the substrate (back) of the second chip to the top surface of the second base island. The lower surface is glued.

Further, for the above-mentioned first coil, it can also be set on the first chip, and the second coil can also be set on the second chip, that is, the coil and the integrated circuit are set on the same chip, which is beneficial to simplify the digital isolator packaging process.

In addition, in the isolator shown in FIGS. 1 to 3 , the coil and the integrated circuit are described as an example where they are provided on the same chip.

In addition, in other embodiments, the integrated circuit and the coil can also be disposed on different chips, that is, the chip for fixing the coil and the chip for forming the integrated circuit are separately disposed. Specifically, the first coil can be fixed on the first coil chip, and the first coil can be fixed on the upper surface of the first base island through the first coil chip; the second coil can be fixed on the second coil chip, and the second coil The chip fixes the second coil on the lower surface of the second base island.

For ease of understanding, Figure 4 also shows a schematic structural diagram of another digital isolator, taking the integrated circuit and the coil manufactured on different chips as an example, where Figure 4 also shows a side view, except that shown in Figure 1 The structures of the first lead frame and the second lead frame also include the first chip 13a provided with the first integrated circuit, the second chip 14a provided with the second integrated circuit, and the first coil chip 161 and the second coil Chip 171 corresponds to the side view shown in FIG. 4, and FIG. 5 shows a top view of another digital isolator. Similarly, in addition to the structure of the first lead frame and the second lead frame, it also includes the first chip 13a, the second lead frame Two chips 14 a , a first coil chip 161 and a second coil chip 171 .

In actual use, the above-mentioned first coil chip and the second coil chip, like the first chip of the first integrated circuit and the second chip of the second integrated circuit, can be bonded to the substrate (back side) of the chip by an adhesive Bonding and fixing, and the digital isolator shown in Figure 4 and Figure 5 above can be manufactured using different processes because the integrated circuit and the coil are manufactured on different chips, and the coil manufacturing process and area can be adjusted independently, thereby Get better performance and cost performance.

Further, based on the structure of the first lead frame and the second lead frame in the embodiment of the present invention, the upper surface of the first integrated circuit faces the lower surface of the second substrate island; the upper surface of the second integrated circuit faces the first substrate The upper surface of the island; and, the above-mentioned first base island includes at least one set of first bonding wires, and the first bonding wires are used to form electrical coupling between the pads on the upper surface of the first integrated circuit and the first lead frame; Wherein, the first bonding wire 151 is shown in FIGS. 1 to 3 . The corresponding second base island also includes at least one group of second bonding wires, that is, the second bonding wires 152 in FIGS. An electrical coupling is formed with the second lead frame.

Further, for an embodiment where the integrated circuit and the coil are fabricated on different chips, the digital isolator is also provided with bonding wires. Specifically, as shown in FIGS. 4 and 5 , the first chip 13a is electrically coupled to the first coil chip 161 through the third bonding wire 181; the second chip 14a is connected to the second coil through the fourth bonding wire 191. Chip 171 forms an electrical coupling. Simultaneously, among Fig. 4 and Fig. 5, also comprise the first bonding wire 151, at this moment, the first bonding wire 151 is provided with the bonding pad on the surface of the first chip 13a on the first integrated circuit and the first lead frame Similarly, the second bonding wire 152 forms an electrical coupling between the bonding pad of the second chip 14a provided with the second integrated circuit and the second lead frame.

Further, the preset height difference between the upper surface of the first base island and the lower surface of the second base island in the embodiment of the present invention is generally expressed as: H=T1+T2+Ts;

Wherein, T1 represents the thickness of the first integrated circuit, as shown in Figure 4, T1 can include the thickness of the first chip and the first coil chip, generally refers to the thickness of the chip that contains the coil structure; similarly, as shown in Figure 4 T2 represents the thickness of the second integrated circuit, and Ts represents the preset safety distance. During specific implementation, the range of the above-mentioned safety distance includes: 100um-1000um, specifically, the safety distance is preferably 200um-500um. In actual use, the safety distance is selected to provide galvanic isolation (galvanic isolation) between the first integrated circuit and the second integrated circuit. When the first integrated circuit and the second integrated circuit are arranged between the first chip and the For the second chip, galvanic isolation is also formed between the first chip and the second chip.

Specifically, the above-mentioned safe distance in the embodiment of the present invention differs from the traditional capacitive-coupled digital isolator and magnetic-coupled digital isolator in that: 1. The safe distance in the embodiment of the present invention is between 100um-1000um, which is traditional 10 times to 100 times that of digital isolators, which can achieve extremely high withstand voltage; 2. An isolation medium can be set between the safety distances, that is, packaging materials, such as epoxy materials and resin materials for plastic packaging, or filled with insulators (filler) plastic packaging material, etc., and the physical position of the safety distance is outside the chip of the integrated circuit. Therefore, when the chip of the integrated circuit, such as the first chip or the second chip itself, an EOS (electrostatic overstress) event occurs, In the event of an ESD (electrostatic discharge) event or other destructive events, it will not have a destructive effect on the isolation medium physically located outside the two chips. Therefore, even if the two chips are damaged, isolation protection can still be provided between the first chip and the second chip, further improving the stability of the digital isolator.

Further, in actual use, since the first chip and the above-mentioned first coil chip are usually arranged on the first base island, the area of the first base island in the embodiment of the present invention is usually larger than the area of the first chip; similarly , the area of the second base island is also larger than the area of the second chip.

Preferably, the area of the first base island is greater than the area covered by the expansion of 200um on each of the four sides of the first chip; the area of the second base island is greater than the area covered by the expansion of 200um on each of the four sides of the second chip; for example, as shown in Figure 3 The top view shown is taken as an example. Since the first base island and the second base island overlap vertically, for the convenience of drawing, in FIG. 3 , the second base island and the second chip use dashed lines. In the embodiment of the present invention, the area of the first base island and the second base island is larger than the area of the chip (the first chip and the second chip) mainly for two purposes: one is to facilitate the fixing of the chip on the base island and provide the chip with a physical Support; the second is that the base island is a good conductor, which can shield the external electromagnetic field from interfering with the first chip and the second chip, and can also reduce the outward electromagnetic field generated by the first chip/coil and the second chip/coil radiation.

Further, in order to facilitate the signal transmission between the first coil and the second coil, in the embodiment of the present invention, the longitudinal projections of the first base island and the second base island overlap; the longitudinal projections of the first chip and the second chip There is overlap, and at the same time, the longitudinal projections of the first coil and the second coil overlap.

Specifically, in the embodiment of the present invention, the first coil and the second coil are helical coils, and the centers of the first coil and the second coil are longitudinally aligned, wherein the longitudinal direction is the same as that indicated by the arrow 21 in Fig. 1 and Fig. 2 The directions of the fingers are consistent, the centers of the first coil and the second coil are longitudinally aligned, which means that the projections of the centers of the first coil and the second coil in the longitudinal direction can coincide, or the centers of the first coil and the second coil are aligned in the longitudinal direction The projected distance is less than a certain threshold to meet the alignment requirements.

For ease of understanding, FIG. 6 shows a schematic diagram of a coil, including a first coil 132 and a second coil 142. Specifically, as shown in FIG. 6, the area enclosed by the projected outer boundary of the first coil 132 and the second coil The area enclosed by the projected outer boundary of 142 is partially overlapped, and the partially overlapped area accounts for the area enclosed by the projected outer boundary of the first coil is greater than the preset area threshold, and the partially overlapped area accounts for the projected outer boundary of the second coil. The surrounding area is greater than the preset area threshold. Wherein, in the embodiment of the present invention, the above-mentioned area threshold is generally represented by a percentage, and usually the area threshold is set to 40%, that is, it accounts for more than 40% of the area surrounded by the projected outer boundary of the first coil or the second coil. Preferably, Accounted for more than 80%.

It should be noted that the area enclosed by the projected outer boundary of the first coil and the projected outer boundary of the second coil in the embodiment of the present invention refer to the area enclosed by the projected outer boundary of the coil, without subtracting the inner hollow space of the coil. the area of the part. Due to design requirements, the area enclosed by the projected outer boundary of the first coil and the area enclosed by the projected outer boundary of the second coil can be the same or different. Therefore, in the embodiment of the present invention, it is required that the projected overlapping area accounts for the first coil and the second coil respectively. The ratio of the peripheral area of the two coils. Moreover, due to the deviation of the manufacturing process, the centers of the two coils cannot be completely aligned, so the ratio of the projected area to the total area is used to describe the degree of alignment to ensure the performance of the digital isolator.

Further, for some usage scenarios that require a large bandwidth, in order to obtain a larger communication bandwidth, the number of the first integrated circuits on the above-mentioned first base island can be multiple; at the same time, the second integrated circuit on the second base island The number of circuits is plural. For ease of understanding, FIG. 7 also shows a top view of another digital isolator, wherein FIG. 7 shows an embodiment including two first integrated circuits and two second integrated circuits. Specifically, in FIG. 7 , showing the first base island 111, and the two first integrated circuits 13 on the first base island 111, and the second base island 121, and the two second integrated circuits 14 on the second base island 121 . Additionally, multiple bond wires are shown in Figure 7, and, in Figure 7, a separate schematic (left side) of the first and second leadframes is shown, as well as the overall Schematic (right). Specifically, as shown in FIG. 7 , each first integrated circuit is configured with a first coil 132 , and each second integrated circuit is configured with a second coil 142 . Based on the embodiment of a plurality of coils shown in FIG. 7 , the first coil and the second coil of each group have overlapping areas in longitudinal projection, and the area enclosed by the outer boundary of the first coil projection and the area enclosed by the outer boundary of the second coil projection The overlapping area accounts for more than 40% of the area enclosed by the outer boundary of the first coil projection (and the area enclosed by the outer boundary of the second coil projection), preferably, accounts for more than 80%.

It should be understood that FIG. 7 is an example in which each base island includes two sets of coils. In other implementations, the number of coils can be set according to actual usage, which is not limited in this embodiment of the present invention.

In actual use, in order to realize the control of the coil by the integrated circuit, the above-mentioned first integrated circuit in the embodiment of the present invention includes an encoding circuit and a coil driver connected in sequence, and the coil driver is also connected to the first coil; wherein the encoding circuit For receiving an input signal, the coil driver is used to drive the first coil according to the input signal, and generate a magnetic field signal between the first coil and the second coil; the second integrated circuit includes a decoding circuit and a coil receiver connected in sequence; the coil receiver It is connected with the second coil; wherein, the coil receiver is used for receiving the magnetic field signal, recovering the magnetic field signal into a digital signal, and the decoding circuit is used for transmitting the digital signal.

For ease of understanding, FIG. 8 shows a schematic diagram of signal transmission. Specifically, in FIG. 8, an encoding circuit B111 and a coil driver B11 are shown, wherein, in the embodiment of the present invention, the coil driver is represented by TX, and the coil driver and The first coil 132 is connected. Further, in FIG. 8, the decoding circuit B211 and the coil receiver B21 of the second integrated circuit are also shown, wherein, in the embodiment of the present invention, the coil receiver is represented by RX; the coil receiver and the first coil receiver The two coils 142 are connected together. Moreover, Fig. 8 also shows a safety distance, that is, DTI. In Fig. 8, it is indicated by oblique lines. In this safety distance, an isolation medium is generally provided to form an isolation medium layer. The specific material of the isolation medium can be determined according to It is set according to actual usage requirements, which is not limited in this embodiment of the present invention.

Specifically, the encoding circuit B111 generates an encoding signal according to the level of the input signal, for example, when the level of the input signal is high, the encoding signal forms a first characteristic signal in the first coil through the coil driver B11; the level of the input signal is low , the encoding signal forms the second characteristic signal on the first coil through the coil driver B11, and the first coil forms a magnetic field under the action of the first characteristic signal and the second characteristic signal, that is, B13 indicated by the arrow, and the magnetic field is at the preset height difference The medium, such as the insulating medium, propagates to the vicinity of the second coil, that is, the magnetic field B23 indicated by the arrow, and forms a receiving signal at both ends of the second coil.

At this time, the coil receiver B21 of the second integrated circuit restores the received signal to a digital signal, and then the decoding circuit B211 of the second integrated circuit judges that the signal satisfies the first characteristic or the second characteristic, so that the output level Set to match the input level to achieve signal transmission.

Specifically, the above-mentioned first characteristic signal may be a first number of pulses, and the second characteristic signal corresponds to a second number of pulses; or: the first characteristic signal is a pulse of the first polarity, and the second characteristic signal corresponds to A pulse of the second polarity, or: the first characteristic signal is an oscillation of the first duration, the second characteristic signal is a non-oscillation or an oscillation signal of the second duration, or the first characteristic signal is a signal of at least one of the above three signals Combination, the second characteristic signal is also a corresponding combination signal, and so on. Specifically, the signal depends on the actual input signal, which is not limited in this embodiment of the present invention.

It should be understood that the foregoing FIG. 8 shows an implementation manner of unidirectional transmission of digital signals, and in other embodiments, the digital isolator in the embodiment of the present invention may also implement bidirectional transmission of digital signals.

Corresponding to the implementation mode of bidirectional transmission, the first integrated circuit in the embodiment of the present invention includes a first coil driver and a first coil signal receiver; the first coil driver is connected to the first coil, and the first coil signal receiver is also connected to the first coil signal receiver. A coil is connected; the corresponding second integrated circuit is provided with a second coil driver and a second coil signal receiver, the second coil driver is connected to the second coil, and the coil signal receiver is also connected to the second coil; in realizing two-way signal transmission , the first integrated circuit controls the enable state of the first coil driver and the first coil signal receiver through the preset state level; the second integrated circuit controls the second coil driver and the second coil through the preset state level Enable state of the signal receiver for bidirectional transmission through the digital isolator.

For ease of understanding, FIG. 9 shows another schematic diagram of signal transmission to further illustrate the above bidirectional transmission process.

Specifically, as shown in Figure 9, it includes a first coil driver TX1 and a first coil signal receiver RX1, a second coil driver TX2 and a second coil signal receiver RX2, and an encoding circuit connected to each coil driver and A decoding circuit connected with each coil signal receiver.

During specific implementation, the above-mentioned first integrated circuit has two states controlled by the state level (STATE): the first level driving state (for example, take logic level 0 as an example, without limitation) and the second level receiving State (take logic level 1 as an example); the corresponding second integrated circuit has two states controlled by logic level: driving state (take logic level 0 as an example, no limitation) and receiving state (take logic level Ping 1 as an example); when the logic control of the integrated circuit is in the driving state, the coil driver can be set to the enabling state through the control state circuit; when the logic control of the integrated circuit is in the receiving state, the coil driver can be set through the control state circuit Set to disabled state, such as TX1 output is high-impedance state. For example, when the state level of the first chip corresponding to the first integrated circuit is the first level, if the input of the first chip is at the high level at this time, the first characteristic signal will be sent to the first coil. When the input of the chip is low level, the second characteristic signal is sent to the first coil; if the first chip is at the second level, if the first chip receives the first characteristic signal at this time, it will pass through the decoding circuit Set the output to a high level; if the first chip receives the second characteristic signal at this time, the output is set to a low level through the decoding circuit, and a similar signal transmission is also used for the second chip corresponding to the second integrated circuit The mode and the specific level state can be set according to the actual use situation, which is not limited in the embodiment of the present invention.

Further, when the state level of the first chip corresponding to the first integrated circuit is the first level, and the first delay (Δta) of the emission of the characteristic signal is completed, the timing circuit of the first chip can control the state of the first integrated circuit level conversion to the second level;

When the state level of the first chip corresponding to the first integrated circuit is the second level, after the second delay (Δtb) is performed after receiving the characteristic signal, the sequential circuit of the first chip can control the state of the first integrated circuit level conversion to the first level;

For the second chip of the second integrated circuit, the above-mentioned similar level conversion process can also be used to automatically trigger state changes between the first integrated circuit and the second integrated circuit, and to realize alternate signal transmission and reception, thereby using A single channel realizes bidirectional transmission of signals. For ease of understanding, Figure 10 shows a timing diagram. The state level of the second chip, wherein the timing of the state level of the first chip is represented by state1, and the timing of the state level of the second chip is represented by state2, and, in FIG. 10, the first integrated circuit is also shown respectively and the timing diagram of the input (Input), output (Output) of the second integrated circuit, and the driver TX.

And, as can be seen from FIG. 10, the state level of the first integrated circuit changes alternately between the enabling state of the first coil driver and the enabling state of the first coil signal receiver; the state level of the second integrated circuit changes in the second Alternate between coil driver enabled and second coil signal receiver enabled states. And, the change from the driver enable state to the receiver enable state is determined by the driving signal time and the first delay time; the change from the receiver enable state to the transmitter enable state starts when the receiver receives the signal The timing second delay time is determined; and the second delay time is greater than the sum of the driving signal time and the first delay time.

In actual use, after the first chip or the second chip sends the signal, usually, it will automatically switch to the receiving state after waiting for a certain period of time. When the first chip or the second chip is in the receiving state, after receiving the signal, wait for a period of time until the signal reception is completed, that is, turn into the transmitting mode.

Usually, the above-mentioned second delay time must be greater than the duration of the signal with a longer duration in the first characteristic signal and the second characteristic signal, so as to ensure that the receiving time is long enough to ensure that the transmitted signal can be completely received. If the second delay is too short, only part of the transmitted signal may be received, which may result in an output error. Therefore, the second delay may be set to meet the signal reception requirements.

Further, in order to facilitate the above bidirectional transmission, the first coil in the embodiment of the present invention includes a first winding and a second winding. Specifically, FIG. 11 shows a schematic diagram of a coil, including a first winding B1A and a second winding B1B , at this time, the above-mentioned first coil driver TX1 is connected to the first winding B1A, and the first coil signal receiver RX1 is connected to the second winding B1B; the corresponding second coil also includes two windings, that is, the third winding in FIG. 11 The winding B2A is connected to the fourth winding B2B, wherein the second coil driver TX2 is connected to the third winding B2A, and the second coil signal receiver RX2 is connected to the fourth winding B2B.

Preferably, the inductance value of the fourth winding in the embodiment of the present invention is greater than the inductance value of the first winding; the inductance value of the second winding is greater than the inductance value of the third winding, that is, the coil shown in (1) in FIG. 11 Taking the coil length as an example to represent the inductance value, the length of the fourth winding B2B is greater than that of the first winding B1A, and the length of the second winding B1B is greater than that of the third winding B2A.

Wherein, the size requirement of the above-mentioned inductance value in the embodiment of the present invention is generally determined by the above-mentioned safety distance, because the distance between the two coils in the embodiment of the present invention is relatively far, that is, the range of the safety distance includes: 100um-1000um, Therefore, the coupling coefficient is not high. Since the coupling coefficient is mainly determined by the outer diameter of the coil and the distance between the receiving coil and the transmitting coil, increasing the ratio of the fourth winding to the first winding, and the ratio of the second winding to the third winding can increase Voltage gain, that is, a higher voltage gain can be achieved with a weaker coupling coefficient.

However, due to the limited area of the chip for setting the coil, or the limited area of the above-mentioned first base island and the second base island, and considering the high cost of setting two sets of independent coils, the embodiment of the present invention The first winding and the second winding are provided with preset overlapping routing areas; meanwhile, the third winding and the fourth winding are also provided with preset overlapping routing areas. That is, the overlapping schematic diagram of the two groups of coils shown in (2) of FIG. 11 , it can be seen that the first winding and the second winding have a common routing part; the third winding and the fourth winding have a common routing part.

Based on the schematic diagram of the coil shown in Figure 11, the first winding and the second winding, the third winding and the fourth winding share a part of the wiring, which is beneficial to save the area of the entire digital isolator, realize miniaturization, and reduce the cost of the digital isolator. At the same time, for any side of the coil, the structure of the winding connected to the circuit changes with time. At different times, the physical structure of the winding connected to the circuit is different (equivalent to a dynamically changing coil), so , can obtain a higher voltage gain, and also realize the bidirectional transmission of signals.

Further, the above-mentioned first winding and second winding in the embodiment of the present invention are spiral coils, and at least a part of the second winding is located inside the preset overlapping routing area of the first winding and the second winding; similarly, the first winding The third winding and the fourth winding are also helical coils, and at least a part of the fourth winding is located inside the preset overlapping wiring area of the third winding and the fourth winding.

For ease of understanding, FIG. 12 also shows a schematic diagram of a winding. Referring to FIG. 12 , it shows an embodiment in which the coils have a common routing, and for the convenience of description, only one coil is used as an example for illustration.

A和D与第二线圈信号接收器RX2相连，而第一绕组为

因此，

为第一绕组和第二绕组的共同走线部分，而

这部分位于

的内侧，这样做有两个好处：且第二绕组至少有一部分位于第一绕组和第二绕组的共同走线部分的内部可以确保第二绕组的电感值大于第一绕组，同时，第二绕组和第一绕组之间的耦合由处于外侧的两个线圈的共同走线部分确定，具有比较高的耦合系数。As shown in Figure 12, it is assumed that the order of the second winding along the helix is

A and D are connected to the second coil signal receiver RX2, while the first winding is

therefore,

is the common routing part of the first winding and the second winding, and

This part is located in

This has two advantages: and at least a part of the second winding is located inside the common wiring part of the first winding and the second winding, which can ensure that the inductance value of the second winding is greater than that of the first winding. At the same time, the second winding The coupling with the first winding is determined by the common routing part of the two outer coils, which has a relatively high coupling coefficient.

Furthermore, the digital isolator provided in the embodiment of the present invention can also satisfy the isolation and transmission of multiple signals. Specifically, for the implementation of unidirectional signal transmission, the first integrated circuit in the embodiment of the present invention further includes a first signal conversion module; the first signal conversion module includes a multi-channel input interface, and the first signal conversion module The output end is connected to the encoding circuit; the second integrated circuit also includes a second signal conversion module; the second signal conversion module includes a multi-channel output interface, and the input end of the second signal conversion module is connected to the decoding circuit; the first signal conversion module It is used to convert multiple input signals into serial signals and transmit them to the second integrated circuit; the decoding circuit of the second integrated circuit is used to decode the serial signals and restore the serial signals through the second signal conversion module output.

Specifically, FIG. 13 shows another schematic diagram of signal transmission. Corresponding to the schematic diagram of signal transmission shown in FIG. 8, the first integrated circuit also includes a first signal conversion module 120. It is a parallel-to-serial P2S module, which can convert the input signals INPUT1~INPUTN of multiple input interfaces into serial signals and send them to the second integrated circuit, and decode them by the decoding circuit of the second integrated circuit, and then set them in The second signal conversion module 122 of the second integrated circuit restores and outputs the multiple signals, wherein the second signal conversion module is a serial-to-parallel S2P module, so as to restore the multiple signals to ONPUT1-ONPUTN for output.

Further, corresponding to the bidirectional transmission process shown in FIG. 9, FIG. 14 also shows another schematic diagram of signal transmission. Specifically, as shown in FIG. 14, in the embodiment of the present invention, the first integrated circuit includes the first coil and A first signal conversion module 130 connected to the driver, and a second signal conversion module 131 connected to the first coil signal receiver; correspondingly, the second integrated circuit includes a third signal conversion module 140 connected to the second coil driver, And the fourth signal conversion module 141 connected with the second coil signal receiver.

Wherein, the first signal conversion module corresponds to the fourth signal conversion module, and the first signal conversion module is used to convert multiple input signals of the first integrated circuit into serial signals and transmit them to the second integrated circuit; The decoding circuit is used to decode the serial signal, and restore and output the serial signal through the fourth signal conversion module;

Further, the second signal conversion module corresponds to the third signal conversion module, and the third signal conversion module is used to convert the multiple input signals of the second integrated circuit into serial signals and transmit them to the first integrated circuit; The decoding circuit is used for decoding and processing the serial signal, and recovering and outputting the serial signal through the third signal conversion module, so as to realize bidirectional transmission of the digital isolator.

During specific implementation, in FIG. 14 , the first signal conversion module 130 on the first integrated circuit is equivalent to an N-way parallel-to-serial P2S module, which converts N-way input signals into serial models, and the first coil driver send out; the fourth signal conversion module on the second integrated circuit is equivalent to an N-way serial-to-parallel S2P module, which restores the received signal to N-way parallel signal output; similarly, the third signal conversion module on the second integrated circuit The signal conversion module is equivalent to an M-channel parallel-to-serial P2S module, which converts the M-channel input signal into a serial signal, which is sent by the second coil driver; the second signal conversion module on the first integrated circuit is equivalent to an M One-way serial-to-parallel S2P module, which restores the received signal to M-way parallel signals for output.

Through the implementations in Figure 13 and Figure 14, one-way or two-way transmission of multi-channel signals can be realized, and the number of specific signal channels can be set according to actual usage conditions, which is not limited in this embodiment of the present invention.

In summary, the digital isolator provided by the embodiment of the present invention not only has the advantages of high data transmission and low power consumption of the traditional on-chip insulating film isolator; it also has the advantages of large DTI, safety and reliability of the traditional optocoupler; at the same time, it does not need to use transparent The material is packaged twice, which significantly simplifies the complexity of the manufacturing process of the isolator, and can realize high-speed signal transmission at the same time.

Further, on the basis of the above embodiments, the embodiments of the present invention also provide an electronic device, where the electronic device is configured with the digital isolator described in the above embodiments.

The electronic device provided by the embodiment of the present invention has the same technical features as the digital isolator provided by the above embodiment, so it can also solve the same technical problem and achieve the same technical effect.

The computer program product of the digital isolator and electronic equipment provided by the embodiments of the present invention includes a computer-readable storage medium storing program codes, and the instructions included in the program codes can be used to execute the methods described in the previous embodiments, specifically For implementation, reference may be made to the foregoing embodiments, and details are not repeated here.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the electronic device described above can refer to the corresponding process in the foregoing embodiments, which will not be repeated here.

In addition, in the description of the embodiments of the present invention, unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be interpreted in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, or in a specific orientation. construction and operation, therefore, should not be construed as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

Finally, it should be noted that: the above examples are only specific implementations of the present invention, to illustrate the technical solutions of the present invention, rather than to limit them, and the protection scope of the present invention is not limited thereto, although with reference to the foregoing examples The present invention has been described in detail, and those skilled in the art should understand that: within the technical scope disclosed by the present invention, any person skilled in the art can still modify the technical solutions described in the foregoing embodiments or can easily think of them Changes, or equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be covered by the protection scope of the present invention Inside. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (21)

1. A digital isolator, characterized in that the digital isolator comprises: a first lead frame, a second lead frame, a first integrated circuit, a second integrated circuit and a package; The first lead frame includes a first base island and a preset number of frame exposed conductors communicating with the first base island; the second lead frame includes a second base island and a second base island communicating with the second base island Preset number of frame exposed conductors; The frame exposed conductor of the first lead frame and the frame exposed conductor of the second lead frame extend to the outside of the package, for soldering the digital isolator to a printed circuit board; The longitudinal height of the first base island is smaller than the longitudinal height of the second base island, and the first base island and the second base island overlap in the longitudinal direction, and the upper surface of the first base island reaches The lower surface of the second base island is provided with a preset height difference; The first integrated circuit is fixed on the upper surface of the first base island, and the second integrated circuit is fixed on the lower surface of the second base island; The first integrated circuit is configured with a first coil, the second integrated circuit is configured with a second coil, and the longitudinal projections of the first coil and the second coil overlap according to a preset area; The first integrated circuit and the second integrated circuit are used to control the first coil and the second coil respectively, so as to control signal transmission between the first coil and the second coil. 2. The digital isolator according to claim 1, wherein the first integrated circuit is arranged on a first chip, and is fixed on the upper surface of the first base island through the first chip; The second integrated circuit is arranged on the second chip, and fixed on the lower surface of the second base island through the second chip. 3. The digital isolator according to claim 2, wherein the first coil is disposed on the first chip, and the second coil is disposed on the second chip. 4. The digital isolator according to claim 2, wherein the first coil is fixed on the first coil chip, and is fixed on the upper surface of the first base island through the first coil chip; The second coil is fixed on the second coil chip, and fixed on the lower surface of the second base island through the second coil chip. 5. The digital isolator according to claim 1, wherein the upper surface of the first integrated circuit faces the lower surface of the second base island; The upper surface of the second integrated circuit faces the upper surface of the first base island; The first base island includes at least one set of first bonding wires for forming an electrical coupling between pads on the upper surface of the first integrated circuit and the first lead frame; The second base island includes at least one set of second bonding wires for forming electrical coupling between pads on the upper surface of the second integrated circuit and the second lead frame. 6. The digital isolator according to claim 4, wherein the first chip forms an electrical coupling with the first coil chip through a third bonding wire; The second chip forms an electrical coupling with the second coil chip through a fourth bonding wire. 7. The digital isolator according to claim 1, wherein the preset height difference between the upper surface of the first base island and the lower surface of the second base island is expressed as: H=T1+T2+Ts; Wherein, T1 represents the thickness of the first integrated circuit, T2 represents the thickness of the second integrated circuit, and Ts represents a preset safety distance. 8. The digital isolator according to claim 7, wherein the range of the safety distance includes: 100um-1000um. 9. The digital isolator according to claim 2, wherein the area of the first base island is larger than the area of the first chip; The area of the second base island is larger than the area of the second chip; The longitudinal projections of the first base island and the second base island overlap; The longitudinal projections of the first chip and the second chip overlap. 10. The digital isolator according to claim 1, wherein the first coil and the second coil are helical coils, and the centers of the first coil and the second coil are longitudinally opposite allow; The area enclosed by the projected outer boundary of the first coil partially overlaps with the area enclosed by the projected outer boundary of the second coil, and the partially overlapped area accounts for an area enclosed by the projected outer boundary of the first coil that is larger than the preset area. The area threshold value, and the partially overlapped area accounts for an area surrounded by the projected outer boundary of the second coil that is greater than the preset area threshold value. 11. The digital isolator of claim 10, wherein the area threshold is at least 40%. 12. The digital isolator according to claim 1, wherein the number of the first integrated circuits on the first base island is multiple; the second integrated circuit on the second base island There are multiple circuits; Each of the first integrated circuits is configured with one of the first coils, and each of the second integrated circuits is configured with one of the second coils. 13. The digital isolator according to claim 1, wherein the first integrated circuit comprises an encoding circuit and a coil driver connected in sequence, and the coil driver is also connected to the first coil; Wherein, the encoding circuit is used to receive an input signal, and the coil driver is used to drive the first coil to generate a magnetic field signal between the first coil and the second coil according to the input signal; The second integrated circuit includes a decoding circuit and a coil receiver connected in sequence; the coil receiver is connected to the second coil; Wherein, the coil receiver is used to receive the magnetic field signal and recover the magnetic field signal into a digital signal, and the decoding circuit is used to transmit the digital signal. 14. The digital isolator according to claim 1, wherein the first integrated circuit comprises a first coil driver and a first coil signal receiver; The first coil driver is connected to the first coil, and the first coil signal receiver is also connected to the first coil; The second integrated circuit is provided with a second coil driver and a second coil signal receiver, the second coil driver is connected to the second coil, and the coil signal receiver is also connected to the second coil; The first integrated circuit controls the enable state of the first coil driver and the first coil signal receiver through a preset state level; the second integrated circuit controls the enable state through a preset state level the enable state of the second coil driver and the second coil signal receiver, so as to realize bidirectional transmission through the digital isolator; The state level of the first integrated circuit alternates between a first coil driver enable state and a first coil signal receiver enable state; The state level of the second integrated circuit alternates between a second coil driver enabled state and a second coil signal receiver enabled state. 15. The digital isolator according to claim 14, wherein the first coil comprises a first winding and a second winding; The first coil driver is connected to the first winding, and the first coil signal receiver is connected to the second winding; The second coil includes a third winding and a fourth winding; The second coil driver is connected to the third winding, and the second coil signal receiver is connected to the fourth winding. 16. The digital isolator according to claim 15, wherein the inductance value of the fourth winding is greater than the inductance value of the first winding; The inductance value of the second winding is greater than the inductance value of the third winding. 17. The digital isolator according to claim 15, wherein the first winding and the second winding are provided with preset overlapping routing areas; The third winding and the fourth winding are provided with preset overlapping routing areas. 18. The digital isolator according to claim 17, wherein the first winding and the second winding are spiral coils, and at least a part of the second winding is located between the first winding and the The inner side of the preset overlapping routing area of the second winding; The third winding and the fourth winding are also helical coils, and at least a part of the fourth winding is located inside a preset overlapping wiring area of the third winding and the fourth winding. 19. The digital isolator according to claim 13, wherein the first integrated circuit further comprises a first signal conversion module; The first signal conversion module includes a multi-channel input interface, and the output end of the first signal conversion module is connected to the encoding circuit; The second integrated circuit also includes a second signal conversion module; The second signal conversion module includes a multi-channel output interface, and the input end of the second signal conversion module is connected to the decoding circuit; The first signal conversion module is used to convert multiple input signals into serial signals and transmit them to the second integrated circuit; The decoding circuit of the second integrated circuit is used to decode the serial signal, and recover and output the serial signal through the second signal conversion module. 20. The digital isolator according to claim 14, wherein the first integrated circuit includes a first signal conversion module connected to the first coil driver, and a first signal conversion module connected to the first coil signal receiver The second signal conversion module; The second integrated circuit includes a third signal conversion module connected to the second coil driver, and a fourth signal conversion module connected to the second coil signal receiver; Wherein, the first signal conversion module corresponds to the fourth signal conversion module, and the first signal conversion module is used to convert multiple input signals of the first integrated circuit into serial signals and transmit them to the The second integrated circuit; the decoding circuit of the second integrated circuit is used to decode the serial signal, and recover and output the serial signal through the fourth signal conversion module; The second signal conversion module corresponds to the third signal conversion module, and the third signal conversion module is used to convert the multiple input signals of the second integrated circuit into serial signals and transmit them to the first Integrated circuit; the decoding circuit of the first integrated circuit is used to decode the serial signal, and restore and output the serial signal through the third signal conversion module, so as to realize the digital isolator two-way transmission. 21. An electronic device, characterized in that the electronic device is configured with the digital isolator according to any one of claims 1-20.

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