CN116108803B - Method and apparatus for generating an irregular clock signal - Google Patents
Method and apparatus for generating an irregular clock signal Download PDFInfo
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- CN116108803B CN116108803B CN202310386979.XA CN202310386979A CN116108803B CN 116108803 B CN116108803 B CN 116108803B CN 202310386979 A CN202310386979 A CN 202310386979A CN 116108803 B CN116108803 B CN 116108803B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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Abstract
The application relates to the technical field of digital verification, and discloses a method and a device for generating an irregular clock signal, wherein the method comprises the following steps: determining a signal unconventional type according to data information of a clock parameter signal in a simulation process in response to a request for generating an unconventional clock signal; determining a number of signal cycles that the non-conventional clock signal needs to last; and shifting or closing the conventional clock signal in the simulation process according to the signal unconventional type, so as to obtain the unconventional clock signal in a time period corresponding to the signal cycle number. The method and the device can realize the abnormal response situation which is covered in the circuit to be tested and is caused by the non-ideal clock signal, and realize the clock signal generation which is more close to the actual use situation.
Description
Technical Field
The present application relates to the field of digital authentication technology, for example, to a method and apparatus for generating an irregular clock signal.
Background
At present, the development trend of integrated circuits is that the design scale is larger and the complexity is higher, so that the cost of the current chip is increased, and therefore, the verification of the circuit function performance is more important. Meanwhile, with the continuous perfection of the circuit function, the variety and the number of test excitation sent to the circuit are increased, the verification process is more complicated, and the working scene of the circuit is more.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
digital verification today is mostly based on general verification methodologies (Universal Verification Methodology, UVM) to build a verification platform through which test stimuli are sent to the circuit under test. In the verification process of the circuit to be tested, a clock signal is firstly provided for the circuit to be tested, and all operations in the circuit to be tested need to work based on the polarity of the clock signal. However, the verification platform generally only provides an ideal clock signal, so that abnormal response conditions caused by non-ideal clock signals inside the circuit to be tested cannot be covered, and it is difficult to fit actual use conditions.
It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the disclosure provides a method and a device for generating an irregular clock signal, a digital control logic verification platform and a storage medium, so as to generate the clock signal which is more suitable for actual use conditions in the digital verification process.
In some embodiments, the method for generating an irregular clock signal comprises:
determining a signal unconventional type according to data information of a clock parameter signal in a simulation process in response to a request for generating an unconventional clock signal;
determining a number of signal cycles that the non-conventional clock signal needs to last;
and shifting or closing the conventional clock signal in the simulation process according to the signal unconventional type, so as to obtain the unconventional clock signal in a time period corresponding to the signal cycle number.
Optionally, the determining the signal unconventional type according to the data information of the clock parameter signal in the simulation process includes:
acquiring bit values in data information of a clock parameter signal;
determining the signal unconventional type according to the bit value of the clock parameter signal;
wherein the signal unconventional types include an ideal signal, an offset signal, and a stop signal.
Optionally, the determining the signal unconventional type according to the bit value of the clock parameter signal includes:
determining the signal unconventional type to produce a normal ideal signal in the case of a first data combination of bit values;
determining the signal unconventional type to produce an offset signal comprising a high level in the case of a second data combination of bit values;
determining the signal unconventional type to produce an offset signal comprising a low level in the case of a third data combination of bit values;
in the case where the bit value is the fourth data combination, the signal unconventional type is determined to be a stop signal that generates an abnormal stop of the clock.
Optionally, the determining the number of signal cycles that the irregular clock signal needs to last includes:
the random generation of the non-conventional clock signal requires a continuous number of signal cycles; or,
the number of signal cycles that the irregular clock signal needs to last is preset, and the irregular clock signal is transmitted at a designated time point.
Optionally, the method further comprises:
setting a time delay variable in each clock cycle in the signal cycle number, so that the duration of the current clock cycle becomes the sum of the clock cycle and the time delay variable;
wherein the range of the time delay variable is 0 to T, and T is the duration of a single clock cycle.
Optionally, the shifting the conventional clock signal in the simulation process according to the signal unconventional type includes:
delaying the rising edge or the falling edge of the conventional clock signal according to the time delay variable serving as an offset at the moment of the rising edge or the falling edge of the conventional clock signal;
and after the delay is finished, carrying out pull-down or pull-up operation on the conventional clock signal in the driving assembly module.
Optionally, the method further comprises:
setting an abnormal stop variable according to a system reference clock signal in the driving assembly module;
controlling the probability that the abnormal stop variable is 0 or valid data;
and under the condition that the abnormal stop variable is effective data, closing a clock enabling switch signal corresponding to a conventional clock signal in the driving component module according to a preset or randomly set signal cycle number.
In some embodiments, the means for generating an irregular clock signal comprises:
a request response module configured to determine a signal unconventional type from data information of the clock parameter signal in the simulation process in response to a request to generate the unconventional clock signal;
a cycle number module configured to determine a number of signal cycles that the non-conventional clock signal needs to last;
and the signal shifting module is configured to shift or close the conventional clock signal in the simulation process according to the signal unconventional type, so that the unconventional clock signal is obtained in a time period corresponding to the signal cycle number.
In some embodiments, the digital control logic verification platform comprises a test top layer module and a drive assembly module in which a processor and a memory storing program instructions are disposed, the processor being configured, when running the program instructions, to perform a method for generating an irregular clock signal as described herein.
In some embodiments, the storage medium stores program instructions that, when executed, perform a method for generating an irregular clock signal as described herein.
The method and the device for generating the irregular clock signal, the digital control logic verification platform and the storage medium provided by the embodiment of the disclosure can realize the following technical effects:
according to the clock parameter signal generation method and device, the driving component offsets or closes the conventional clock signal in the simulation process according to the signal unconventional type and the signal cycle number corresponding to the clock parameter signal, so that the unconventional clock signal is obtained in the time period corresponding to the signal cycle number and is used by the circuit to be tested, the abnormal response situation, which is covered inside the circuit to be tested and caused by the non-ideal clock signal, is achieved, and the clock signal generation which is closer to the actual use situation is achieved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a schematic diagram of a system environment of a digital control logic verification platform provided by an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a method for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another method for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another method for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of another method for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 6 is a schematic illustration of one particular application provided by an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of another specific application provided by an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of another method for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of another method for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 10 is a schematic diagram of an apparatus for generating an unconventional clock signal provided by an embodiment of the present disclosure;
FIG. 11 is a block diagram of a digital control logic verification platform provided by an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.
In connection with fig. 1, in the process of verifying a circuit to be tested, a digital control logic verification platform constructed according to a UVM verification methodology sets a specific clock frequency according to a pre-designed working frequency index, for example, a system clock is defined in a test top module of the verification platform for instantiating the circuit to be tested and the verification platform, and the system clock is generally defined as a turnover normal time signal in an ideal state and is used for a subsequent excitation driving component and the like. This system clock may be considered to be idealized and fixed in period, so it lacks some randomness and may cover abnormal or boundary scenarios that are not verified.
The present application is actually applied to digital control logic verification of an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) chip, and also can be applied to digital control logic verification of a flash memory chip, and in the actual application process, different chip application environments and application temperatures may cause errors in different situations of internal clock signals, and clock signals generated in an actual crystal oscillator generally include clock offset and clock jitter, and even clock burrs. For this reason, the present application is intended to generate an unconventional clock signal to be provided to the circuit under test for use, so that the verification process is more realistic.
As shown in connection with fig. 2, an embodiment of the present disclosure provides a method for generating an irregular clock signal, comprising:
step 201: in response to a request to generate an unconventional clock signal, a signal unconventional type is determined from data information of a clock parameter signal during the simulation.
Step 202: the number of signal cycles that the non-conventional clock signal needs to last is determined.
Step 203: and shifting or closing the conventional clock signal in the simulation process according to the signal unconventional type, so as to obtain the unconventional clock signal in a time period corresponding to the signal cycle number.
In the embodiment of the application, as shown in fig. 1, the driving module Driver in the UVM verification platform sends clock signals, driving instructions and the like to the circuit to be tested, and in the verification process, the UVM verification platform uses the driving function of the driving module Driver to give the clock signals in different forms. Specifically, in the Driver module Driver, an enable switch signal defining the system clock (i.e., the normal clock signal) is a clock enable switch signal, which is turned on in a default state, and an on enable signal abnormal clk enable defining the non-normal clock signal is turned off in a default state.
In the simulation process, the UVM verification platform judges whether a request for adding an unconventional clock signal exists in excitation, and if an instruction for adding the unconventional clock signal is not detected, the UVM verification platform directly outputs a clock signal in an ideal state; if a request for adding an irregular clock signal is received in the excitation, the request for generating the irregular clock signal is responded, the signal irregular type and the signal cycle number are determined according to the data information of the clock parameter signal in the simulation process, the regular clock signal in the simulation process is shifted or closed according to the signal irregular type, and finally the irregular clock signal is obtained in a time period corresponding to the output signal cycle number.
By adopting the method for generating the irregular clock signal provided by the embodiment of the disclosure, the driving component offsets or closes the regular clock signal in the simulation process according to the signal irregular type and the signal cycle number corresponding to the clock parameter signal by generating the clock parameter signal, so that the irregular clock signal is obtained in the time period corresponding to the signal cycle number and is used by the circuit to be tested, thereby realizing the abnormal response condition covered inside the circuit to be tested and caused by the non-ideal clock signal, and realizing the generation of the clock signal which is more close to the actual use condition.
Optionally, as shown in connection with fig. 3, the determining the signal unconventional type according to the data information of the clock parameter signal in the simulation process includes:
step 301: and acquiring bit values in the data information of the clock parameter signals.
Step 302: a signal unconventional type is determined based on the bit value of the clock parameter signal, wherein the signal unconventional type includes an ideal signal, an offset signal, and a stop signal.
In the embodiment of the present application, as shown in fig. 4, the UVM verification platform of the present application obtains, through the Driver of the driving component module, a bit value in data information of the clock parameter signal, and then determines, according to the bit value of the clock parameter signal, a specific signal unconventional type, including an ideal signal, an offset signal, and a stop signal.
Optionally, as shown in fig. 5, the determining the signal unconventional type according to the bit value of the clock parameter signal includes:
step 501: in the case of a first data combination of bit values, the signal unconventionalization type is determined to produce a normal, ideal signal.
Step 502: in the case of a second data combination of bit values, the signal unconventionalization type is determined to produce an offset signal containing a high level.
Step 503: in the case of a third data combination of bit values, the signal unconventionalization type is determined to produce an offset signal containing a low level.
Step 504: in the case where the bit value is the fourth data combination, the signal unconventional type is determined to be a stop signal that generates an abnormal stop of the clock.
In an embodiment of the present application, the clock parameter signal may be a clock parameter signal [1:0] having a bit width of two bits, wherein the bit values of the first data combination to the fourth data combination may be:
bit [0:0]: generating a normal clock signal;
bit [0:1]: generating an irregular clock signal including a high level wide;
bit [1:0]: generating an irregular clock signal comprising a low level and a wide level;
bit [1:1]: an abnormally stopped non-conventional clock signal is generated.
In practical application, the clock parameter signal and the number of signal cycles are transmitted to the Driver module, and when the bit value of the clock parameter signal is [0:1], a clock sequence with a wider high level is generated by combining with the number of unconventional clock signal cycles, as shown by a delay T1 in FIG. 6, and the sequence is transmitted to the bus;
in practical application, the clock parameter signal and the number of signal cycles are transmitted to the Driver module, and when the bit value of the clock parameter signal is [1:0], a clock sequence with a low level and a wider range is generated by combining with the number of unconventional clock signal cycles, as shown by a delay T2 in FIG. 6, and the sequence is transmitted to the bus;
in practical application, the clock parameter signal and the number of periods of the unconventional clock signal are transmitted to the Driver module Driver, when the bit value of the clock parameter signal is [1:1], the unconventional clock signal periods are combined to generate an abnormally stopped clock sequence, as shown by an abnormally stopped unconventional clock signal clk_stop in fig. 7, and the sequence is transmitted to the bus;
in practical applications, the clock parameter signal and the number of periods of the unconventional clock signal are transmitted to the Driver module Driver, and when the bit value of the clock parameter signal is [0:0], a clock sequence in an ideal state is generated and transmitted to the bus.
Therefore, the method and the device can generate at least three types of unconventional clock signals, so that the method and the device are close to the actual working environment of the chip as much as possible, and the authenticity and the reliability of the simulation test are improved.
Optionally, the determining the number of signal cycles that the irregular clock signal needs to last includes:
the random generation of the non-conventional clock signal requires a continuous number of signal cycles; or,
the number of signal cycles that the irregular clock signal needs to last is preset, and the irregular clock signal is transmitted at a designated time point.
In the embodiment of the application, the number of signal cycles that the unconventional clock signal needs to last can be randomly generated, or the number of signal cycles added to the unconventional clock can be set to be a known number, and the signal cycles can be designated to be sent at a specific time point, for example, during the period of sending an instruction to a circuit to be tested by excitation, so that a random scene in a real scene can be simulated, and an unconventional verification point can be artificially added at the specific time point. In the actual simulation process, the waveform diagram is shown in fig. 6, and it can be obviously seen that the period T of the conventional clock signal is multiple of the refclk of the system reference clock signal, and the delay T1 is not equal to the period T and the delay T2 is not equal to the period T.
Optionally, in an embodiment of the present application, a time delay variable is set in each of the number of signal cycles such that the duration of the current clock cycle becomes the sum of the clock cycle and the time delay variable.
Wherein the range of the time delay variable is 0 to T, and T is the duration of a single clock cycle.
In the embodiment of the application, the time delay variable is added in each clock cycle in the signal cycle number of the unconventional clock signal, a certain probability is set so that the time delay variable can be randomly 0, thereby realizing that part of cycles contain clock jitter and the rest of cycles are normal clock signals, and the clock signals with different qualities can be sent by controlling the range and probability of the value of the time delay variable.
Thus, since the ideal period of the clock period is fixed, if the period is defined as T 0 The clock signal is inverted every time T time passes, the time delay variable is added to change the duration of the current clock period into the sum of the clock period and the time delay variable, and the time delay variable is required to meet the precision, i.e. cannot deviate from T greatly 0 Otherwise, the clock signal does not accord with the actual clock signal.
Optionally, as shown in connection with fig. 8, the shifting the conventional clock signal in the simulation process according to the signal unconventional type includes:
step 801: and delaying the rising edge or the falling edge of the conventional clock signal according to the time delay variable serving as an offset at the moment of the rising edge or the falling edge of the conventional clock signal.
Step 802: and after the delay is finished, carrying out pull-down or pull-up operation on the conventional clock signal in the driving assembly module.
In embodiments of the present application, a system is typically defined in the test top module of the test platform during simulationThe system reference clock signal refclk has a period T 0 This is the clock signal in the ideal state. In a driving component module Driver of the test platform, a time delay variable with precision conforming to a clock period parameter is defined by using a random function, a driving capability of the driving component module Driver is utilized, a time delay variable is added at a moment point of a rising edge or a falling edge of a system reference clock signal refclk as an offset of a clock edge, after delay, an internal clock clk_drv of the driving component module Driver is correspondingly pulled down or pulled up, and an unconventional clock signal is sent to a virtual interface for use by a circuit to be tested.
Optionally, as shown in conjunction with fig. 9, an embodiment of the disclosure provides a method for generating an irregular clock signal, further comprising:
step 901: an abnormal stop variable is set according to a system reference clock signal inside the driving assembly module.
Step 902: the probability that the abnormal stop variable is 0 or valid data is controlled.
Step 903: and under the condition that the abnormal stop variable is effective data, closing a clock enabling switch signal corresponding to a conventional clock signal in the driving component module according to a preset or randomly set signal cycle number.
In the embodiment of the application, in the simulation process, the clock enabling switch signal corresponding to the conventional clock signal in the driving component module is defaulted to be always on, and when the clock enabling switch signal is valid, the conventional clock signal can be normally sent to the virtual interface to ensure that the circuit to be tested can normally work according to the clock frequency. In the simulation process, an abnormal stop variable can be set according to a system reference clock signal refclk in a test top module, and under the condition that the abnormal stop variable is effective data, a clock enabling switch signal corresponding to a conventional clock signal is pulled down, and meanwhile, the probability that the abnormal stop variable is 0 or effective data is controlled, so that the period length of closing the conventional clock signal can be given, and the conventional clock signal can be closed at random periods. In this way, the clock can be stopped abnormally at any moment of sending the excitation, so as to cover more verification scenes, and the waveform diagram actually used is shown in fig. 7.
As shown in connection with fig. 10, an embodiment of the present disclosure provides an apparatus for generating an irregular clock signal, comprising:
a request response module 101 configured to determine a signal unconventional type from data information of the clock parameter signal in the simulation process in response to a request to generate the unconventional clock signal;
a cycle number module 102 configured to determine a number of signal cycles that the non-conventional clock signal needs to last;
the signal shifting module 103 is configured to shift or turn off the conventional clock signal in the simulation process according to the signal unconventional type, so as to obtain the unconventional clock signal in a period corresponding to the signal period number.
By adopting the device for generating the irregular clock signal provided by the embodiment of the disclosure, the driving component offsets or closes the regular clock signal in the simulation process according to the signal irregular type and the signal cycle number corresponding to the clock parameter signal by generating the clock parameter signal, so that the irregular clock signal is obtained in the time period corresponding to the signal cycle number and is used by the circuit to be tested, thereby realizing the abnormal response condition covered inside the circuit to be tested and caused by the non-ideal clock signal, and realizing the generation of the clock signal which is more close to the actual use condition.
As shown in connection with fig. 11, an embodiment of the present disclosure provides a digital control logic verification platform, including a test top layer module and a driver component module in which a processor (processor) 110 and a memory (memory) 111 storing program instructions are provided. Optionally, the apparatus may further comprise a communication interface (Communication Interface) 112 and a bus 113. The processor 110, the communication interface 112, and the memory 111 may communicate with each other via the bus 113. The communication interface 112 may be used for information transfer. The processor 110 may invoke logic instructions in the memory 111 to perform the method of generating the non-conventional clock signal of the above-described embodiments.
Further, the logic instructions in the memory 111 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.
The memory 111 serves as a computer readable storage medium, and may be used to store a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 110 performs functional applications as well as data processing, i.e. implements the method for generating an irregular clock signal in the above-described embodiments, by running program instructions/modules stored in the memory 111.
The memory 111 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 111 may include a high-speed random access memory, and may also include a nonvolatile memory.
Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for generating an irregular clock signal.
The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.
Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium including: a plurality of media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or a transitory storage medium.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.
Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (5)
1. A method for generating an irregular clock signal, comprising:
determining a signal unconventional type according to data information of a clock parameter signal in a simulation process in response to a request for generating an unconventional clock signal;
determining a number of signal cycles that the non-conventional clock signal needs to last;
shifting or closing a conventional clock signal in the simulation process according to the signal unconventional type, so as to obtain an unconventional clock signal in a time period corresponding to the signal period number, wherein the unconventional clock signal comprises a high-level wider unconventional clock signal and a low-level wider unconventional clock signal;
wherein, the determining the signal unconventional type according to the data information of the clock parameter signal in the simulation process comprises the following steps:
acquiring bit values in data information of a clock parameter signal;
determining the signal unconventional type according to the bit value of the clock parameter signal;
wherein the signal unconventional types include an ideal signal, an offset signal, and a stop signal;
wherein, the determining the signal unconventional type according to the bit value of the clock parameter signal comprises:
determining that the signal unconventional type is generating a normal ideal signal in the case that the Bit value is a first data combination, wherein the first data combination is Bit [0:0], which indicates that a normal clock signal is generated;
determining the signal unconventionalization type to generate an offset signal comprising a high level in the case of a second combination of Bit values, wherein the second combination of data is Bit [0:1], indicating the generation of an unconventional clock signal comprising a wider high level;
determining the signal unconventional type to generate an offset signal comprising a low level in the case of a third data combination of Bit values, wherein the third data combination is Bit [1:0], indicating that an unconventional clock signal comprising a wider low level is generated;
determining that the signal unconventional type is a stop signal generating an abnormal stop of the clock under the condition that the Bit value is a fourth data combination, wherein the fourth data combination is Bit [1:1], which represents an unconventional clock generating the abnormal stop;
wherein said determining the number of signal cycles that the non-conventional clock signal needs to last comprises:
the random generation of the non-conventional clock signal requires a continuous number of signal cycles; or,
presetting a signal cycle number which needs to be sustained by an irregular clock signal, and transmitting at a designated moment;
wherein the method further comprises:
setting a time delay variable in each clock cycle in the signal cycle number, so that the duration of the current clock cycle becomes the sum of the clock cycle and the time delay variable; the value range of the time delay variable is 0 to T, the T is the duration of a single clock period, the time delay variable has the probability of being 0 randomly so as to realize that part of periods contain clock jitter and the rest of periods are normal clock signals, and the clock signals with different qualities can be transmitted by controlling the value of the time delay variable and the probability of being 0 randomly;
the method for shifting the conventional clock signal in the simulation process according to the signal unconventional type comprises the following steps:
delaying the rising edge or the falling edge of the conventional clock signal according to the time delay variable serving as an offset at the moment of the rising edge or the falling edge of the conventional clock signal;
and after the delay is finished, carrying out pull-down or pull-up operation on the conventional clock signal in the driving assembly module.
2. The method as recited in claim 1, further comprising:
setting an abnormal stop variable according to a system reference clock signal in the driving assembly module;
controlling the probability that the abnormal stop variable is 0 or valid data;
and under the condition that the abnormal stop variable is effective data, closing a clock enabling switch signal corresponding to a conventional clock signal in the driving component module according to a preset or randomly set signal cycle number.
3. An apparatus for generating an irregular clock signal, comprising:
a request response module configured to determine a signal unconventional type from data information of the clock parameter signal in the simulation process in response to a request to generate the unconventional clock signal;
a cycle number module configured to determine a number of signal cycles that the non-conventional clock signal needs to last;
the signal offset module is configured to offset or close a conventional clock signal in the simulation process according to the signal unconventional type so as to obtain the unconventional clock signal in a time period corresponding to the signal cycle number, wherein the unconventional clock signal comprises a high-level wider unconventional clock signal and a low-level wider unconventional clock signal;
wherein, the determining the signal unconventional type according to the data information of the clock parameter signal in the simulation process comprises the following steps:
acquiring bit values in data information of a clock parameter signal;
determining the signal unconventional type according to the bit value of the clock parameter signal;
wherein the signal unconventional types include an ideal signal, an offset signal, and a stop signal;
wherein, the determining the signal unconventional type according to the bit value of the clock parameter signal comprises:
determining that the signal unconventional type is generating a normal ideal signal in the case that the Bit value is a first data combination, wherein the first data combination is Bit [0:0], which indicates that a normal clock signal is generated;
determining the signal unconventionalization type to generate an offset signal comprising a high level in the case of a second combination of Bit values, wherein the second combination of data is Bit [0:1], indicating the generation of an unconventional clock signal comprising a wider high level;
determining the signal unconventional type to generate an offset signal comprising a low level in the case of a third data combination of Bit values, wherein the third data combination is Bit [1:0], indicating that an unconventional clock signal comprising a wider low level is generated;
determining that the signal unconventional type is a stop signal generating an abnormal stop of the clock under the condition that the Bit value is a fourth data combination, wherein the fourth data combination is Bit [1:1], which represents an unconventional clock generating the abnormal stop;
wherein said determining the number of signal cycles that the non-conventional clock signal needs to last comprises:
the random generation of the non-conventional clock signal requires a continuous number of signal cycles; or,
presetting a signal cycle number which needs to be sustained by an irregular clock signal, and transmitting at a designated moment;
setting a time delay variable in each clock cycle in the signal cycle number, so that the duration of the current clock cycle becomes the sum of the clock cycle and the time delay variable; the value range of the time delay variable is 0 to T, the T is the duration of a single clock period, the time delay variable has the probability of being 0 randomly so as to realize that part of periods contain clock jitter and the rest of periods are normal clock signals, and the clock signals with different qualities can be transmitted by controlling the value of the time delay variable and the probability of being 0 randomly;
the method for shifting the conventional clock signal in the simulation process according to the signal unconventional type comprises the following steps:
delaying the rising edge or the falling edge of the conventional clock signal according to the time delay variable serving as an offset at the moment of the rising edge or the falling edge of the conventional clock signal;
and after the delay is finished, carrying out pull-down or pull-up operation on the conventional clock signal in the driving assembly module.
4. A digital control logic verification platform comprising a test top layer module and a drive assembly module in which a processor and a memory storing program instructions are provided, characterized in that the processor is configured to perform the method for generating an irregular clock signal as claimed in claim 1 or 2 when running the program instructions.
5. A storage medium storing program instructions which, when executed, perform the method for generating an irregular clock signal according to claim 1 or 2.
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