CN116107415A

CN116107415A - Processor circuit, power supply control method and terminal equipment

Info

Publication number: CN116107415A
Application number: CN202111333114.4A
Authority: CN
Inventors: 史岩松
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2021-11-11
Filing date: 2021-11-11
Publication date: 2023-05-12
Also published as: WO2023082723A1

Abstract

The application relates to a power supply technology and provides a processor circuit, a power supply control method and terminal equipment, wherein the processor circuit comprises a processor, and the processor is provided with a control logic module and a plurality of cores; different cores in the multiple cores are respectively powered by different power supply modules; the control logic module is respectively connected with the multiple cores and the multiple power supply modules and is used for outputting a voltage regulating signal according to the frequency of a target core so that the power supply module corresponding to the target core can regulate the power supply voltage, and the target core is at least one core of the multiple cores. An independent power supply module is arranged for each core, power can be supplied according to the actual working condition of each core, the maximum power supply voltage is not required to be provided for each core to supply power for all cores simultaneously, and the independent power supply enables the cores which are idle or only need low-load operation to stop power supply or low-voltage operation, so that unnecessary power consumption can be avoided.

Description

Processor circuit, power supply control method and terminal equipment

Technical Field

The application belongs to the technical field of power supplies, and particularly relates to a processor circuit, a power supply control method and terminal equipment.

Background

The number of cores of a processor means that there are several cores physically, i.e. in hardware. For example, a dual core may include 2 relatively independent sets of processor core units, and a quad core may include 4 relatively independent sets of processor core units. In an example of an 8-core processor, the internal memory includes 4 large cores and 4 small cores, wherein the concept of small cores is introduced to balance the power consumption of the system. For example, when running on a hand tour where performance is required, the large core can run at high frequency to reach the highest performance, and the small core is idle; when only social chat software is operated, only a small core can be started in the internet surfing process, and a large core is in an idle state, so that the optimal energy efficiency ratio is achieved.

However, the power supply of each core in the current processor is affected by the core with the maximum value of the power supply voltage, which results in that when only part of cores are operated, the same voltage is supplied to all cores, and the power supply voltage is increased unnecessarily compared with other cores.

Disclosure of Invention

The invention aims to provide a processor circuit, a power supply control method and terminal equipment, and aims to solve the problem that power consumption is affected due to the fact that all cores of a multi-core processor need to be simultaneously powered.

A first aspect of embodiments of the present application provides a processor circuit comprising

The processor is provided with a control logic module and a plurality of kernels;

different cores in the multiple cores are respectively powered by different power supply modules; the control logic module is respectively connected with the multiple cores and the multiple power supply modules and is used for outputting a voltage regulating signal according to the frequency of a target core so that the power supply module corresponding to the target core can regulate the power supply voltage, and the target core is at least one core of the multiple cores.

In an alternative embodiment, the power supply module includes a power control module and a voltage conversion module;

the power supply control module is respectively connected with the control logic module and the voltage conversion module and is used for receiving the voltage regulation signal output by the control logic module so as to control the voltage conversion module to regulate the power supply voltage output to the target kernel;

the voltage conversion module is connected with the target kernel and used for adjusting the power supply voltage output to the target kernel.

In an alternative embodiment, the system further comprises a power management module;

the power management module is respectively connected with the control logic module and each power control module, and is used for receiving the voltage regulation signals output by the control logic module and controlling at least one power control module to work according to the voltage regulation signals.

In an alternative embodiment, the control logic module is further configured with the following functions: and adjusting the frequency of the target kernel according to the load state of the target kernel.

In an alternative embodiment, the adjusting the frequency of the target kernel according to the load state of the target kernel includes:

determining an average operating current of the target core over a period of time;

task scheduling among cores is carried out according to the average working current of the target cores in the period of time;

and adjusting the frequency of the target kernel according to the task scheduling result among the kernels.

In an alternative embodiment, the device further comprises a current detection module, wherein the current detection module is connected with each power supply module and is used for detecting the output current of each power supply module;

accordingly, the determining the average working current of the target kernel in a period of time includes:

the control logic module obtains the output current of each power supply module from the current detection module, and calculates the average working current of the target kernel correspondingly connected with each power supply module in a period of time according to the output current of each power supply module; or,

The power supply control module of the power supply module obtains the output current of the power supply module from the current detection module, calculates the average working current of the target kernel correspondingly connected with the power supply module in a period of time according to the output current of the power supply module, and transmits the average working current to the control logic module.

In an alternative embodiment, the current detection module includes a plurality of detection branches, each detection branch is connected to each power supply module in a one-to-one correspondence, and each detection branch is used for detecting the output current of the power supply module correspondingly connected to the detection branch.

In an alternative embodiment, the inter-core task scheduling includes scheduling tasks of a first target core to a second target core for execution;

the first target kernel is at least one kernel of a plurality of kernels, and after the task of the first target kernel is scheduled to be executed by the second target kernel, the average working current of the second target kernel in a preset time period is smaller than or equal to the full-load current of the second target kernel.

The second aspect of the embodiment of the present application further provides a power supply control method, which is applied to a power supply module for supplying power to a processor, where the processor is provided with a control logic module and a plurality of cores, different cores in the plurality of cores are powered by different power supply modules, and the power supply control method includes:

Providing a power supply voltage for each core connected with the power supply module;

and adjusting the power supply voltage provided for the target core according to the trigger caused by the frequency of the control logic module for adjusting the target core, wherein the target core is at least one core in a plurality of cores.

In an alternative embodiment, the triggering is caused by the control logic module adjusting the frequency of the target core according to the load state of the target core.

In an alternative embodiment, the power supply control method further includes:

and adjusting the frequency trigger of the target kernel according to the average working current of the target kernel in the period of time after task scheduling among kernels, and adjusting the power supply voltage provided for the target kernel.

In an alternative embodiment, the determining the average operating current of the target core over a period of time includes:

and calculating the average working current of the target kernel corresponding to the power supply module in a period of time according to the obtained output current of the power supply module.

In an alternative embodiment, the adjusting the supply voltage provided to the target core by the target core according to the trigger caused by the control logic module for adjusting the frequency of the target core includes:

receiving the corresponding voltage regulating signal output by the control logic module according to the frequency regulation of the target kernel;

and controlling a voltage conversion module of the power supply module to carry out voltage conversion according to the received voltage regulation signal so as to regulate the power supply voltage of the target kernel.

The third aspect of the embodiment of the present application further provides another power supply control method, applied to a processor provided with a plurality of cores, where different cores in the plurality of cores are powered by different power supply modules, where the power supply control method includes:

Acquiring the frequency of a target kernel in the process that the power supply module of the target kernel supplies power to the target kernel, wherein the target kernel is at least one kernel of a plurality of kernels;

and controlling the power supply module for supplying power to the target kernel to adjust the power supply voltage supplied to the target kernel according to the frequency of the target kernel.

In an optional embodiment, before the power supply module in the target kernel supplies power to the target kernel, the method further includes:

and adjusting the frequency of the target kernel according to the load state of the target kernel.

and adjusting the frequency of the target kernel related to the task scheduling among the kernels according to the task scheduling result among the kernels.

Calculating the average working current of the target cores corresponding to the power supply modules in a period of time according to the acquired output currents of the power supply modules; or,

and obtaining the average working current of each target kernel in a period of time from each power supply module, wherein the average working current of each target kernel in a period of time is calculated by the corresponding power supply module according to the output current of the power supply module detected by the current detection module.

In an alternative embodiment, the controlling the power supply module to supply power to the target core according to the frequency of the target core adjusts the power supply voltage provided to the target core, including:

Outputting a corresponding voltage regulating signal to a power supply control module of the power supply module for supplying power to the target core according to the frequency of the target core;

the voltage regulation signal is used for indicating the power supply control module to control and regulate the voltage conversion performed by the voltage conversion module of the power supply module so as to regulate the power supply voltage provided by the voltage conversion module to the target kernel.

A fourth aspect of the embodiments of the present application provides a terminal device comprising a processor circuit as described above.

A fifth aspect of the embodiments of the present application provides a terminal device comprising a processor and a computer program stored in and executable on the processor, characterized in that the processor implements the steps of the method as described above when executing the computer program.

A sixth aspect of the embodiments of the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps as described above.

Compared with the prior art, the embodiment of the application has the beneficial effects that: an independent power supply module is arranged for each core, power can be supplied according to the actual working condition of each core, the maximum power supply voltage is not required to be provided for each core to supply power for all cores simultaneously, and the independent power supply enables the cores which are idle or only need low-load operation to stop power supply or low-voltage operation, so that power consumption can be reduced.

Drawings

Fig. 1 is a schematic structural diagram of a processor circuit according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of a processor of the processor circuit shown in FIG. 1;

FIG. 3 is a schematic diagram of a power module of the processor circuit shown in FIG. 1;

FIG. 4 is a schematic diagram of a processor circuit according to a second embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a processor circuit according to a third embodiment of the present disclosure;

FIG. 6 is a schematic flow chart of a power supply control method according to one embodiment of the present disclosure;

fig. 7 is a schematic flow chart of voltage regulation in a power supply control method according to one embodiment of the present disclosure;

FIG. 8 is a schematic flow chart of voltage regulation in a power supply control method according to one embodiment of the present disclosure;

fig. 9 is a schematic flowchart of a power supply control method according to one embodiment of the present disclosure;

fig. 10 is a schematic flow chart of a power supply control method according to one embodiment of the present disclosure;

fig. 11 is a schematic flow chart of frequency adjustment in a power supply control method according to one embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" means two or more, and the meaning of "a number" means one or more, unless specifically defined otherwise.

Referring to fig. 1, a processor circuit applicable to a terminal device (such as a mobile phone, a tablet computer, a smart watch, a personal computer, etc.) provided in an embodiment of the first aspect of the present application includes a processor 100 provided with a control logic module 120 and a plurality of cores 110a to 110n, wherein different cores 110a to 110n in the plurality of cores 110a to 110n are powered by different power supply modules 200a to 200n, and the control logic module 120 is respectively connected to the plurality of cores 110a to 110n and the plurality of power supply modules 200a to 200n, and is configured to output a voltage adjustment signal according to a frequency of a target core, so that the power supply module 200a to 200n corresponding to the target core adjusts a power supply voltage, and the target core is at least one core in the plurality of cores 110a to 110 n.

In some alternative embodiments, the processor circuit includes a plurality of power modules 200 a-200 n, where the number of power modules 200 a-200 n is the same as the number of cores 110 a-110 n, and where the plurality of power modules 200 a-200 n may be integrated within the processor 100 or may be configured independently of the processor 100. In alternative embodiments, the plurality of power modules 200 a-200 n are in a mateable connection with the processor circuit; at this time, the plurality of power supply modules 200a to 200n are provided independently of the processor 100.

It is understood that the frequency of the cores 110 a-110 n represents the workload state. Thus, in various embodiments, each of the plurality of cores 110 a-110 n within processor 100 is controlled to follow changes in its frequency, powered at a corresponding voltage, such that not only asymmetric workloads may be performed on the plurality of cores 110 a-110 n to provide deterministic performance; the cores 110 a-110 n with low loads can also work at a lower frequency and supply power with lower voltage, and even the cores 110 a-110 n without operation tasks are stopped to be powered off, so that unnecessary loss is reduced.

Referring to fig. 2, the control logic module 120 of the processor 100 includes a non-core portion of the processor 100, such as a logic control module 122, a clock generation module 124 for providing frequencies, and a frequency modulation control module 126 for adjusting the operating frequencies of the cores 110 a-110 n, wherein the control logic module 120 can be specifically built by logic circuits. In other embodiments, the frequency adjustment of the target kernel may be a preset adjustment by an external instruction; the logic control module 122 may also adjust the frequency of the target core according to the load status of the target core. For determining the load state of the target kernel, the control logic module 120 may compare the task at the next time in the queue of the target kernel with the current or historical task, for example, the task same as the task at the next time, if not the same, the task may also be compared with the similar task, so as to estimate the load state of the target kernel at the next time when the task at the next time is about to be run.

The load status at the next moment may include idle, load shedding, and load increasing, and the logic control module 122 may control the fm control module 126 to provide a preset frequency to the target core according to the estimated current load status at the next moment or the current load status at the next moment, or may adjust the frequency, for example, stop the providing of the frequency (signal) to enable the target core to sleep (corresponding to idle), reduce the frequency (corresponding to load shedding), and increase the frequency (corresponding to load increasing).

The load state of the target core may be represented by its operating voltage or current, or operating frequency. The method can also be embodied on the type of the task currently executed by the target kernel, such as a game task operated by multiple image data, a shooting task with high load, an instant messaging task, a web browsing task and the like with low load.

In addition, while adjusting the frequency of the target core, the logic control module 122 outputs a voltage adjustment signal corresponding to the frequency according to the current or next frequency of the target core, and controls the corresponding power supply modules 200a to 200n supplying power to the target core to adjust the power supply voltage. Specifically, the logic control module 122 outputs corresponding voltage adjustment signals to the power supply modules 200a to 200n according to the frequency variation of the target core.

Referring to fig. 3, in some embodiments, each of the power supply modules 200 a-200 n includes a power control module 210 and a voltage conversion module 220, respectively. Each power control module 210 is connected to the control logic module 120 and each voltage conversion module 220, and is configured to receive a voltage adjustment signal output by the control logic module 120, so as to control the voltage conversion module 220 to adjust the power supply voltage VOUT output to the target core; each voltage conversion module 220 is connected to each core 110a to 110n for adjusting the supply voltage VOUT output to the target core.

It can be understood that the voltage adjustment signal carries a specific target voltage value, or the voltage adjustment signal carries a frequency of a target core, the power control module 210 can determine the target voltage value according to a pre-stored correspondence between the frequency and the target voltage value, and the power control module 210 will control the voltage of the voltage conversion module 220 according to the voltage adjustment signal to convert to obtain the supply voltage VOUT of the target voltage value. The power control module 210 may be a single-chip microcomputer based on an advanced reduced instruction set machine (Advanced RISC Machine, ARM), a micro-control unit (Microcontroller Unit, MCU), or the like.

In one example, assume that the process includes four kernels: the power supply control module 210 of the power supply module for supplying power to the core 1 receives a corresponding instruction and then controls the voltage conversion module 220 connected with the power supply control module to output 1.2V voltage to the core 1, wherein the power supply voltage required by the core 1 is 1.2V, and the power supply voltage required by the core 2-4 is 0.8V; after receiving the corresponding instruction, the power control module 210 of the power supply module for supplying power to the cores 2-4 controls the voltage conversion module 220 connected with the power control module to output 0.8V voltage to the cores 2-4.

Referring to fig. 4, the processor circuit further includes a Power Management module 150, where the Power Management module 150 may be a Power Management Integrated Circuit (PMIC), the Power Management module 150 is respectively connected to the control logic module 120 and the Power control module 210 in each of the Power supply modules 200a to 200n, and the Power Management module 150 is configured to receive a voltage adjustment signal output by the control logic module 120 and control operation of at least one Power control module 210 according to the voltage adjustment signal. In this embodiment, the power management module 150 is configured to control the plurality of power control modules 210 to control the corresponding voltage conversion modules 220 to regulate the power supply voltage VOUT. In other embodiments, if the serial port of the processor 100 is sufficient, the power management module 150 may be omitted to save cost, and a connected serial port is provided for each power control module 210 to transmit the voltage adjustment signal, as shown in fig. 1. It will be appreciated that providing the power management module 150 may save the serial port of the processor 100.

The voltage conversion module 220 may be a boost (boost) circuit, a buck (buck) circuit, or a buck-boost (boost-buck) circuit. With continued reference to fig. 3, in some embodiments, the voltage conversion module 220 is a voltage reduction circuit, and includes a half-bridge power portion formed by MOS transistors M1 and M2, and an energy storage filtering portion formed by an inductor L1 and a capacitor C1, where the voltage conversion module 220 mainly implements voltage conversion and power output to provide a supply voltage VOUT to the corresponding cores 110a to 110 n; specifically, the power control module 210 controls the switching frequency and the duty ratio of the MOS transistors M1 and M2 according to the voltage adjustment signal, the load, and the output (the supply voltage VOUT), and the output control signals h_drive and l_drive respectively to realize the adjustment of different supply voltages VOUT.

In addition, when the conventional processor performs kernel assignment on the linear task, the conventional processor has certain randomness, so that the full utilization of the processing capacity of each kernel cannot be achieved, and the following improvement is further made on the basis of the conventional processor.

Referring to fig. 3 and 5, in some embodiments, the processor circuit further includes a current detection module 300 coupled to each of the power supply modules 200 a-200 n; the current detection module 300 is configured to: detecting output currents of the power supply modules 200a to 200 n; the current detection module 300 is specifically connected to the power control module 210, and the current detection module 300 may be implemented by a current mirror, an inductance coupling, a series connection of a current detection resistor, or a digital sampling analysis, which is not limited in this application. Also, the current detection module 300 may include a plurality of detection branches connected in one-to-one correspondence with the plurality of power supply modules 200a to 200n, each detection branch for detecting an output current of the power supply module 200a to 200n connected thereto. In some cases, the current detection module 300 is a single detection circuit provided with a plurality of detection ports, which can detect the output currents of the respective plurality of power supply modules 200a to 200n in a time-sharing and rotation manner.

The output current value of the power supply modules 200a to 200n detected by the current detection module 300 is the current consumed by the power supply modules 200a to 200n when the cores 110a to 110n associated with the cores 110a to 110n operate, which includes the consumption of software and hardware of the cores 110a to 110n during operation, and also reflects the working conditions and loads of the operation tasks and the control tasks in the cores 110a to 110 n.

Optionally, the adjusting, by the control logic module 120, the frequency of the target kernel according to the load state of the target kernel specifically includes: determining an average operating current of each core 110 a-110 n (which may also be the target core) over a period of time; task scheduling among the cores is performed according to the average working current of each core 110 a-110 n in a period of time; the frequencies of the cores 110a to 110n are adjusted according to the results of task scheduling between cores.

The determination of the average operating current may be performed at the power control module 210 or at the control logic module 120. Specifically, in the first manner, the power control module 210 obtains the output current of each power supply module 200a to 200n from the current detection module 300, and the control logic module 120 calculates the average operating current of each core 110a to 110n corresponding to each power supply module 200a to 200n for a period of time. In the second way, the power control module 210 obtains the output current of each power supply module 200 a-200 n from the current detection module 300, and at the same time, the power control module 210 calculates the average working current of each core 110 a-110 n corresponding to each power supply module 200 a-200 n in a period of time, and the control logic module 120 obtains the average working current of each core 110 a-110 n in a period of time from the power control module 210 of each power supply module 200 a-200 n and transmits the average working current to the core.

For the average working current, the average working current of each clock cycle of each core 110 a-110 n is calculated first, and the average working current in a period of time is the average working current in at least one clock cycle. Thus, when the multithreading task is realized, the cores 110a to 110n of the processor 100 are more precisely assigned to the task, so that the maximum utilization rate of each core 110a to 110n is realized, and the maximum energy saving is realized.

In an alternative embodiment, the task scheduling performed by the control logic module 120 between the kernels is specifically: the inter-core task scheduling includes scheduling the task of the first target core to the second target core for execution, at this time, power supply of the first target core may be turned off, or the first target core may be put into sleep, so that the load of the first target core is reduced, and further, power supply voltage/current is reduced, so as to reduce power consumption of the processor 100. Wherein the first target core is at least one core of the cores 110 a-110 n, i.e. tasks of more than one core may be scheduled to another core. And after the task of the first target kernel is scheduled to the second target kernel for execution, the average working current of the second target kernel in the preset time period is smaller than or equal to the full-load current of the second target kernel, so that the second target kernel can process or control a plurality of tasks at the same time. The preset duration may be the same as the above period of time, or may be different, but is at least one clock cycle. The full load current is the current consumed by the core when operating at full load at a certain frequency.

In an alternative embodiment, the task scheduling performed by the control logic module 120 between the kernels is specifically: and in the preset duration, if the average working current of the first target core is less than I1 x 80%, and the average working current of the second target core is less than I2 x 20%, scheduling the task in the second target core to the first target core, and closing the second target core, wherein I1 is the current consumed during the full-load operation of the first target core, and I2 is the current consumed during the full-load operation of the second target core.

In an alternative embodiment, the task scheduling performed by the control logic module 120 between the kernels is specifically: and dispatching the task in the second target kernel to the first target kernel, and closing the second target kernel, wherein the first target kernel is a kernel with average working current of < I1 x 80% in a preset time period in a plurality of kernels, and the second target kernel is a kernel with average working current of I2< I2 x 20% in the preset time period in the plurality of kernels. I1 is the current consumed by the first target core at full load operation, and I2 is the current consumed by the second target core at full load operation.

In an alternative embodiment, the frequencies of the cores 110 a-110 n related to inter-core task scheduling are adjusted according to the inter-core task scheduling result, and the control logic module 120 will output a voltage adjustment signal related to the frequency adjustment according to the frequency of any core 110 a-110 n, and the power control module 210 will adjust the power supply voltage VOUT of the cores 110 a-110 n provided according to the voltage adjustment signal.

In one example, for example, the core 1 operates at a frequency of 1.8GHz, the current consumed by the core during the full load operation is I1, the core 2 operates at a frequency of 1.2GHz, the current consumed by the core during the full load operation is I2, the current detection module 300 monitors the load currents (i.e. the output currents of the corresponding power supply modules 200 a-200 n) of the cores 1 and 2 in real time, and transmits the load currents to the power supply control module 210, the load currents are transmitted to the logic control module 122 in the processor 100 by the power supply control module 210 in a communication manner, the logic control module 122 calculates the average operating current of the cores 1 and 2 in each clock cycle, and if the average operating current of the core 1 in a plurality of cycles is I1 and I1 is 80%, the average operating current of the core 2 in a plurality of cycles is I2 and I2 is 20%, the logic control module 122 dispatches the tasks in the core 2 to the core 1 to execute, and then closes the core 2, thereby achieving the energy saving purpose.

In some embodiments, current detection module 300 may be integrated within power supply modules 200 a-200 n as part of power supply modules 200 a-200 n to enable load detection functionality for power supply modules 200 a-200 n. Of course, the current detection module 300 may be independent of the power supply modules 200a to 200n. The power supply modules 200 a-200 n may be implemented using discrete devices or may be implemented using integrated circuits.

According to the embodiment of the application, each core 110 a-110 n is independently powered by using the power supply module 200 a-200 n with the load detection function (the load detection function can be independently set), and the load current of each core 110 a-110 n is monitored in real time, so that the power supply of each core 110 a-110 n closest to the actual running condition can be realized, and when a multithreading task is realized, the cores 110 a-110 n are more accurately assigned and distributed, the maximum utilization rate of each core 110 a-110 n is realized, and the maximum energy saving is realized.

A second aspect of the present embodiment provides a power supply control method applied to power supply modules 200a to 200n for supplying power to a processor 100, where the processor 100 is provided with a control logic module 120 and a plurality of cores 110a to 110n, different cores 110a to 110n in the plurality of cores 110a to 110n are powered by different power supply modules 200a to 200n, please refer to fig. 1 to 5, and fig. 6, and the power supply control method includes:

step S110 provides power supply voltages to the respective cores 110a to 110n connected to the power supply modules 200a to 200 n.

In step S120, the power supply voltage provided to the target core is adjusted according to the trigger caused by the control logic module 120 to adjust the frequency of the target core, where the target core is at least one core of the cores 110a to 110 n.

The frequencies of cores 110 a-110 n are adjusted according to the load conditions of cores 110 a-110 n. The logic control module 122 adjusts the frequency of the target core according to the load state of the target core, and the power supply modules 200a to 200n will respond to the adjustment of the frequency of the target core.

In an alternative embodiment, referring to fig. 3, each of the power supply modules 200a to 200n includes a power control module 210 and a voltage conversion module 220 connected to the power control module 210, each of the power control modules 210 is connected to the control logic module 120, the voltage conversion modules 220 are connected to the cores 110a to 110n in a one-to-one correspondence, and referring to fig. 7, step S120 includes:

In step S122, the receiving control logic module 120 outputs a corresponding voltage adjustment signal according to the frequency of the adjustment target core.

Specifically, the control logic module 120 generates a voltage adjustment signal of the corresponding target core according to the frequency of the target core and outputs the voltage adjustment signal to the power control module 210. The voltage regulation signal is used by the power control module 210 to determine the regulated supply voltage VOUT. It may be appreciated that the voltage adjustment signal carries a specific target voltage value, or the voltage adjustment signal carries a frequency of the target core, and the power control module 210 may determine the target voltage value according to a pre-stored correspondence between the frequency and the target voltage value.

Step S124, the voltage conversion module 220 of the power supply modules 200a to 200n is controlled to perform voltage conversion according to the received voltage adjustment signal, so as to adjust the power supply voltage of the target core. It is understood that steps S122 and S124 may be performed by the power control module 210 or by the power management module 150.

For determining the load state of the target kernel, the control logic module 120 may compare the task at the next time in the queue of the target kernel with the current or historical task, for example, compare the same task as the task at the next time, and if not the same task is the same, compare the adjacent task, and estimate the load state of the target kernel at the next time when the task at the next time is about to be run.

In an alternative embodiment, referring to fig. 3, 5 and 8, the power supply control method further includes:

step S210, determining an average operating current of the target core over a period of time.

Specifically, the output currents of the power supply modules 200a to 200n are detected by the current detection module 300, and the obtained output currents of the power supply modules 200a to 200n are used to calculate the average working currents of the cores 110a to 110n corresponding to the power supply modules 200a to 200n in a period of time. As described above, for the calculation of the average operating current over a period of time, reference may be made to the foregoing embodiments, which are not described here in detail.

In step S210, the trigger of adjusting the frequency of the target core is adjusted according to the average working current of the target core in a period of time from the control logic module 120, and the power supply voltage VOUT provided to the target core is adjusted.

As can be seen from the foregoing embodiments, the adjustment of the power supply voltage VOUT of the target core is based on the change of the frequency of the target core, in this embodiment, based on the task scheduling of more than one core to another core for reducing power consumption, the core that is scheduled with the task can reduce the frequency of its operation after the task scheduling is completed, so the frequency of a part of the target cores can be reduced based on the task scheduling between the cores, and thus the power supply modules 200 a-200 n will adjust the power supply voltage VOUT provided to the part of the target cores as a trigger. It will be appreciated that the power control module 210 will output a voltage regulation signal related to the regulation of the frequency in accordance with the control logic module 120 adjusting the frequency of the target core based on the inter-core task schedule, adjusting the supply voltage VOUT of the provided target core.

For specific descriptions of task scheduling between kernels, reference may be made to the foregoing embodiments, which are not repeated here.

The third aspect of the present embodiment further provides another power supply control method applied to a processor 100 provided with a plurality of cores 110a to 110n, wherein different cores 110a to 110n of the plurality of cores 110a to 110n are powered by different power supply modules 200a to 200n, referring to fig. 1 to 5, and fig. 9, the power supply control method includes:

in step S320, in the process that the power supply module 200a to 200n of the target core is the power supply of the target core, the frequency of the target core is obtained, and the target core is at least one core of the cores 110a to 110 n.

Step S340, according to the frequency of the target core, the power supply modules 200a to 200n for supplying power to the target core are controlled to adjust the power supply voltage provided to the target core.

It is understood that the frequency of the cores 110 a-110 n may represent workload states. Thus, in various embodiments, each of the plurality of cores 110 a-110 n within processor 100 is controlled to follow changes in its frequency, powered at a corresponding voltage, such that not only asymmetric workloads may be performed on the plurality of cores 110 a-110 n to provide deterministic performance; the cores 110 a-110 n with low loads can also work at a lower frequency and supply power with lower voltage, and even the cores 110 a-110 n without operation tasks are stopped to be powered off, so that unnecessary loss is reduced.

Referring to fig. 10, in an alternative embodiment, the power supply control method further includes, before step S320: step S310, adjusting the frequency of the target kernel according to the load state of the target kernel. Generally, the load state can be classified into idle, load-reducing, and load-increasing. Accordingly, adjusting the frequency of the respective target cores may be to stop the provision of the frequency (signal) such that the target cores sleep (corresponding to idle), decrease the frequency (corresponding to load shedding), and increase the frequency (corresponding to load boosting).

In other embodiments, the frequency adjustment of the cores 110 a-110 n may be preset by external instructions; the logic control module 122 may also adjust the frequency of the corresponding target core according to the load status of the target core. For the determination of the load states of the cores 110a to 110n, the control logic module 120 may compare the task at the next time in the queue of the target cores with the current or historical task, for example, the task same as the task at the next time is compared, and if the task is not the same, the task close to the task is compared, so as to estimate the load state of the target core at the next time, which is about to run the task at the next time.

The load status at the next moment may include idle, load shedding, and load increasing, and the logic control module 122 may control the fm control module 126 to provide a preset frequency to the target core according to the load status at the current or next moment of the predicted upcoming execution, or may adjust the frequency, such as stopping the provision of the frequency (signal) to enable the target core to sleep (corresponding to idle), reducing the frequency (corresponding to load shedding), and increasing the frequency (corresponding to load increasing). Wherein the load of the target core may be represented by its operating voltage or current or power, or operating frequency.

In a more detailed embodiment, step S320 includes outputting corresponding voltage regulation signals to the power control modules 210 of the power supply modules 200 a-200 n that power the target core based on the frequency of the target core. The voltage adjustment signal is used for instructing the power control module 210 to control and adjust the voltage transformation performed by the voltage transformation module 220 of the power supply modules 200 a-200 n, so as to adjust the power supply voltage VOUT provided by the voltage transformation module 220 to the target core. An embodiment of the power supply module may be referred to in fig. 3 and the description thereof.

In addition, when the conventional processor performs kernel assignment on the linear task, the conventional processor has certain randomness, so that the full utilization of the processing capacity of each kernel can not be achieved, and on the basis of the conventional processor, the power supply control method of the application also improves the conventional processor.

Referring to fig. 3, 5 and 11, in an alternative embodiment, step S310 includes:

in step S312, an average operating current of the target core over a period of time is determined. Specifically, the output currents of the power supply modules 200a to 200n are detected by the current detection module 300, the obtained output currents of the power supply modules 200a to 200n are calculated, and the average working current of the target cores corresponding to the power supply modules 200a to 200n in a period of time is calculated. As described above, for the calculation of the average operating current over a period of time, reference may be made to the foregoing embodiments, which are not described here in detail.

Step S314, task scheduling among the cores is performed according to the average working current of the target core in a period of time.

In an alternative embodiment, inter-core task scheduling includes scheduling tasks of a first target core to a second target core for execution and shutting down the first target core to reduce power consumption of processor 100. The first target core is at least one core of the plurality of cores 110a to 110n, and after the task of the first target core is scheduled to be executed by the second target core, the average working current of the second target core in the preset time period is smaller than or equal to the full load current of the second target core. Enabling the second target kernel to satisfy simultaneous processing or control of multiple tasks. The preset duration may be the same as the above period of time, or may be different, but is at least one clock cycle. The full load current is the current consumed by the core when operating at full load at a certain frequency.

For example, in one example, the core 1 operates at a frequency of 1.8GHz, the current consumed by the core during the full load operation is I1, the core 2 operates at a frequency of 1.2GHz, the current consumed by the core during the full load operation is I2, the current detection module 300 monitors the load currents (i.e. the output currents of the corresponding power supply modules 200 a-200 n) of the cores 1 and 2 in real time, and transmits the load currents to the power supply control module 210, the load currents are transmitted to the logic control module 122 in the processor 100 by the power supply control module 210 in a communication manner, the logic control module 122 calculates the average working current of the cores 1 and 2 in each clock cycle, and if the average working current of the core 1 in a plurality of cycles is I1 and I1 is 80%, the average working current of the core 2 in a plurality of cycles is I2 and I2 is 20%, the logic control module 122 dispatches the tasks in the core 2 to the core 1 to execute, and then closes the core 2, thereby achieving the energy saving purpose.

Step S316, adjusting the frequency of the target kernel related to task scheduling according to the task scheduling result among the kernels. And the control logic module 120 further adjusts the power supply module for controlling the power supply of the target core to the power supply voltage VOUT provided by the target core according to the frequency of the target core.

For step S312, determining the average operating current of the target core over a period of time includes: the control logic module 120 calculates the average working current of the target cores corresponding to the power supply modules 200a to 200n in a period of time according to the acquired output currents of the power supply modules 200a to 200 n; alternatively, the control logic module 120 is included to obtain, from the power supply modules 200a to 200n, the average working current of the target core calculated by the power management module 150 or the power control module 210 in a period of time, where the average working current of the core in a period of time is calculated by the power management module 150 or the power control module 210 according to the output currents of the power supply modules 200a to 200n detected by the current detection module 300.

It will be appreciated that inter-core task scheduling is also one type of change in load state of the cores, i.e., the control logic module 120 may adjust the frequencies of the cores 110 a-110 n based on inter-core task scheduling and output voltage regulation signals related to the frequency adjustment, and the power control module 210 will adjust the supply voltages VOUT of the cores 110 a-110 n provided according to the voltage regulation signals.

The power supply control method provided in the second aspect of the embodiments of the present application may be implemented when the power supply control module 210 of the power supply modules 200a to 200n executes a computer program, or may be implemented when the power supply management module 150 executes a computer program. The power supply control method provided in the third aspect of the embodiments of the present application may be implemented when the control logic module 120 in the processor 100 executes a computer program, or may be implemented when other controllers in the processor 100 execute a computer program, such as a power control logic module. Or may be implemented when the computer program is executed by a controller other than the processor 100.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules, that is, the internal structure of the processor circuit is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

Based on the same inventive concept, the embodiment of the application also provides an energy storage device data display device. Fig. 12 is a schematic structural diagram of an energy storage device data display device provided in an embodiment of the present application, as shown in fig. 12, a terminal device provided in this embodiment includes: a memory 400 and a processor 100, the memory 400 for storing a computer program; the processor 100 is arranged to perform the method described in the method embodiments above when a computer program is called. In other embodiments, the terminal device provided in this embodiment includes a processor 100, and the computer program is stored in the processor 100, where the processor 100 is configured to execute the method described in the foregoing method embodiment when the computer program is called.

The terminal device provided in the embodiment of the present application may execute the above method embodiment, and its implementation principle is similar to that of the technical effect, and will not be described herein again.

The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the method described in the above method embodiment.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein.

The processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The Memory may include non-volatile Memory in a computer readable medium, random access Memory (Random Access Memory, RAM) and/or non-volatile Memory, etc., such as Read-Only Memory (ROM) or Flash Memory (Flash Memory). Memory is an example of a computer-readable medium.

Computer readable media include both non-transitory and non-transitory, removable and non-removable storage media. Storage media may embody any method or technology for storage of information, which may be computer readable instructions, data structures, program modules, or other data. Examples of storage media for a computer include, but are not limited to, phase-Change Memory (PCM), static Random-Access Memory (SRAM), dynamic Random-Access Memory (Dynamic Random Access Memory, DRAM), other types of RAM, ROM, electrically erasable programmable read-Only Memory (EEPROM), flash Memory or other Memory technology, compact disc read-Only, ROM, digital versatile disc (Digital Versatile Disc, DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by the computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media, such as modulated data signals and carrier waves.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A processor circuit, comprising:

2. The processor circuit of claim 1, wherein the power supply module comprises a power control module and a voltage conversion module;

3. The processor circuit of claim 2, further comprising a power management module;

4. A processor circuit according to any one of claims 1 to 3, wherein the control logic module is further configured with the following functionality: and adjusting the frequency of the target kernel according to the load state of the target kernel.

5. The processor circuit of claim 4, wherein said adjusting the frequency of the target core based on the load state of the target core comprises:

6. The processor circuit of claim 5 further comprising a current detection module coupled to each of said power supply modules for detecting an output current of each of said power supply modules;

7. The processor circuit of claim 6 wherein said current detection module comprises a plurality of detection branches, each of said detection branches being connected in one-to-one correspondence with each of said power supply modules, each of said detection branches being configured to detect an output current of said power supply module to which it is correspondingly connected.

8. The processor circuit of claim 5 wherein the inter-core task scheduling comprises scheduling tasks of a first target core to a second target core for execution;

9. A power control method, applied to a power supply module that supplies power to a processor, the processor being provided with a control logic module and a plurality of cores, different cores of the plurality of cores being supplied with power by different power supply modules, the power control method comprising:

providing a power supply voltage for each of the cores connected to the power supply module;

10. The power control method of claim 9, wherein the triggering is caused by the control logic module adjusting a frequency of the target core based on a load state of the target core.

11. The power supply control method according to claim 9 or 10, characterized in that the power supply control method further comprises:

12. The power control method of claim 11, wherein the determining the average operating current of the target core over a period of time comprises:

13. The power control method of claim 11, wherein the inter-core task scheduling includes scheduling tasks of a first target core to a second target core for execution;

14. The power supply control method according to claim 9 or 10, wherein the adjusting the power supply voltage supplied to the target core according to the trigger caused by the control logic module for adjusting the frequency of the target core includes:

15. A power supply control method, applied to a processor provided with a plurality of cores, different cores of the plurality of cores being supplied with power by different power supply modules, comprising:

16. The power supply control method according to claim 15, characterized by further comprising, before the obtaining of the frequency of the target core in the process that the power supply module of the target core supplies power to the target core:

17. The power supply control method according to claim 16, wherein the adjusting the frequency of the target core according to the load state of the target core includes:

18. The power control method of claim 17, wherein the determining the average operating current of the target core over a period of time comprises:

19. The power control method of claim 17, wherein the inter-core task scheduling includes scheduling tasks of a first target core to a second target core for execution;

20. The power supply control method according to claim 15 or 16, wherein the controlling the power supply module that supplies power to the target core to adjust the power supply voltage supplied to the target core according to the frequency of the target core includes:

21. A terminal device comprising a processor circuit as claimed in any one of claims 1 to 8.

22. Terminal device comprising a processor and a computer program stored in and executable on the processor, characterized in that the processor, when executing the computer program, realizes the steps of the method according to any of claims 9 to 14 or the steps of the method according to any of claims 15 to 20.

23. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 9 to 14 or the steps of the method according to any one of claims 15 to 20.