CN116107377A - Circuit for generating bias voltage of passive self-mixer - Google Patents
Circuit for generating bias voltage of passive self-mixer Download PDFInfo
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- CN116107377A CN116107377A CN202310136763.8A CN202310136763A CN116107377A CN 116107377 A CN116107377 A CN 116107377A CN 202310136763 A CN202310136763 A CN 202310136763A CN 116107377 A CN116107377 A CN 116107377A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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- H03D7/125—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes with field effect transistors
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Abstract
The present disclosure provides a circuit for generating a non-derived mixer bias voltage, comprising: a bias module for providing a bias current; the bias voltage generation module is used for generating gate end bias voltage required by the PMOS tube of the rear passive self-mixer and source-drain common mode level of the NMOS tube and the PMOS tube of the rear passive self-mixer under the action of the bias current; the compensation module is used for compensating the bias voltage and the common mode level of the source and the drain, so that the radio frequency input impedance of the rear passive self-mixer cannot change along with temperature, process and power supply voltage changes when the rear passive self-mixer works; the gate bias voltage required by the NMOS tube of the rear passive self-mixer is directly provided by the power supply voltage VDD.
Description
Technical Field
The present disclosure relates to the field of analog integrated circuits, and more particularly, to a circuit for generating a passive self-mixer bias voltage.
Background
The wake-up receiver is in a normally open state, has extremely low power consumption and is responsible for monitoring channels. The primary receiver is in a sleep state when the wake-up receiver does not receive the data communication request identification signal (i.e., wake-up signal), and upon receipt of the wake-up signal, the wake-up receiver wakes up the active primary receiver. This approach can effectively reduce power consumption of the wireless communication system. Since the wake-up receiver is normally open, the power consumption requirements on itself are very stringent, typically on the order of microwatts (μw) or nanowatts (nW). In the existing wake-up receiver architecture, the direct envelope detection architecture can meet such severe power consumption requirements. In the wake-up receiver of the direct envelope detection architecture applied in the present disclosure, the radio frequency input signal directly enters the passive self-mixer to be down-converted to the intermediate frequency after passing through the matching network, and as the power starving units such as the active mixer, the local oscillator, the radio frequency low noise amplifier and the like are omitted, and the self-mixer is passive, the power consumption of the wake-up receiver using the architecture can be very low. However, the bias voltage of the passive self-mixer in the wake-up receiver based on the architecture is usually provided by adopting an off-chip external voltage source, and is not suitable for practical product application, or other bias voltages required by the passive self-mixer are generated on-chip, and the problems of high system complexity, high power consumption or poor performance exist.
Disclosure of Invention
Based on the above problems, the present disclosure provides a circuit for generating a bias voltage without a source of a mixer, so as to alleviate the above technical problems in the prior art.
The disclosure provides a circuit for generating a bias voltage without a source of a mixer, comprising a bias module, a bias voltage generating module and a compensation module.
The bias module is used for providing bias current; the bias voltage generation module is used for generating gate end bias voltage required by the PMOS tube of the rear passive self-mixer and source-drain common mode level of the NMOS tube and the PMOS tube of the rear passive self-mixer under the action of the bias current; the compensation module is used for compensating the bias voltage and the source-drain common mode level, so that the radio frequency input impedance of the rear passive self-mixer cannot change along with temperature, process and power supply voltage changes when the rear passive self-mixer works; the gate bias voltage required by the NMOS tube of the rear passive self-mixer is directly provided by the power supply voltage VDD.
According to an embodiment of the present disclosure, the bias module includes: reference current source I R Second NMOS tube M 2 。
Reference current source I R For providing bias current I REF The bias current I REF The temperature, the process angle and the power supply voltage are not changed along with the change of the temperature, the process angle and the power supply voltage; second NMOS tube M 2 Is connected to the gate and drain of the on-chip reference current source I R Lower end of the second NMOS tube M 2 The source electrode of the transistor is grounded; the reference current source I R Is connected to the power supply voltage VDD.
According to an embodiment of the present disclosure, a bias voltage generation module includes: a first NMOS tube unit, a first PMOS tube unit, a third NMOS tube M 3 。
The first NMOS transistor unit comprises a plurality of NMOS transistors connected in series, wherein the source electrode of the previous NMOS transistor is connected to the drain electrode of the next NMOS transistor, the drain electrode of the first NMOS transistor is connected to the power supply voltage VDD, and the source electrode of the last NMOS transistor is connected to the first node CN 1 The gates of the plurality of NMOS transistors connected in series are commonly connected to a power supply voltage VDD; the first PMOS tube unit comprises a plurality of PMOS tubes connected in series, wherein the source electrode of the former PMOS tube is connected to the drain electrode of the next PMOS tube, and the drain electrode of the first PMOS tube is connected to the second node CN2 and then connected to the third NMOS tube M 3 The source of the last PMOS tube is connected to the first node CN 1 The grid electrodes of the PMOS tubes connected in series are commonly connected to a third NMOS tube M 3 A drain electrode of (2); the third NMOS tube M 3 Gate of (d) and second NMOS transistor M 2 The gate of the third NMOS tube M is connected with 3 The source of (c) is grounded.
According to the embodiment of the disclosure, the sizes of the NMOS transistors connected in series in the first NMOS transistor unit are the same and are equal to the sizes of NMOS transistors used for frequency conversion in the rear passive self-mixer; the sizes of the PMOS tubes connected in series in the first PMOS tube unit are the same and are equal to the sizes of the PMOS tubes used for frequency conversion in the rear passive self-mixer; third NMOS tube M 3 The second NMOS tube M in the size and bias module of (a) 2 The third NMOS tube M has the same size 3 Equivalent to M second NMOS tubes M 2 Is connected in parallel to make the third NMOS tube M 3 Drain-source current of (2) is the second NMOS tube M 2 M is more than or equal to 1, which is M times of drain-source current.
According to an embodiment of the present disclosure, a compensation module includes: first PMOS tube M 1 First operational amplifier OP 1 A second NMOS tube unit, a fourth NMOS tube M 4 A second PMOS tube unit, a resistor R REF Second operational amplifier OP 2 Fifth NMOS tube M 5 Sixth NMOS tube M 6 。
First PMOS tube M 1 Is connected to the power supply voltage VDD, and the drain is connected to the third node CN 3 The method comprises the steps of carrying out a first treatment on the surface of the First operational amplifier OP 1 Is connected to the first node CN 1 The non-inverting input terminal is connected to the third node CN 3 An output end connected to the first PMOS tube M 1 A gate electrode of (a); the second NMOS transistor unit comprises a plurality of NMOS transistors connected in series, wherein the drain electrode of the previous NMOS transistor is connected to the source electrode of the next NMOS transistor, the source electrode of the first NMOS transistor is connected to the fourth node CN4, and the drain electrode of the last NMOS transistor is connected to the third node CN 3 The gates of the plurality of NMOS transistors connected in series are commonly connected to a power supply voltage VDD; fourth NMOS tube M 4 The drain electrode of (a) is connected to the fourth node CN4, and the gate electrode is connected to the third NMOS transistor M 3 The source electrode is grounded; the second PMOS tube unit comprises a plurality of PMOS tubes connected in series, wherein the source electrode of the former PMOS tube is connected to the drain electrode of the next PMOS tube, and the drain electrode of the first PMOS tube is connected to the fourth node CN 4 The source of the last PMOS tube is connected to the third node CN 3 The gates of the PMOS tubes connected in series are commonly connected to the second node CN 2 The method comprises the steps of carrying out a first treatment on the surface of the Resistor R REF Is connected to the third node CN 3 The method comprises the steps of carrying out a first treatment on the surface of the Second operational amplifier OP 2 Is connected to the fourth node CN 4 The non-inverting input terminal is connected to the fifth node CN 5 Is connected back to resistor R REF Is arranged at the lower end of the lower part; fifth NMOS tube M 5 Is connected to the second operational amplifier OP 2 The source terminal is grounded, and the grid electrode is connected to the fourth NMOS tube M 4 A gate electrode of (a); sixth NMOS tube M 6 Is connected to the second operational amplifier OP 2 Output terminal of (2)The drain is connected to the second node CN2 and the source is grounded.
According to the embodiment of the disclosure, the sizes of the plurality of NMOS transistors in the second NMOS transistor unit are the same and equal to the sizes of NMOS transistors used for frequency conversion in the rear passive self-mixer, and the sizes of the plurality of PMOS transistors in the second PMOS transistor unit are the same and equal to the sizes of PMOS transistors used for frequency conversion in the rear passive self-mixer.
According to an embodiment of the present disclosure, a fourth NMOS tube M 4 Is of the size and bias module second NMOS tube M 2 The dimensions of (a) are the same, but the fourth NMOS transistor M 4 Equivalent to N second NMOS tubes M 2 In parallel with each other, so that the fourth NMOS transistor M 4 The drain-source current of (a) is the second NMOS tube M 2 N times of drain-source current, N is more than or equal to 1.
According to an embodiment of the present disclosure, a fifth NMOS tube M 5 The second NMOS tube M in the size and bias module of (a) 2 The fifth NMOS transistor M has the same size 5 Equivalent to P second NMOS tubes M 2 Is connected in parallel to make the fifth NMOS tube M 5 The drain-source current of (a) is the second NMOS tube M 2 P times of drain-source current, and P is more than or equal to 1.
According to an embodiment of the present disclosure, the first operational amplifier OP is used for 1 Clamping such that the first node CN 1 And the third node CN 3 Is equal in potential.
According to an embodiment of the present disclosure, the second operational amplifier OP 2 Clamping is performed such that the second operational amplifier OP 2 The non-inverting input terminal and the inverting input terminal of (a) are equal in potential.
Drawings
FIG. 1 is a schematic diagram of a typical passive self-mixer in the prior art;
fig. 2 is a schematic circuit diagram of a differential passive self-mixer with adjustable gate voltage in the prior art;
FIG. 3 shows a prior art method for generating a gate bias voltage V of an NMOS transistor of a passive self-mixer in a wake-up receiver G_BN Gate bias voltage V of PMOS tube G_BP Is a circuit schematic of (a);
FIG. 4 is a prior artThe grid end bias voltage V of the passive self-mixer NMOS tube in the wake-up receiver is generated in an on-chip mode BN Gate bias voltage V of PMOS tube BP Common source-drain common mode level V of NMOS tube and PMOS tube CM1 A schematic circuit diagram generated by an on-chip bandgap reference source;
fig. 5 is a circuit schematic diagram of generating a passive self-mixer bias voltage by on-chip means in accordance with an embodiment of the present disclosure.
Detailed Description
The present disclosure provides a circuit for generating a bias voltage without a source from a mixer, and in particular, a circuit for generating a gate bias voltage of an NMOS transistor, a gate bias voltage of a PMOS transistor, and a common source-drain common mode level of the NMOS and PMOS transistors of a passive self-mixer in a wake-up receiver. If the circuit can provide the grid end bias voltage VDD of the NMOS tube and the grid end bias voltage V of the PMOS tube for the passive self-mixer on the chip GP Common source-drain common mode level V of NMOS tube and PMOS tube CM，COPY . The circuit comprises a temperature, process angle and power supply voltage compensation module, ensures that the radio frequency input impedance of the rear passive self-mixer determined by the generated bias voltage is basically unchanged when the temperature is changed, the process difference and the power supply voltage are changed, can be suitable for a larger temperature range, is suitable for the process difference and the power supply voltage change, has stronger robustness, and has extremely low power consumption (nW magnitude). Meanwhile, the radio frequency input impedance of the rear passive self-mixer determined by the bias voltage generated by the invention can have a large adjustment range, which shows that the invention can be used in passive self-mixers of wake-up receivers with different index requirements.
When the passive self-mixer works normally, the MOS tubes for frequency conversion work in a weak inversion state. The most important circuit element parameter without the source of the mixer is the small signal output impedance R of the MOS tube for frequency conversion out For R out The method comprises the following steps:
wherein V is ds Is the drain-source voltage of the MOS tube, I ds Is MOS tubeDrain-source current of V gs Is the gate-source voltage of the MOS tube. R is R out Determining the radio frequency input impedance, output noise power, charging time, etc. of the passive self-mixer by adjusting R out The value of (2) can effectively optimize the performance of the passive self-mixer. In the wake-up receiver using the direct envelope detection architecture, the passive self-mixer is directly connected with the matching network as the next stage of the matching network, so that the radio frequency input impedance of the self-mixer directly affects the passive voltage gain of the matching network, thereby affecting important indexes such as sensitivity and the like of the wake-up receiver. In the design of a wake-up receiver of a direct envelope detection architecture, the small signal output impedance R of a MOS tube for frequency conversion in a passive self-mixer is adjusted out It is extremely important to adjust the radio frequency input impedance of the passive self-mixer to a suitable value.
Fig. 1 is a circuit configuration diagram of a typical passive self-mixer, the circuit being self: moody, J and powers, SM. "Triode-mode Envelope Detectors for Near Zero Power Wake-up Receivers," IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2019, pp.1499-1502. When the passive self-mixer is designed, the small signal output impedance R of the MOS tube is mainly regulated by regulating the size of the MOS tube and using the MOS tubes with different threshold voltages out . However, this adjustment method has a number of drawbacks: on one hand, the MOS tube is larger in size, and larger input parasitic capacitance is introduced, and the parasitic capacitance can influence the passive voltage gain of the front-stage matching network, so that the performance of the wake-up receiver is deteriorated; on the other hand, the adjusting mode is affected by factors such as temperature, process and the like, and the overall robustness of the circuit is poor.
Fig. 2 is a circuit structure diagram of a differential passive self-mixer with adjustable gate voltage, and the circuit is as follows: moody, J and powers, SM. "Triode-mode Envelope Detectors for Near Zero Power Wake-up Receivers," IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2019, pp.1499-1502. MOS tube small signal output impedance R of differential passive self-mixer with adjustable gate voltage out The value of (2) can be changed by changing the gate bias voltage of the NMOS tube and the gate bias voltage of the PMOS tubeThe common source-drain common mode level of the voltage, NMOS tube and PMOS tube is regulated. Compared with the typical non-source mixer shown in fig. 1, the circuit shown in fig. 2 outputs an impedance R to a small signal of a MOS transistor out Has a larger adjustment range of values; the MOS tube with small size can be selected, so that the input parasitic capacitance is reduced, and the influence of the input parasitic capacitance on the passive voltage gain of the matching network is reduced; through a proper bias voltage generating circuit, the MOS tube small signal output impedance R can be realized out The value of (2) does not change with temperature, process and power supply voltage, and has good robustness. In the circuit shown in fig. 2, the common mode level of the NMOS gate bias, the PMOS gate bias and the source drain is determined by the three bias voltages, namely the small signal output impedance R of the NMOS tube and the PMOS tube out The difference of the adjustable gate voltage is directly determined to be free from the radio frequency input impedance of the mixer when in operation, so that important indexes such as sensitivity and the like of a wake-up receiver are affected.
In most existing designs, these three bias voltages required for passive self-mixers are often provided by means of an off-chip external voltage source, but this approach is not suitable for practical product applications. In the prior art, there is also an example of generating the bias voltage of the passive self-mixer MOS transistor by an on-chip method, and as shown in fig. 3, the circuit is derived from: mangal and P.R.kit, "An ultra-low-power Wake-Up Receiver with Voltage-multiplexing Self-Mixer and Interferer-Enhanced Sensitivity," in IEEE Custom Integrated Circuits Conference (CICC), 2017, PP.1-4. However, in this example, the gate bias voltage V of the NMOS transistor generated by the circuit G_BN And the gate bias voltage V of the PMOS tube G_BP Are voltages at the output of the operational amplifier, which causes the bias voltage generated to be limited by the voltage swing at the output of the operational amplifier. In some applications or under specific process or temperature conditions, it may be desirable to require V G_BN Is close to the supply voltage and V G_BP Which increases the complexity and power consumption of the op-amp design and may cause the circuit to fail due to degradation of the dc operating point of the op-amp, resulting in a resultant post-stage differential free of rf input impedance from the mixer and the required power consumptionThe values differ significantly, eventually leading to degradation of the performance of the wake-up receiver. And in the example, the common source-drain common mode level V of the NMOS tube and the PMOS tube C External off-chip voltage sources are needed to provide or generate through on-chip band gap reference voltage sources, so that the complexity and the power consumption of the system are increased.
As shown in FIG. 4, the circuit can also be used for generating the bias voltage of the MOS transistor of the passive self-mixer on a chip, the circuit is from patent number CN201810259599, and the circuit can generate the bias voltage V of the gate end of the NMOS transistor of the post-stage passive self-mixer BN Gate bias voltage V of PMOS tube BP Common source-drain common mode level V of NMOS tube and PMOS tube CM1 Generated by an on-chip bandgap reference source. Because the MOS tube of the passive self-mixer works in a weak inversion state, the small signal output impedance of the NMOS tube of the rear-stage passive self-mixer determined by the bias voltage generated by the circuit is proportional to V t /I B The small signal output impedance of the PMOS tube is also proportional to V t /I B The specific values of which are related to the circuit process parameters. V (V) t Is thermal voltage, V t =kt/q, k is boltzmann constant, T is thermodynamic temperature, q is the amount of charge of electrons, which means that the radio frequency input impedance of the passive self-mixer of the subsequent stage, determined by this bias voltage, varies with temperature and is affected by the circuit process. And the circuit can only change the bias current I B To simultaneously adjust the small signal output impedance of the NMOS and PMOS transistors of the rear passive self-mixer, and not to separately adjust them, which limits the performance of the rear passive self-mixer.
Accordingly, the present disclosure provides a circuit that generates a bias voltage that does not originate from a mixer, in order to ameliorate some of the technical problems of the prior art.
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
In an embodiment of the present disclosure, a circuit for generating a passive self-mixer bias voltage is provided, as shown in fig. 5, the circuit for generating a non-derived mixer bias voltage, comprising:
a bias module 1 for providing a bias current I REF ；
The bias voltage generating module 2 is used for generating a gate terminal bias voltage V required by the PMOS tube of the post passive self-mixer under the action of the bias current GP And a level (VCM, AND V) equal to the common mode level of the source and drain of the NMOS and PMOS transistors of the post passive self-mixer CM，COPY Equal); and
a compensation module 3 for compensating the bias voltage V GP Source drain common mode level V CM，COPY And compensation is performed, so that the radio frequency input impedance of the rear passive self-mixer cannot change along with temperature, process and power supply voltage changes during operation.
The gate bias voltage required by the NMOS tube of the rear passive self-mixer is directly provided by the power supply voltage VDD.
According to an embodiment of the present disclosure, a bias voltage generation module includes:
a first NMOS transistor unit including multiple NMOS transistors connected in series, wherein the source of the previous NMOS transistor is connected to the drain of the next NMOS transistor, the drain of the first NMOS transistor is connected to the power supply voltage VDD, and the source of the last NMOS transistor is connected to the first node CN 1 The gates of the plurality of NMOS transistors connected in series are commonly connected to a power supply voltage VDD;
the first PMOS tube unit comprises a plurality of PMOS tubes connected in series, wherein the source electrode of the former PMOS tube is connected to the drain electrode of the next PMOS tube, and the drain electrode of the first PMOS tube is connected to the second node CN2 and then connected to the third NMOS tube M 3 The source of the last PMOS tube is connected to the first node CN 1 The grid electrodes of the PMOS tubes connected in series are commonly connected to a third NMOS tube M 3 A drain electrode of (2);
the third NMOS tube M 3 Gate of (d) and second NMOS transistor M 2 The gate of the third NMOS tube M is connected with 3 The source of (c) is grounded.
According to an embodiment of the present disclosure, the plurality of serially connected NMOS transistors in the first NMOS transistor unit are the same size and equal to those used in the post passive self-mixerNMOS tube size of frequency conversion; the sizes of the PMOS tubes connected in series in the first PMOS tube unit are the same and are equal to the sizes of the PMOS tubes used for frequency conversion in the rear passive self-mixer; third NMOS tube M 3 The second NMOS tube M in the size and bias module of (a) 2 The third NMOS tube M has the same size 3 Equivalent to M second NMOS tubes M 2 Is connected in parallel to make the third NMOS tube M 3 The drain-source current of (a) is the second NMOS tube M 2 M is more than or equal to 1, which is M times of drain-source current.
According to an embodiment of the present disclosure, a compensation module includes:
first PMOS tube M 1 The source is connected to the power supply voltage VDD, and the drain is connected to the third node CN 3 ；
First operational amplifier OP 1 The inverting input terminal is connected to the first node CN 1 The non-inverting input terminal is connected to the third node CN 3 An output end connected to the first PMOS tube M 1 A gate electrode of (a);
a second NMOS transistor unit including multiple NMOS transistors connected in series, wherein the drain electrode of the previous NMOS transistor is connected to the source electrode of the next NMOS transistor, the source electrode of the first NMOS transistor is connected to the fourth node CN4, and the drain electrode of the last NMOS transistor is connected to the third node CN 3 The gates of the plurality of NMOS transistors connected in series are commonly connected to a power supply voltage VDD;
fourth NMOS tube M 4 The drain electrode is connected to the fourth node CN4, and the gate electrode is connected to the third NMOS transistor M 3 The source electrode is grounded;
the second PMOS tube unit comprises a plurality of PMOS tubes connected in series, wherein the source electrode of the former PMOS tube is connected to the drain electrode of the next PMOS tube, the drain electrode of the first PMOS tube is connected to the fourth node CN4, and the source electrode of the last PMOS tube is connected to the third node CN 3 The gates of the PMOS tubes connected in series are commonly connected to the second node CN 2 ；
Resistor R REF The upper end of which is connected to a third node CN 3 ；
Second operational amplifier OP 2 The inverting input terminal is connected to the fourth node CN4, and the non-inverting input terminalThe ingress is connected to a fifth node CN 5 And is connected to a resistor R REF Is arranged at the lower end of the lower part;
fifth NMOS tube M 5 The drain is connected to the second operational amplifier OP 2 The source terminal is grounded, and the grid electrode is connected to the fourth NMOS tube M 4 A gate electrode of (a); and
sixth NMOS tube M 6 The gate is connected to the second operational amplifier OP 2 Is connected with the drain of the output terminal of the second node CN 2 The source is grounded.
According to the embodiment of the disclosure, the sizes of the plurality of NMOS transistors in the second NMOS transistor unit are the same and equal to the sizes of NMOS transistors used for frequency conversion in the rear passive self-mixer, and the sizes of the plurality of PMOS transistors in the second PMOS transistor unit are the same and equal to the sizes of PMOS transistors used for frequency conversion in the rear passive self-mixer.
According to an embodiment of the present disclosure, a fourth NMOS tube M 4 Is of the size and bias module second NMOS tube M 2 The dimensions of (a) are the same, but the fourth NMOS transistor M 4 Equivalent to N second NMOS tubes M 2 In parallel with each other, so that the fourth NMOS transistor M 4 The drain-source current of (a) is the second NMOS tube M 2 N times of drain-source current, N is more than or equal to 1.
According to an embodiment of the present disclosure, a fifth NMOS tube M 5 The second NMOS tube M in the size and bias module of (a) 2 The fifth NMOS transistor M has the same size 5 Equivalent to P second NMOS tubes M 2 Is connected in parallel to make the fifth NMOS tube M 5 The drain-source current of (a) is the second NMOS tube M 2 P times of drain-source current, and P is more than or equal to 1.
According to an embodiment of the present disclosure, the first operational amplifier OP is used for 1 Clamping such that the first node CN 1 And the third node CN 3 Is equal in potential. Through a second operational amplifier OP 2 Clamping is performed such that the second operational amplifier OP 2 The non-inverting input terminal and the inverting input terminal of (a) are equal in potential.
As shown in fig. 5, the bias module 1 is configured to provide bias currents to the bias voltage generating module 2 and the compensating module 3. The unit bias current is I REF By extremely low power consumption (nW quantity)Stage) reference current source I R Give, I REF Is not changed with temperature, process angle and power supply voltage. The bias voltage generation module 2 is used for generating a PMOS tube gate end bias voltage V required by a post passive self-mixer GP Source-drain common mode level V of NMOS tube and PMOS tube of post passive self-mixer CM，COPY Equal level V CM The gate bias voltage of the NMOS tube needed by the rear passive self-mixer is directly provided by the power supply voltage VDD. The compensation module 3 is used for compensating the temperature, the process angle and the power supply voltage of the small signal output impedance of the NMOS tube and the PMOS tube of the rear passive self-mixer determined by the bias voltage generated in the bias voltage generation module 2. If the compensation module 3 is not used for compensation, the radio frequency input impedance of the passive self-mixer at the later stage in operation can vary greatly with temperature and process angle and can be influenced by power supply voltage, which can seriously influence the performance of the wake-up receiver. When the bias voltage generating module 2 and the compensating module 3 cooperate, the radio frequency input impedance of the post passive self-mixer in working is not changed along with temperature, process angle and power supply voltage, so that the whole circuit has stronger robustness.
As shown in fig. 5, the compensation module 3 includes a first operational amplifier OP 1 The non-inverting input terminal and the inverting input terminal are respectively connected to the first node CN 1 (potential is equal to V CM ) And a third node CN 3 (potential is equal to V CM，COPY ) By using the first operational amplifier OP 1 Clamping to equalize the potentials of the first node and the third node; further comprises a second operational amplifier OP 2 The non-inverting input terminal and the inverting input terminal are respectively connected to the fifth node CN 5 (potential is equal to V + ) And a fourth node CN 4 (potential is equal to V - ) By using the second operational amplifier OP 2 Clamping to make V + And V - Is equal in potential.
In the bias module 1, a second NMOS tube M 2 Is connected with the grid electrode and the drain electrode of the reference current source I R Is connected with the lower end of the second NMOS tube M 2 Is a source of (a)The electrode is grounded, and a reference current source I R Is connected to the supply voltage VDD. Second NMOS tube M 2 Is I REF . The gate bias voltage of the NMOS tube needed by the rear passive self-mixer is directly provided by the power supply voltage VDD.
In the bias voltage generating module 2, the first NMOS transistor unit includes N 2 NMOS transistors N 2 More than or equal to 1, the first PMOS tube unit comprises P 2 P of PMOS tubes 2 Not less than 1, wherein, NMOS tube M N2，1 The drain electrode of the transistor is connected with the power supply voltage, and the source electrode is connected with the NMOS tube M N2，2 Drain electrode of NMOS tube M N2，2 Is connected with NMOS tube M N2，3 And so on, NMOS tube M N2，N2-1 Is connected with NMOS tube M N2，N2 Drain electrode of NMOS tube M N2，1 、M N2，2 ......M N2，N2 The gates of (2) are connected together, and then the gates are connected to the power supply voltage VDD, and the NMOS transistor M is recorded N2，N2 Is V at the source level of (2) CM . Third NMOS tube M 3 The source electrode of the second NMOS transistor M is grounded, the grid electrode of the second NMOS transistor M is grounded, and the second NMOS transistor M is connected with the second NMOS transistor M in the bias module 1 2 Gate connection, drain and PMOS tube M P2，1 Is connected to the drain of the transistor. PMOS tube M P2，1 Drain electrode of (d) and third NMOS transistor M 3 Is connected with the drain electrode of the PMOS tube M P2，1 Source electrode of (C) and PMOS tube M P2，2 Drain electrode connection of PMOS tube M P2，2 Source electrode of (C) and PMOS tube M P2，3 Drain electrode connection of PMOS tube M P2，P2-1 Source electrode of (C) and PMOS tube M P2，P2 Drain electrode connection of PMOS tube M P2，1 、M P2，2 ......M P2，P2 The grids of the PMOS transistors are connected together and then connected to the PMOS transistor M P2，1 Drain electrode of PMOS tube M P2，1 Is V at the drain level of (2) GP NMOS tube M N2，N2 Source electrode of (C) and PMOS tube M P2，P2 Is connected to the source of the (c).
In the bias voltage generating module 2, N2 NMOS transistors M in the first NMOS transistor unit N2，1 、M N2，2 ......M N2，N2 And is equal to the NMOS transistor size for frequency conversion in the passive self-mixer of the subsequent stage. P in the first PMOS tube unit 2 PMOS tubesM P2，1 、M P2，2 ......M P2，P2 The size of the PMOS tube is the same as that of the PMOS tube used for frequency conversion in the rear passive self-mixer. Third NMOS tube M 3 Is the same as the second NMOS transistor M in the bias module 1 2 The third NMOS tube M has the same size 3 Equivalent to M second NMOS tubes M 2 So the third NMOS tube M 3 The drain-source current of (a) is the second NMOS tube M 2 M times the drain-source current of (i.e. mxi) REF 。
The principle of the bias voltage generating module 2 is as follows: and n is a subthreshold slope coefficient of the MOS tube, the typical value of n is 1.2-1.5, and the value of n is related to the technological parameter and the bias voltage of the MOS tube. When the action of the compensation module 3 is not considered, and VDD-V CM ＞100mV、V CM -V GP When the values of > 100mV and n are close to 1, the bias voltage generated by the bias voltage generating module 2 (the gate bias voltage VDD of the NMOS tube, the gate bias voltage V of the PMOS tube GP Common source-drain common mode level V of NMOS tube and PMOS tube CM ) The determined small signal output impedance of NMOS tube of the rear passive self-mixer is approximately equal to (lambda.V) t )/(N 2 ·M·I REF ) The small signal output impedance of the PMOS tube is approximately equal to (beta.V) t )/(P 2 ·M·I REF ) Wherein V is t The thermal voltage, lambda and beta are respectively process correction coefficients and are related to process parameters. By adjusting N 2 、P 2 、M、I REF The value of the (2) can be used for adjusting the small signal output impedance of the NMOS tube and the PMOS tube of the rear passive self-mixer, so as to further adjust the radio frequency input impedance of the rear passive self-mixer when in operation, and preliminarily adjust the radio frequency input impedance to a value required at a certain temperature.
In the compensation module 3, the second NMOS transistor unit includes N 3 NMOS transistors N 3 More than or equal to 1, the second PMOS tube unit comprises P 3 P of PMOS tubes 3 Not less than 1, wherein the first PMOS tube M 1 Is connected with the source electrode and the power supply voltage, and the grid electrode is connected with the first operational amplifier OP 1 Is connected with the output end of OP 1 Is connected with the non-inverting input end of the first PMOS tube M 1 Is V at the drain level of (2) CM，COPY . First operational amplifier OP 1 An NMOS tube M in the bias voltage generation module 2 N2，N2 Is connected to the source of (c). Fourth NMOS tube M 4 The source electrode of the third NMOS transistor M is grounded, the gate electrode of the third NMOS transistor M is grounded, and the third NMOS transistor M is connected with the third NMOS transistor M in the bias voltage generation module 2 3 Is connected with the grid electrode, the drain electrode and the NMOS tube M N3，1 Is connected to the source of the (c). NMOS tube M N3，1 The source electrode of (C) is connected with the fourth NMOS tube M 4 The drain electrode of (2) is connected with NMOS tube M N3，2 Source electrode of NMOS tube M N3，2 The drain electrode of (a) is connected with NMOS tube M N3，3 And so on, NMOS tube M N3，N3-1 The drain electrode of (a) is connected with NMOS tube M N3，N3 Source electrode of NMOS tube M N3，N3 Drain electrode of (C) and first PMOS tube M 1 Is connected to the drain of the transistor. NMOS tube M N3，1 、M N3，2 ......M N3，N3 And then connects their gates to the supply voltage. PMOS tube M P3，1 Drain electrode of (d) and NMOS transistor M N3，1 The source electrode of the PMOS tube M is connected with P3，1 Source electrode of (C) and PMOS tube M P3，2 Drain electrode connection of PMOS tube M P3，2 Source electrode of (C) and PMOS tube M P3，3 Drain electrode connection of PMOS tube M P3，P3-1 Source electrode of (C) and PMOS tube M P3，P3 Drain electrode connection of PMOS tube M P3，1 、M P3，2 ......M P3，P3 The grid electrodes of the (C) are connected together and then are connected with a PMOS tube M in the bias voltage generation module 2 P2，1 Is connected to the gate of the transistor. PMOS tube M P3，P3 Source electrode of (d) and NMOS tube M N3，N3 Is connected to the drain of the transistor. Fifth NMOS tube M 5 Source electrode of the fourth NMOS transistor M is grounded 4 Gate connection, drain and resistor R REF Is connected with the lower end of the resistor R REF Upper end of (2) and PMOS tube M P3，P3 Is connected to the source of the (c). Second operational amplifier OP 2 And a fifth NMOS transistor M 5 Is connected with the drain electrode of the PMOS tube M and the inverting input end of the PMOS tube M P3，1 Is connected with the drain electrode, the output end and the NMOS tube M 6 Is connected to the gate of the transistor. Note the second operational amplifier OP 2 Is V + The inverting input level is V-. NMOS tube M 6 Is grounded, drain and PMOS tube M P3，1 Is connected to the gate of the transistor.
In the compensation module 3, N 3 NMOS tube M N3，1 、M N3，2 ......M N3，N3 And is equal to the NMOS transistor size for frequency conversion in the passive self-mixer of the subsequent stage. P (P) 3 PMOS tubes M P3，1 、M P3，2 ......M P3，P3 The size of the PMOS tube is the same as that of the PMOS tube used for frequency conversion in the rear passive self-mixer. Fourth NMOS tube M 4 Is the same as the second NMOS transistor M in the bias module 1 2 The dimensions of (a) are the same, but the fourth NMOS transistor M 4 Equivalent to N second NMOS tubes M 2 So the fourth NMOS tube M 4 The drain-source current of (a) is the second NMOS tube M 2 N times the drain-source current of (N x I) REF . Fifth NMOS tube M 5 Is the same as the second NMOS transistor M in the bias module 1 2 The fifth NMOS transistor M has the same size 5 Equivalent to P second NMOS tubes M 2 So the fifth NMOS tube M 5 The drain-source current of (a) is the second NMOS tube M 2 P times the drain-source current of (i.e. p×i) REF 。
The working principle of the compensation module 3 is as follows: by a first operational amplifier OP 1 V is the virtual short character of (1) CM ＝V CM，COPY The method comprises the steps of carrying out a first treatment on the surface of the By a second operational amplifier OP 2 V is the virtual short character of (1) + ＝V - 。R REF The resistance value of the resistor is basically unchanged with temperature, process and the like. At this time the resistance R REF The voltage drop over is equal to N 3 NMOS tube M N3，1 、M N3，2 ......M N3，N3 The drain-source voltage drop on is also equal to P 3 PMOS tubes M P3，1 、M P3，2 ......M P3，P3 The source-drain voltage drop on the gate electrode is equal to V CM，COPY -V + . Adjusting resistance R REF Resistance value of (1) and flow-through resistance R REF Is equal to the current value P x I of (2) REF Can adjust V CM，COPY -V + Is a value of (2). When the wake-up receiver works normally, the source-drain voltage drop of the NMOS tube and the PMOS tube for frequency conversion in the post passive self-mixer is very small, and the small signal output impedance is approximately equal to the direct signal output impedanceThe current on-resistance is assumed that the absolute values of drain-source voltages of NMOS tube and PMOS tube used for frequency conversion in the post passive self-mixer are respectively V dsn And V dsp . Then N 3 ＝(V CM，COPY -V + )/V dsn ＝P×I REF ×R REF /V dsn Similarly, can obtain P 3 ＝(V CM，COPY -V + )/V dsp ＝P×I REF ×R REF /V dsp . NMOS tube M at this time N3，1 、M N3，2 ......M N3，N3 And PMOS tube M P3，1 、M P3，2 ......M P3，P3 The working points of the NMOS transistor and the PMOS transistor are respectively equivalent to the working points of the NMOS transistor and the PMOS transistor used for frequency conversion in the post passive self-mixer, so the NMOS transistor M is changed N3，1 、M N3，2 ......M N3，N3 And PMOS tube M P3，1 、M P3，2 ......M P3，P3 The small signal output impedance of the NMOS tube and the PMOS tube for frequency conversion in the post passive self-mixer is equivalent to the small signal output impedance of the NMOS tube and the PMOS tube for frequency conversion in the post passive self-mixer, so that the radio frequency input impedance of the post passive self-mixer is changed. NMOS tube M N3，1 、M N3，2 ......M N3，N3 The sum of the small signal output impedance of (a) is connected in parallel with the PMOS tube M P3，1 、M P3，2 ......M P3，P3 The sum of the small signal output impedances of (2) is P R REF N. When the bias voltage generating module 2 and the compensating module 3 work cooperatively, the small signal output impedance of the NMOS tube for frequency conversion in the rear passive self-mixer is as follows: (2. V) dsn )/(N·I REF ) The small signal output impedance of the PMOS tube is as follows: (2. V) dsp )/(N·I REF ). Second operational amplifier OP 2 Through regulating NMOS tube M 6 To regulate the N flowing through the bias voltage generating module 2 2 NMOS tube M N2，1 、M N2，2 ......M N2，N2 And P 2 PMOS tubes M P2，1 、M P2，2 ......M P2，P2 To regulate V CM And V is equal to GP The value of (2) and the small signal output impedance of the NMOS tube for frequency conversion in the rear passive self-mixer are as follows: (2. V) dsn )/(N·I REF ) The small signal output impedance of the PMOS tube is as follows: (2. V) dsp )/(N·I REF ). Due to V dsn 、V dsp The values of (2) are determined by the design index of the wake-up receiver and the post passive self-mixer, so I is adjusted according to the design index requirement of the wake-up receiver REF The value of N can obtain the optimal small signal output impedance of the NMOS tube and the PMOS tube of the rear passive self-mixer, and further obtain the optimal radio frequency input impedance of the rear passive self-mixer. And due to I REF And N does not change with temperature, process and supply voltage, the compensation module 3 makes the radio frequency input impedance of the post passive self-mixer not change with temperature, process and supply voltage, which indicates that the circuit has strong robustness.
M, N, P, N referred to above, according to an embodiment of the present disclosure 2 、P 2 、N 3 、P 3 、VDD、I REF 、R REF The specific values of (a) can be flexibly selected according to the design index requirement of the wake-up receiver, and the disclosure is not limited thereto.
According to the embodiment of the disclosure, if the MOS tube used for frequency conversion of the rear passive self-mixer only uses an NMOS tube or only uses a PMOS tube, the circuit of the disclosure can still provide bias voltage for the passive self-mixer.
From the above, the technical scheme of the present disclosure has the following advantages and positive effects compared with the prior art:
1. the method and the device enable three bias voltages (namely, the gate bias voltage of the NMOS tube, the gate bias voltage of the PMOS tube and the common source-drain common mode level of the NMOS tube and the PMOS tube) required by the passive self-mixer to be generated in an on-chip mode in a wake-up receiver using the passive self-mixer, and are not provided in a mode of using an off-chip external voltage source.
2. The present disclosure not only generates three bias voltages (namely, gate bias voltage VDD of NMOS tube and gate bias voltage V of PMOS tube) required by passive self-mixer on chip GP Common source-drain common mode level V of NMOS tube and PMOS tube CM，COPY ) And the compensation module 3 is designed. At the position ofUnder the synergistic effect of the bias voltage generation module 2 and the compensation module 3, the radio frequency input impedance of the rear passive self-mixer determined by the bias voltage generated by the bias voltage generation module cannot change along with temperature, process and power supply voltage when the rear passive self-mixer works, and the whole circuit has stronger robustness.
3. The method supports low power supply voltage and extremely low power consumption operation, can achieve nW-level power consumption, and has great significance in extremely low power consumption wake-up receiver design.
4. The present disclosure has significant advantages over the prior art.
More specifically, the present disclosure has significant advantages over the prior art shown in fig. 3:
(1) In the present disclosure, the output levels of the two operational amplifiers are moderate, the requirements for the design of the operational amplifiers are low, and the low-power operational amplifiers with simple structures can be used to save the circuit power consumption. In the prior art shown in FIG. 3, the gate bias voltage V of the NMOS transistor is generated by the circuit G_BN And the gate bias voltage V of the PMOS tube G_BP Are voltages at the output of the operational amplifier, which causes the bias voltage generated to be limited by the voltage swing at the output of the operational amplifier. In some applications or under specific process or temperature conditions, it may be desirable to require V G_BN Is close to the supply voltage and V G_BP This increases the complexity and power consumption of the op-amp design and may cause the circuit to fail due to degradation of the dc operating point of the op-amp, resulting in a large difference between the resulting post-stage differential without the equivalent rf input impedance from the mixer and the required value, ultimately resulting in degradation of the wake-up receiver.
(2) In the present disclosure, the gate bias voltage of the NMOS tube of the post passive self-mixer is the power supply voltage VDD, the minimum gate bias voltage of the PMOS tube can approach 0, and the common source-drain common mode level V of the NMOS tube and the PMOS tube CM，COPY Is about V n ～VDD-|V p I (resistance R REF The pressure drop across it is small, negligible), where V n Is a fourth NMOS tube M 4 Operating in saturationMinimum drain-source voltage, V, required p Is a first PMOS tube M 1 The minimum absolute value drain-source voltage required to operate in saturation allows a large adjustment range of the radio frequency input impedance of the post passive self-mixer determined by the bias voltage generated by the present disclosure, which illustrates that the present disclosure can be applied to passive self-mixers of wake-up receivers with different index requirements compared to the prior art shown in fig. 3.
(3) In the technique shown in fig. 3, the common source-drain common mode level V of the NMOS and PMOS transistors of the passive self-mixer of the subsequent stage C Is provided by an external off-chip voltage source or generated by an on-chip bandgap reference voltage source, which can increase the complexity and power consumption of the circuit. In the present disclosure, the common source-drain common mode level V of NMOS and PMOS transistors of the rear passive self-mixer CM，COPY No external application is needed, and no other circuit module is needed.
In summary, compared with the prior art shown in fig. 3, the bias voltage generated by the present disclosure has a larger adjustment range for the radio frequency input impedance of the post passive self-mixer, wider applicability, stronger robustness, higher yield and smaller power consumption.
The present disclosure has significant advantages over the prior art shown in fig. 4:
(1) The circuit shown in FIG. 4 can also generate the gate bias voltage V of the NMOS transistor of the post passive self-mixer on the chip BN Gate bias voltage V of PMOS tube BP Common source-drain common mode level V of NMOS tube and PMOS tube CM1 Generated by an on-chip bandgap reference source. Because the MOS tube of the passive self-mixer works in a weak inversion state, the small signal output impedance of the NMOS tube of the rear-stage passive self-mixer determined by the bias voltage generated by the circuit is proportional to V t /I B The small signal output impedance of the PMOS tube is also proportional to V t /I B The specific values of which are related to the circuit process parameters. V (V) t Is thermal voltage, V t The amount of charge of the following passive self-mixer, k being boltzmann constant, T being thermodynamic temperature, q being electrons, is determined by the bias voltage, which means that the radio frequency input impedance of the following passive self-mixer is not temperature stable and will be subject toTo the effect of the circuit process. Whereas the radio frequency input impedance of the subsequent passive self-mixer, as determined by the bias voltage generated by the present disclosure, does not vary with temperature and process.
(2) The circuit shown in FIG. 4 can only be implemented by changing I B The method of the (2) can be used for simultaneously adjusting the small signal output impedance of the NMOS tube and the PMOS tube of the rear passive self-mixer, and the NMOS tube and the PMOS tube cannot be separately and independently adjusted, so that the performance of the rear passive self-mixer is limited. In the present disclosure, when the compensation module 3 is adjusted to adjust the small signal output impedance of the post-stage passive self-mixer MOS transistor, the bias voltage generation module 2 can be adjusted to generate N 2 And P 2 The small signal output impedance of the NMOS tube and the PMOS tube are respectively and independently adjusted.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
The circuit for generating a passive self-mixer bias voltage of the present disclosure should be well recognized by those skilled in the art in light of the foregoing description.
In summary, the present disclosure provides a circuit for generating a non-source mixer bias voltage that can provide an NMOS transistor gate bias voltage VDD and a PMOS transistor gate bias voltage V on-chip for a passive self-mixer GP Common source-drain common mode level V of NMOS tube and PMOS tube CM，COPY . The circuit comprises a temperature, process angle and power supply voltage compensation module, so that the radio frequency input impedance of the rear passive self-mixer determined by the generated bias voltage is basically unchanged when the temperature is changed, the process difference is reduced, and the power supply voltage is different, and the whole circuit has stronger robustness. The gate bias voltage of the NMOS tube of the post passive self-mixer provided by the circuit is the power supply voltages VDD and PMOGate bias voltage V of S-tube GP The minimum source-drain common mode level V can be close to 0, and common source-drain common mode level V of NMOS tube and PMOS tube CM，COPY Is about V n ～VDD-|V p I (resistance R REF The pressure drop across it is small, negligible), where V n Is a fourth NMOS tube M 4 Minimum drain-source voltage, V, required to operate in saturation p Is a first PMOS tube M 1 The drain-source voltage with the minimum absolute value required for working in the saturated state can enable the radio frequency input impedance of the rear-stage passive self-mixer to have a large adjustment range, so that the circuit can be applied to passive self-mixers of wake-up receivers with different index requirements. The circuit is suitable for a large temperature range, can adapt to process and power supply voltage differences, and has the advantage of extremely low power consumption (nW magnitude).
It should also be noted that the foregoing describes various embodiments of the present disclosure. These examples are provided to illustrate the technical content of the present disclosure, and are not intended to limit the scope of the claims of the present disclosure. A feature of one embodiment may be applied to other embodiments by suitable modifications, substitutions, combinations, and separations.
It should be noted that in this document, having "an" element is not limited to having a single element, but may have one or more elements unless specifically indicated.
In addition, unless specifically stated otherwise, herein, "first," "second," etc. are used for distinguishing between multiple elements having the same name and not for indicating a level, a hierarchy, an order of execution, or a sequence of processing. A "first" element may occur together with a "second" element in the same component, or may occur in different components. The presence of an element with a larger ordinal number does not necessarily indicate the presence of another element with a smaller ordinal number.
In this context, the so-called feature A "or" (or) or "and/or" (and/or) feature B, unless specifically indicated, refers to the presence of B alone, or both A and B; the feature A "and" (and) or "AND" (and) or "and" (and) feature B, means that the nail and the B coexist; the terms "comprising," "including," "having," "containing," and "containing" are intended to be inclusive and not limited to.
Further, in this document, terms such as "upper," "lower," "left," "right," "front," "back," or "between" are used merely to describe relative positions between elements and are expressly intended to encompass situations of translation, rotation, or mirroring. In addition, in this document, unless specifically indicated otherwise, "an element is on another element" or similar recitation does not necessarily mean that the element contacts the other element.
Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (10)
1. A circuit for generating a passive self-mixer bias voltage, comprising:
a bias module for providing a bias current;
the bias voltage generation module is used for generating gate end bias voltage required by the PMOS tube of the rear passive self-mixer and source-drain common mode level of the NMOS tube and the PMOS tube of the rear passive self-mixer under the action of the bias current; and
the compensation module is used for compensating the bias voltage and the source-drain common mode level, so that the radio frequency input impedance of the rear passive self-mixer cannot change along with temperature, process and power supply voltage changes when the rear passive self-mixer works;
the gate bias voltage required by the NMOS tube of the rear passive self-mixer is directly provided by the power supply voltage VDD.
2. The circuit of claim 1, the bias module comprising:
Reference current source I R For providing bias current I REF The bias current I REF The temperature, the process angle and the power supply voltage are not changed along with the change of the temperature, the process angle and the power supply voltage; and
second NMOS tube M 2 With gate and drain connected together to the on-chip reference current source I R Lower end of the second NMOS tube M 2 The source electrode of the transistor is grounded;
the reference current source I R Is connected to the power supply voltage VDD.
3. The circuit of claim 1, the bias voltage generation module comprising:
a first NMOS transistor unit including multiple NMOS transistors connected in series, wherein the source of the previous NMOS transistor is connected to the drain of the next NMOS transistor, the drain of the first NMOS transistor is connected to the power supply voltage VDD, and the source of the last NMOS transistor is connected to the first node CN 1 The gates of the plurality of NMOS transistors connected in series are commonly connected to a power supply voltage VDD;
the first PMOS tube unit comprises a plurality of PMOS tubes connected in series, wherein the source electrode of the former PMOS tube is connected to the drain electrode of the next PMOS tube, and the drain electrode of the first PMOS tube is connected to the second node CN 2 And is connected to a third NMOS tube M 3 The source of the last PMOS tube is connected to the first node CN 1 The grid electrodes of the PMOS tubes connected in series are commonly connected to a third NMOS tube M 3 A drain electrode of (2);
the third NMOS tube M 3 Gate of (d) and second NMOS transistor M 2 The gate of the third NMOS tube M is connected with 3 Is connected with the source electrode of (C)And (3) ground.
4. The circuit of claim 3, wherein the plurality of serially connected NMOS transistors in the first NMOS transistor unit are the same size and equal to the NMOS transistor size for frequency conversion in the subsequent passive self-mixer; the sizes of the PMOS tubes connected in series in the first PMOS tube unit are the same and are equal to the sizes of the PMOS tubes used for frequency conversion in the rear passive self-mixer; third NMOS tube M 3 The second NMOS tube M in the size and bias module of (a) 2 The third NMOS tube M has the same size 3 Equivalent to M second NMOS tubes M 2 Is connected in parallel to make the third NMOS tube M 3 The drain-source current of (a) is the second NMOS tube M 2 M is more than or equal to 1, which is M times of drain-source current.
5. The circuit of claim 1, the compensation module comprising:
first PMOS tube M 1 The source is connected to the power supply voltage VDD, and the drain is connected to the third node CN 3 ；
First operational amplifier OP 1 The inverting input terminal is connected to the first node CN 1 The non-inverting input terminal is connected to the third node CN 3 An output end connected to the first PMOS tube M 1 A gate electrode of (a);
a second NMOS transistor unit comprising multiple NMOS transistors connected in series, wherein the drain electrode of the previous NMOS transistor is connected to the source electrode of the next NMOS transistor, and the source electrode of the first NMOS transistor is connected to the fourth node CN 4 The drain of the last NMOS transistor is connected to the third node CN 3 The gates of the plurality of NMOS transistors connected in series are commonly connected to a power supply voltage VDD;
fourth NMOS tube M 4 The drain electrode is connected to the fourth node CN4, and the gate electrode is connected to the third NMOS transistor M 3 The source electrode is grounded;
the second PMOS tube unit comprises a plurality of PMOS tubes connected in series, wherein the source electrode of the former PMOS tube is connected to the drain electrode of the next PMOS tube, and the drain electrode of the first PMOS tube is connected to the fourth node CN 4 The source of the last PMOS tube is connected to the third node CN 3 The gates of the PMOS tubes connected in series are commonly connected to the second node CN 2 ；
Resistor R REF The upper end of which is connected to a third node CN 3 ；
Second operational amplifier OP 2 The inverting input terminal is connected to the fourth node CN 4 The non-inverting input terminal is connected to the fifth node CN 5 Is connected back to resistor R REF Is arranged at the lower end of the lower part;
fifth NMOS tube M 5 The drain is connected to the second operational amplifier OP 2 The source terminal is grounded, and the grid electrode is connected to the fourth NMOS tube M 4 A gate electrode of (a); and
sixth NMOS tube M 6 The gate is connected to the second operational amplifier OP 2 Is connected with the drain of the output terminal of the second node CN 2 The source is grounded.
6. The circuit of claim 5, wherein the plurality of NMOS transistors in the second NMOS transistor unit are the same size and equal to the NMOS transistor size for frequency conversion in the passive self-mixer of the subsequent stage, and the plurality of PMOS transistors in the second PMOS transistor unit are the same size and equal to the PMOS transistor size for frequency conversion in the passive self-mixer of the subsequent stage.
7. The circuit for generating a passive self-mixer bias voltage as recited in claim 5, a fourth NMOS transistor M 4 Is of the size and bias module second NMOS tube M 2 The dimensions of (a) are the same, but the fourth NMOS transistor M 4 Equivalent to N second NMOS tubes M 2 In parallel with each other, so that the fourth NMOS transistor M 4 The drain-source current of (a) is the second NMOS tube M 2 N times of drain-source current, N is more than or equal to 1.
8. The circuit for generating a passive self-mixer bias voltage as recited in claim 5, a fifth NMOS transistor M 5 The second NMOS tube M in the size and bias module of (a) 2 The fifth NMOS transistor M has the same size 5 Equivalent to P second NMOS tube M 2 Is connected in parallel to make the fifth NMOS tube M 5 The drain-source current of (a) is the second NMOS tube M 2 P times of drain-source current, and P is more than or equal to 1.
9. The circuit for generating a passive self-mixer bias voltage of claim 5, passed through a first operational amplifier OP 1 Clamping such that the first node CN 1 And the third node CN 3 Is equal in potential.
10. The circuit for generating a passive self-mixer bias voltage as recited in claim 5, passed through a second operational amplifier OP 2 Clamping is performed such that the second operational amplifier OP 2 The non-inverting input terminal and the inverting input terminal of (a) are equal in potential.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116996082A (en) * | 2023-09-26 | 2023-11-03 | 中国科学技术大学 | Differential output wake-up receiver radio frequency circuit |
-
2023
- 2023-02-10 CN CN202310136763.8A patent/CN116107377A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116996082A (en) * | 2023-09-26 | 2023-11-03 | 中国科学技术大学 | Differential output wake-up receiver radio frequency circuit |
| CN116996082B (en) * | 2023-09-26 | 2023-12-05 | 中国科学技术大学 | Differential output wake-up receiver radio frequency circuit |
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