CN116013887A - Semiconductor device and method for manufacturing intermediate structure - Google Patents

Abstract

The invention discloses a semiconductor device and a method for manufacturing an intermediate structure. The semiconductor device includes an interposer configured to be mounted on and electrically coupled to a chuck of a test apparatus, and a first object disposed on a first surface of the interposer and electrically coupled to the interposer. The first object is configured to be analyzed by the test apparatus.

Description

Semiconductor device and method for manufacturing intermediate structure

The priority of U.S. patent application Ser. Nos. 17/508,966 and 17/509,205 (i.e., priority dates "22 th 10 th 2021" and "25 th 10 th 2021"), the contents of which are incorporated herein by reference in their entirety), are claimed.

Technical Field

The present disclosure relates to semiconductor devices having interposer structures, and more particularly, to a semiconductor device having interface structures in semiconductor device testing and a method of testing the same.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are continually shrinking in size to meet the increasing demands for computing power. Accordingly, various problems occur in the process of downsizing, and such problems are increasing. The semiconductor device requires multiple tests (or analyses) during the fabrication process to ensure its quality. The configuration of the semiconductor device for testing is still in need of improvement.

The above description of "prior art" merely provides background art, and it is not admitted that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure.

Disclosure of Invention

The disclosure is directed to a semiconductor device and a method for manufacturing an interposer to solve at least one of the above problems.

One embodiment of the present disclosure provides an interposer that includes an interposer configured to be secured to and electrically coupled with a chuck of a test device, and a first object disposed on a first surface of the interposer and electrically coupled with the interposer. The first object is configured to be analyzed by the test apparatus.

In some embodiments, the interposer includes a fixing unit disposed along the interposer and extending to the chuck to fix the interposer to the chuck.

In some embodiments, the fixing unit is a screw.

In some embodiments, the interposer includes a lower connector disposed on a second surface of the interposer. The second surface is opposite to the first surface and faces the chuck.

In some embodiments, the lower connector and the chuck are electrically coupled by a chuck connector.

In some embodiments, the chuck connector is a pogo pin (pogo pin).

In some embodiments, the chuck connector is a conductive polymer.

In some embodiments, the interposer includes a test pattern configured to electrically couple the first object and the lower connector.

In some embodiments, the test pattern includes at least one through board via disposed along the interposer and in contact with the lower connector.

In some embodiments, the first object includes a package substrate disposed on the first surface of the interposer and electrically coupled to the interposer, a first semiconductor chip disposed on the package substrate, and a wire configured to electrically couple the first semiconductor chip and the package substrate.

In some embodiments, the package substrate and the interposer are electrically coupled by an upper connector.

In some embodiments, the upper connector is a solder ball (solder ball).

In some embodiments, the interposer includes a second semiconductor chip disposed on the package substrate, the second semiconductor chip being proximate to the first semiconductor chip and electrically coupled to the package substrate.

In some embodiments, the first semiconductor chip and the second semiconductor chip have the same layout.

In some embodiments, a thickness of the interposer is greater than a thickness of the package substrate.

Another embodiment of the present disclosure provides an interposer that includes an interposer configured to be secured to and electrically coupled with a chuck of a test device, an upper connector disposed on a first surface and electrically coupled with the interposer, a lower connector disposed on a second surface and electrically coupled with the interposer, and a through-board via disposed in the interposer and configured to electrically couple with the upper connector and the lower connector. The first surface of the interposer is opposite to the second surface of the interposer.

In some embodiments, the interposer includes a first object disposed on and electrically coupled with the upper connector. The first object includes a first semiconductor chip.

Another embodiment of the present disclosure provides a method for manufacturing an interposer, including providing an interposer, forming a through-board via along the interposer, forming a through-board opening along the interposer, forming an upper connector on a first surface of the interposer, and forming a lower connector on a second surface of the interposer.

In some embodiments, the upper connector is a solder ball.

In some embodiments, the interposer includes an epoxy-based material, or imine-triazene (bismaleimide triazine, BT) resin.

Due to the design of the intermediate structure, the internal signal of the object to be detected can be detected, and the high-frequency fault mode and effect analysis can be performed.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure may be more completely understood in consideration of the following description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

Fig. 1 is a cross-sectional view illustrating an interposer of one embodiment of the present disclosure.

Fig. 2 and 3 are close-up cross-sectional views illustrating portions of an interposer according to one embodiment of the present disclosure.

Fig. 4 is a cross-sectional view illustrating an interposer according to another embodiment of the present disclosure.

Fig. 5 is a close-up cross-sectional view illustrating a portion of an interposer according to another embodiment of the present disclosure.

Fig. 6 is a cross-sectional view illustrating an interposer of another embodiment of the present disclosure.

Fig. 7 is a close-up cross-sectional view illustrating a portion of an interposer according to another embodiment of the present disclosure.

Fig. 8 and 9 are cross-sectional views illustrating interposer structures of some embodiments of the present disclosure.

Fig. 10 is a flowchart illustrating a method of fabricating an interposer with a first object according to one embodiment of the present disclosure.

Fig. 11 to 15 are sectional views illustrating a process flow of manufacturing an interposer having the first object according to an embodiment of the present disclosure.

The reference numerals are as follows:

10 preparation method

100 interposer structure

101 interposer

101FS first surface

101SS second surface

103 through board via hole

105 fixing unit

107 first board bonding pad

109 second board bonding pad

109O opening

111 first resist layer

111O opening

113 second resist layer

201 upper connector

203 lower connector

311 first semiconductor chip

313 first bond pad

315 shaping layer

315B bottom portion

315L side portions

315O opening

315U upper part

317 passivation layer

321 second semiconductor chip

323 second bonding pad

401 packaging substrate

403 first adhesive layer

405 second adhesion layer

407 solder ball pad

409 third resist layer

409O opening

411 wire

415 fourth resist layer

415O opening

417 bump

419 underfill layer

501 chuck

503 chuck connector

505 top connecting pin

507 bottom connecting pin

509 casing body

511 elastic connection unit

BO through plate opening

S11, step

S13, step

S15, step

T1 thickness

Thickness T2

W1 width

W2 width

W3 width

W4 width

Z direction

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, many of these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed in the region of the first and second features, such that the first and second features may not be in direct contact. For brevity and clarity, some features may be arbitrarily drawn in various scales and repeated reference numerals and/or letters do not in itself dictate a relationship between the various embodiments and/or configurations discussed. In the drawings, some layers/features may be omitted for simplicity.

Further, for ease of description, spatially relative terms, such as "below", "lower", "above", "upper", and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The elements may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the use of the words "about" and "approximately" to modify the amount of a constituent, component or reactant of the present disclosure refers to a change in the amount of a numerical value that may occur, for example, by typical measurement and liquid handling procedures used to make a concentrate or solution. In addition, inadvertent errors in measurement sequence, differences in the manufacture, source, or purity of the components used to make the composition or perform the method, and the like may also vary. In one embodiment, the terms "about" and "approximately" refer to within 10% of the reported numerical value. In another embodiment, the terms "about" and "approximately" refer to within 5% of the reported numerical value. In another embodiment, the terms "about" and "approximately" refer to values within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

It will be understood that when an element or layer is referred to as being "connected" or "coupled" to another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

It will be understood that, although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by the terms. Unless otherwise indicated, the terms are used merely to distinguish one element from another element. Thus, for example, a first element, first element or first portion discussed below could be termed a second element, second element or second portion without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, when referring to directions, layouts, positions, shapes, sizes, amounts, or other means, terms such as "same", "equal", "planar", or "coplanar", are not necessarily meant to refer to exactly the same directions, layouts, positions, shapes, sizes, amounts, or other means, but to include nearly the same directions, layouts, positions, shapes, sizes, amounts, or other means within an acceptable range of variation that may occur, for example, due to a manufacturing process. The term "substantially" may be used to reflect this meaning. For example, items described as "substantially identical," "substantially equal," or "substantially planar" may be identical, equal, or planar, and may be identical, equal, or planar within acceptable variations, such as may occur as a result of a manufacturing process.

In the description of the present disclosure, it is assumed that an X-Y-Z coordinate system is employed, where X and Y refer to dimensions in a plane parallel to the major surface of the structure and Z refers to dimensions perpendicular to that plane, the features being morphologically aligned when the two features have substantially the same X, Y coordinates.

In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and an electro-optical element, a light-emitting display element, a semiconductor circuit, and an electronic element are included in the category of the semiconductor element.

Fig. 1 is a cross-sectional view illustrating an interposer 100 of one embodiment of the present disclosure. Fig. 2 and 3 are close-up cross-sectional views illustrating portions of an interposer 100 according to one embodiment of the present disclosure. It should be noted that some elements are omitted in the close-up cross-sectional view for clarity.

Referring to fig. 1, an interposer 101 may be provided and may include an epoxy-based material or an imine-triazene (bismaleimide triazine, BT) resin. In some embodiments, the interposer 101 may be a laminate sheet, but is not limited thereto. In some embodiments, the interposer 101 may be a printed circuit board. In some embodiments, interposer 101 may have a thickness T1 of about 0.8 millimeters (mm) to about 1.2 mm. Interposer 101 may include a first surface 101FS and a second surface 101SS that are parallel to each other. In this embodiment, the first surface 101FS may be upward and the second surface 101SS may be downward.

Referring to fig. 1, a plurality of through-board vias 103 may be provided in the interposer 101. For simplicity, clarity and ease of illustration, only one through-plate via 103 is depicted. In some embodiments, the through board vias 103 may be disposed along the interposer 101. That is, the upper surface of the through-board via 103 may be substantially coplanar with the first surface 101 FS. The bottom surface of the through-board via 103 may be substantially coplanar with the second surface 101 SS. In some embodiments, the through-board vias 103 may be disposed in the interposer 101 between the first surface 101FS and the second surface 101 SS. In other words, the top surface of the through-board via 103 may not be substantially coplanar with the first surface 101 FS. The bottom surface of the through-board via 103 may not be substantially coplanar with the second surface 101 SS. In some embodiments, the fabrication technique of the through-board via 103 may be, for example, copper, aluminum, or other suitable metal or metal alloy. In some embodiments, the plurality of through-board vias 103 may be configured in a test pattern. The test pattern may be specified according to an object to be tested.

Referring to fig. 1, interposer 101 may be configured to be mounted on a chuck 501 of a test apparatus. In some embodiments, the test equipment may be automated test equipment including a probe card (probe card). The interposer 101 may be fixed on the chuck 501 by a plurality of fixing units 105. For simplicity, clarity and ease of illustration, only one fixation unit 105 is depicted. The fixing unit 105 may be disposed along the interposer 101 and extend to the chuck 501. In some embodiments, the fixing unit 105 may be a screw.

Referring to fig. 1, a plurality of upper connectors 201 may be disposed on the first surface 101FS of the interposer 101. In some embodiments, the plurality of upper connectors 201 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the plurality of upper connectors 201 may be solder balls.

Referring to fig. 1, a plurality of lower connectors 203 may be disposed on the second surface 101SS of the interposer 101. In some embodiments, the plurality of lower connectors 203 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the plurality of lower connectors 203 may be solder balls. In some embodiments, the plurality of lower connectors 203 may be pogo pins (pogo pins). The lower pins of the plurality of lower connectors 203 may have a shape such as crowned, pyramid crowned, serrated, cup-shaped, conical, spherical, flattened, half-moon, or leaf.

In some embodiments, interposer 101, plurality of through-board vias 103, and plurality of lower connectors 203 are collectively configured as interposer 100. In some embodiments, the interposer 100 may include a plurality of upper connectors 201.

In some embodiments, a first object may be disposed on the interposer 100 and may be electrically coupled to the interposer 100. The first object may be tested by the test apparatus. In some embodiments, the first object being tested may be, for example, a semiconductor component, such as a semiconductor chip. The semiconductor chip may be part of a wafer. Further, the semiconductor chip may be part of a chip stack under test.

Referring to fig. 1, the first object may include a first semiconductor chip 311, a plurality of first bonding pads 313, a molding layer 315, a package substrate 401, a first adhesion layer 403, and a plurality of conductive lines 411. The package substrate 401 may be disposed on the plurality of upper connectors 201 and may be electrically coupled with the plurality of upper connectors 201. In some embodiments, the package substrate 401 may be a laminate, but is not limited thereto. In some embodiments, package substrate 401 may include an epoxy-based material or BT resin. In some embodiments, the package substrate 401 may be a printed circuit board. In some embodiments, package substrate 401 may have a thickness T2 that is less than thickness T1 of interposer 101.

Referring to fig. 1, a first semiconductor chip 311 may be disposed on a package substrate 401 with a first adhesion layer 403 therebetween. The first semiconductor chip 311 may include a substrate and a circuit layer (the substrate and the circuit layer are not shown separately for clarity). The substrate of the first semiconductor chip 311 may be disposed on the first adhesion layer 403. The fabrication technique of the substrate of the first semiconductor chip 311 may be, for example, a bulk (bulk) semiconductor substrate entirely composed of at least one semiconductor material. The semiconductor material may comprise any material or stack of materials having semiconductor properties including, but not limited to, silicon, germanium, silicon-germanium alloys, group III-V compound semiconductors, or group II-VI compound semiconductors.

The circuit layer of the first semiconductor chip 311 may be disposed on the substrate of the first semiconductor chip 311. The circuit layer of the first semiconductor chip 311 may include an interlayer dielectric layer and/or an intermetallic dielectric layer including a plurality of functional blocks (not shown for clarity) and a plurality of conductive features (not shown for clarity). The plurality of functional blocks may be transistors, such as complementary metal oxide semiconductor transistors (CMOS), metal Oxide Semiconductor Field Effect Transistors (MOSFET), fin field effect transistors (FinFET), etc., or combinations thereof. The plurality of functional blocks may cooperate to provide various functions such as logic, input and output (I/O), memory, analog circuitry, and the like. The cooperation of the plurality of functional blocks may be achieved by a plurality of conductive features. In the present disclosure, the configuration of the plurality of functional blocks and the plurality of conductive features may be referred to as a layout of the first semiconductor chip 311.

The plurality of conductive features may include a plurality of conductive plugs, a plurality of conductive lines, a plurality of conductive vias, and a plurality of conductive pads, or other suitable conductive elements. The fabrication technique of the plurality of conductive features may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

The interlayer dielectric and/or the intermetal dielectric may be fabricated using techniques such as silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant (low k) dielectric materials, and the like, or combinations thereof. The low-k dielectric material may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0.

Referring to fig. 1, the first adhesive layer 403 may be a Die Attach Film (DAF), a silver paste, or the like. In some embodiments, the first adhesion layer 403 may also include gold, silver, aluminum oxide, or boron nitride particles.

Referring to fig. 1, a plurality of first bonding pads 313 may be disposed in the first semiconductor chip 311. The top surfaces of the plurality of first bonding pads 313 may be substantially coplanar with the top surface of the first semiconductor chip 311. Specifically, the plurality of first bonding pads 313 may be disposed in the circuit layer of the first semiconductor chip 311. The top surfaces of the plurality of first bonding pads 313 may be substantially coplanar with the top surface of the circuit layer of the first semiconductor chip 311. The fabrication technique of the plurality of first bond pads 313 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

Referring to fig. 1, a plurality of wires 411 may electrically couple a plurality of first bonding pads 313 and a package substrate 401, respectively. The fabrication technique of the plurality of conductive lines 411 may be, for example, gold (Au).

Referring to fig. 1, a molding layer 315 may be disposed on the package substrate 401 to cover the first semiconductor chip 311, the plurality of first bonding pads 313, the first adhesion layer 403, the plurality of conductive lines 411, and the top surface of the package substrate 401. The molding layer 315 may include polybenzoxazole (polybenzoxazole), polyimide (polyimide), benzocyclobutene (benzocyclobutene), an epoxy laminate, or ammonium difluoride (ammonium bifluoride).

Referring to fig. 1, the interposer 101 and the chuck 501 of the test equipment may be electrically coupled by a plurality of chuck connectors 503. For simplicity, clarity and ease of illustration, only one chuck coupler 503 is depicted. In some embodiments, the chuck connector 503 may be a conductive polymer, such as conductive rubber. In some embodiments, the chuck connector 503 may be a pogo pin (pogo pin).

Referring to fig. 1 and 2, in particular, a plurality of first board pads 107 may be disposed on the first surface 101FS of the interposer 101. For simplicity, clarity and ease of illustration, only one first board pad 107 is depicted. The first board pads 107 may be disposed between the through board vias 103 and the upper connector 201. The first board pads 107 may electrically couple the through board vias 103 and the upper connector 201. In some embodiments, the width W2 of the first board pad 107 may be greater than or equal to the width W1 of the through board via 103. The fabrication technique of the first board pads 107 may be, for example, copper or other suitable metal or metal alloy.

Referring to fig. 1 and 2, a first resist layer 111 may be disposed on the first surface 101FS of the interposer 101. The first resist layer 111 may include a plurality of openings 111O to expose the plurality of first board pads 107. In some embodiments, the plurality of first board pads 107 are solder mask-defined pads, and the plurality of openings 111O of the first resist layer 111 are smaller in size than the plurality of first board pads 107 to cover the periphery of the plurality of first board pads 107. The first resist layer 111 may be a film including polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium difluoride.

Referring to fig. 1 and 2, a plurality of ball pads 407 may be disposed on the bottom surface of the package substrate 401. For simplicity, clarity and ease of illustration, only one solder ball pad 407 is depicted. The solder ball pads 407 may be disposed between the package substrate 401 and the upper connector 201. The solder ball pads 407 may electrically couple the package substrate 401 and the upper connector 201. In some embodiments, the width W3 of the ball pad 407 may be the same as the width W1 of the first board pad 107, but is not limited thereto. The ball pad 407 may be fabricated using, for example, copper or other suitable metal or metal alloy.

Referring to fig. 1 and 2, a third resist layer 409 may be disposed on the bottom surface of the package substrate 401. The third resist layer 409 may include a plurality of openings 409O to expose the plurality of ball pads 407. In some embodiments, the plurality of ball pads 407 are solder pads defined by a solder mask, and the plurality of openings 409O of the third resist layer 409 are smaller in size than the plurality of ball pads 407 to cover the periphery of the plurality of ball pads 407. The third resist layer 409 may include polybenzoxazole, polyimide, benzocyclobutene, an epoxy laminate, or ammonium difluoride.

Referring to fig. 1 to 3, a plurality of second board pads 109 may be disposed on the second surface 101SS of the interposer 101. For simplicity, clarity and ease of illustration, only one second board pad 109 is depicted. The second board pads 109 may be disposed between the through board vias 103 and the lower connector 203. The second board pads 109 may electrically couple the through board vias 103 and the lower connectors 203. In some embodiments, the width W4 of the second board pad 109 may be greater than or equal to the width W1 of the through board via 103. The fabrication technique of the second board pads 109 may be, for example, copper or other suitable metal or metal alloy.

Referring to fig. 1 to 3, a second resist layer 113 may be disposed on the second surface 101SS of the interposer 101. The second resist layer 113 may include a plurality of openings 109O to expose a plurality of second board pads 109. In some embodiments, the plurality of second board pads 109 are solder mask defined pads, and the plurality of openings 109O of the second resist layer 113 are smaller in size than the plurality of second board pads 109 to cover the periphery of the plurality of second board pads 109. The second resist layer 113 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium difluoride.

Referring to fig. 1 to 3, although the chuck connector 503 is a pogo pin, the chuck connector 503 may include a top connection pin 505, a bottom connection pin 507, a housing 509, and an elastic connection unit 511. A housing 509 may be disposed between the lower connector 203 and the chuck 501. In some embodiments, the housing 509 may have a hollow cylindrical shape. In some embodiments, the fabrication technique of the housing 509 may be, for example, an insulating material. The spring pins may include springs or spring-like mechanisms that allow contact between the chuck 501 and the lower connector 203 to be less pressurized against the lower connector 203.

Referring to fig. 1 to 3, a top connection pin 505 may be disposed between the lower connector 203 and the housing 509. The top connection pin 505 may have an upper end configured to contact the lower connector 203, and a lower end connected with an upper surface of the housing 509. In some embodiments, the upper end of the top connecting pin 505 may have a shape such as a crown, pyramid crown, serration, cup, cone, sphere, flat, half moon, or blade.

Referring to fig. 1-3, bottom connecting pins 507 may be disposed between the chuck 501 and housing 509 of the test equipment. The bottom connection pins 507 may have lower ends configured to contact the chuck 501 of the test equipment and upper ends connected to the lower surface of the housing 509. In some embodiments, the lower end of the bottom connecting pin 507 may have a shape such as a crown, pyramid crown, serration, cup, cone, sphere, flat, half moon, or blade.

Referring to fig. 1 to 3, an elastic connection unit 511 may be provided in the housing 509. The elastic connection unit 511 may be physically and electrically coupled between the top connection pin 505 and the bottom connection pin 507. In some embodiments, the elastic connection unit 511 may be a spring, such as a tension spring. The elastic connection unit 511 may serve as a shock absorber to reduce stress on the lower connector 203 and as a method of securing the lower connector 203 in contact with the chuck connector 503.

In general, in analyzing a semiconductor device, a circuit board is fixed on the test device, and a chip is fixed on a lower surface of the circuit board, i.e., facing the test device. Due to the arrangement of the circuit board and the chip, the chip is shielded by the circuit board. Therefore, the probes of the probe card cannot directly contact the chip to analyze the internal signals of the chip.

In contrast, in the present disclosure, the presence of the interposer 100 allows the object (e.g., the first semiconductor chip 311) to be completely exposed so that the probe can directly contact the object to analyze the internal signals of the chip. In addition, the interposer 100 and the chuck 501 of the test equipment are electrically coupled only by the lower connector 203 and the chuck connector 503, rather than long cables. Thus, the shorter connection between the test object and the test device allows the first semiconductor chip 311 to be analyzed at high frequencies. Further, the chuck connector 503 is in contact with the lower connector 203 of the interposer 100, not directly with the first semiconductor chip 311 or the package substrate 401. Thus, the chance of damaging the test object by the chuck connector 503 can be avoided or mitigated when placing the object on the test apparatus.

Fig. 4 is a cross-sectional view illustrating another embodiment of the present disclosure. Fig. 5 is a close-up cross-sectional view illustrating a portion of another embodiment of the present disclosure. Elements in fig. 4 that are the same as or similar to elements in fig. 1 have been labeled with similar reference numerals, and duplicate descriptions have been omitted. It should be noted that some elements are omitted in the close-up cross-sectional view for clarity.

Referring to fig. 4, the first semiconductor chip 311 may be bonded to the package substrate 401 through a flip chip (flip chip) bonding process by a plurality of bumps 417. For simplicity, clarity and ease of illustration, only one bump 417 is depicted. The bump 417 is disposed between the package substrate 401 and the first semiconductor chip 311. In some embodiments, bumps 417 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof.

An underfill layer 419 may be disposed between the package substrate 401 and the first semiconductor chip 311 to fill a space between the first semiconductor chip 311 and the package substrate 401. The underfill layer 419 may surround the plurality of bumps 417. In some embodiments, the underfill 419 may be formed by curing an underfill material composed of a cross-linked organic resin and low coefficient of thermal expansion (coefficient of thermal expansion, CTE) inorganic particles (up to 75 wt%). In some embodiments, the underfill material may be formulated with a liquid resin (e.g., an epoxy resin), a hardener (e.g., an anhydride or amine), an elastomer for toughening, a catalyst for promoting crosslinking, and other additives for flow modification and adhesion prior to curing.

The underfill layer 419 may be closely attached to the first semiconductor chip 311, the plurality of bumps 417, and the package substrate 401 such that the underfill layer 419 may redistribute stress and strain from CTE mismatch and mechanical shock throughout the chip area of the first semiconductor chip 311. Accordingly, the generation and growth of cracks in the bump 417 can be prevented or significantly reduced. In addition, the underfill layer 419 may provide protection for the plurality of bumps 417 to improve mechanical integrity of the configuration of the first semiconductor chip 311 and the package substrate 401; therefore, the overall reliability of the arrangement of the first semiconductor chip 311 and the package substrate 401 can also be significantly improved. In addition, the underfill layer 419 may provide partial protection against moisture ingress, as well as other forms of contamination.

Referring to fig. 4, the molding layer 315 may cover the first semiconductor chip 311, the underfill layer 419, and the top surface of the package substrate 401.

Referring to fig. 4 and 5, in particular, a plurality of ball pads 407 may also be disposed on the top surface of the package substrate 401. The solder ball pads 407 may be disposed between the package substrate 401 and the bumps 417. The ball pads 407 may electrically couple the package substrate 401 and the first semiconductor chip 311. A fourth resist layer 415 may be disposed on the top surface of the package substrate 401. The fourth resist layer 415 may include a plurality of openings 415O to expose a plurality of ball pads 407 disposed on the top surface of the package substrate 401. In some embodiments, the plurality of ball pads 407 disposed on the top surface of the package substrate 401 are solder mask defined pads, and the plurality of openings 415O of the fourth resist layer 415 have a smaller size than the plurality of ball pads 407 to cover the periphery of the plurality of ball pads 407. The fourth resist layer 415 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium difluoride.

Referring to fig. 4 and 5, in particular, the lowermost layer portion of the first semiconductor chip 311 may be a passivation layer 317. In some embodiments, the passivation layer 317 may include a polybenzoxazole, polyimide, benzocyclobutene, a benzocyclobutene (benzocyclobutene) deposited film, a solder resist (solder resist) film, or the like, or a combination thereof. Passivation layer 317, which is a polymeric material by fabrication techniques, may have many characteristic attractions such as the ability to fill high aspect ratio (high aspect ratio) openings, a relatively low dielectric constant (about 3.2), a simple deposition process, reduced sharp features or steps of the underlying layer, and high temperature resistance after curing. In other embodiments, passivation layer 317 may be a dielectric layer. The dielectric layer may comprise a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), an oxynitride (e.g., silicon oxynitride), a silicon nitride oxide, a phosphosilicate glass, a borosilicate glass, a borophosphosilicate glass, or the like, or a combination thereof.

It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, in which the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a material containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

Referring to fig. 4 and 5, in particular, a plurality of first bonding pads 313 may be disposed in the passivation layer 317. For simplicity, clarity and ease of illustration, only one first bond pad 313 is depicted. The first bonding pad 313 may be disposed on the bump 417 and electrically coupled with the bump 417. The fabrication technique of the first bond pad 313 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

Fig. 6 is a cross-sectional view illustrating another embodiment of the present disclosure. Fig. 7 is a close-up cross-sectional view illustrating a portion of another embodiment of the present disclosure. Elements in fig. 6 that are the same as or similar to elements in fig. 1 have been labeled with similar reference numerals, and duplicate descriptions have been omitted. It should be noted that some elements are omitted in the close-up cross-sectional view for clarity.

Referring to fig. 6 and 7, the molding layer 315 may include a bottom portion 315B, an upper portion 315U, and a side portion 315L. The upper portion 315U may be disposed on the top surface of the package substrate 401 and may cover the first semiconductor chip 311, the plurality of first bonding pads 313, and the plurality of conductive lines 411. The thickness of the bottom portion 315B may be greater than that of the third resist layer 409, and may cover the third resist layer 409 to prevent moisture intrusion from the bottom surface of the package substrate 401. In addition, the plurality of upper connectors 201 may not directly contact the opening 315O of the bottom portion 315B to avoid contact stress. The side portion 315L may be provided on a sidewall of the package substrate 401, and may integrally connect the upper portion 315U and the bottom portion 315B, thus preventing intrusion of moisture from a side direction.

Fig. 8 and 9 are cross-sectional views illustrating some embodiments of the present disclosure. Elements in fig. 8 and 9 that are the same as or similar to those in fig. 1 have been marked with similar reference numerals, and repetitive descriptions have been omitted.

Referring to fig. 8, the second semiconductor chip 321 may be disposed beside the first semiconductor chip 311. The second semiconductor chip 321 may be fixed on the package substrate 401 through the first adhesive layer 403. A plurality of second bonding pads 323 may be disposed in the second semiconductor chip 321. The top surfaces of the plurality of second bonding pads 323 may be substantially coplanar with the top surfaces of the second semiconductor chips 321. The plurality of wires 411 may electrically couple the plurality of second bonding pads 323 with the package substrate 401. The molding layer 315 may cover the first semiconductor chip 311 and the second semiconductor chip 321.

In some embodiments, the second semiconductor chip 321 may have a different layout than the first semiconductor chip 311. In some embodiments, the second semiconductor chip 321 may have the same layout as the first semiconductor chip 311. In some embodiments, the first semiconductor chip 311 and the second semiconductor chip 321 may provide the same functionality, but are not limited thereto. In some embodiments, the second semiconductor chip 321 may be bonded on the package substrate 401 through a plurality of bumps 417 (shown in fig. 4). With the configuration of the present embodiment, the first semiconductor chip 311 and the second semiconductor chip 321 can be simultaneously subjected to internal probing. The signals of the first semiconductor chip 311 and the second semiconductor chip 321 may be observed at the same time.

Referring to fig. 9, the second semiconductor chip 321 may be disposed above the first semiconductor chip 311. The second semiconductor chip 321 may be fixed on the first semiconductor chip 311 by the second adhesive layer 405. The second adhesive layer 405 may be a chip attach film (DAF), a silver paste, or the like. In some embodiments, the second adhesion layer 405 may also include gold, silver, aluminum oxide, or boron nitride particles. The plurality of wires 411 may electrically couple the plurality of second bonding pads 323 with the package substrate 401. The molding layer 315 may cover the first semiconductor chip 311 and the second semiconductor chip 321.

It should be noted that the terms "formed", "formed" and "forming" may refer to and include any method of creating, building, patterning, implanting or depositing elements, dopants or materials. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching, and wet etching.

It should be noted that the functions or steps noted herein may occur out of the order noted in the figures. For example, two numbers displayed in succession may, in fact, be executed substantially concurrently, or the numbers may sometimes be executed in the reverse order, depending upon the functionality or steps involved.

Fig. 10 is a flow chart illustrating a method 10 of fabricating an interposer 100 having a first object according to one embodiment of the present disclosure. Fig. 11 to 15 are sectional views illustrating a process flow of manufacturing the interposer 100 having the first object according to one embodiment of the present disclosure.

Referring to fig. 10 and 11, in step S11, an interposer 101 may be provided, and a plurality of through-board vias 103 may be formed along the interposer 101.

Referring to fig. 11, the interposer 101 may be a laminate including an epoxy-based material or BT resin. In some embodiments, the through-board vias 103 may be formed by drilling holes in the interposer 101 to form a hole and then electroplating the hole. In some embodiments, the through-plate vias 103 may be configured from vertically aligned micro-vias.

Referring to fig. 10 and 12, in step S13, a plurality of lower connectors 203 may be formed on the second surface 101SS of the interposer 101, and a plurality of through-board openings BO may be formed along the interposer 101.

Referring to fig. 12, the plurality of lower connectors 203 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the plurality of lower connectors 203 may be solder balls. Solder balls may be initially formed by evaporation, plating, printing, solder transfer, or ball placement as a layer of tin having a thickness of about 10 micrometers (μm) to about 100 μm. Once the tin layer is formed on the second surface 101SS of the interposer 101, a reflow process may be performed to mold the tin layer into a desired shape and form solder balls. The plurality of through-plate openings BO may be formed by drilling holes in the interposer 101.

The interposer 101, the plurality of through-board vias 103, and the plurality of lower connectors 203 may be collectively configured as the interposer 100.

Referring to fig. 10 and 13 to 15, in step S15, the first semiconductor chip 311 may be fixed on the package substrate 401, a plurality of upper connectors 201 may be formed on the bottom surface of the package substrate 401, the package substrate 401 may be bonded to the first surface 101FS of the interposer 101 through the plurality of upper connectors 201, and the interposer 101 may be fixed to the chuck 501 of the test device through a plurality of fixing units 105 disposed along the plurality of through-board openings BO and extending to the chuck 501.

Referring to fig. 13, the first semiconductor chip 311 may be fixed on the package substrate 401 through the first adhesive layer 403. Fixing the first semiconductor chip 311 on the package substrate 401 may include the following processes: a layer of adhesive material may be formed under the first semiconductor chip 311. The layer of adhesive material may comprise a flowable material. The first semiconductor chip 311 having the adhesive material layer may be bonded on the package substrate 401. Thereafter, a curing process may be subsequently performed, thereby allowing the adhesive material layer to be crosslinked and cured to form the first adhesive layer 403.

The package substrate 401 may be used to carry the first semiconductor chip 311. The package substrate 401 may be electrically coupled with the plurality of first bonding pads 313 of the first semiconductor chip 311 through the plurality of conductive lines 411. The fabrication technique of the plurality of conductive lines 411 may be, for example, gold (Au). The plurality of wires 411 may be formed by using ultrasonic bonding, thermo-acoustic bonding, or thermo-compression bonding through a ball-wedge process or a wedge-wedge process. The first semiconductor chip 311, the package substrate 401, the first adhesive layer 403, and the plurality of conductive lines 411 together constitute the first object.

Referring to fig. 13, a molding layer 315 may be formed on the package substrate 401 to cover the first semiconductor chip 311 and the plurality of conductive lines 411. The shaping layer 315 may be formed from a shaping compound such as polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium difluoride. The molding layer 315 may be formed by compression molding, transfer molding, liquid encapsulation molding, or the like. For example, the molding compound may be dispensed in liquid form. Subsequently, a curing process is performed to cure the molding compound. The formation of the molding compound may overflow the first semiconductor chip 311 such that the molding compound covers the first semiconductor chip 311. Planarization processes, such as mechanical polishing, chemical mechanical polishing, or other etch-back techniques, may be employed to remove excess portions of the molding compound and provide a substantially planar surface.

Referring to fig. 13, the plurality of upper connectors 201 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the plurality of upper connectors 201 may be solder balls. Solder balls may be initially formed by evaporation, plating, printing, solder transfer, or ball placement as a layer of tin having a thickness of about 10 microns to about 100 microns. Once the tin layer is formed on the bottom surface of the package substrate 401, a reflow process may be performed to mold the tin layer into a desired shape and form solder balls.

In some embodiments, a plurality of upper connectors 201 may be formed on the first surface 101FS of the interposer 101 at the same time as the plurality of lower connectors 203 are formed. In some embodiments, the interposer 100 may include a plurality of upper connectors 201.

Referring to fig. 14, a package substrate 401 may be bonded on the first surface 101FS of the interposer 101. A reflow process may be employed.

Referring to fig. 15, the plurality of fixing units 105 may be vertically aligned into the plurality of through-plate openings BO, respectively. The plurality of fixing units 105 may extend into the chuck 501 of the test apparatus so that the plurality of lower connectors 203 are in contact with the plurality of chuck connectors 503 of the test apparatus.

The positions of the plurality of fixing units 105 may be adjusted to determine the contact stress between the plurality of lower connectors 203 and the plurality of chuck connectors 503. In the process of analyzing the first semiconductor chip 311, the molding layer 315 may be removed. The probes of the probe card may directly contact the top surface of the first semiconductor chip 311 to detect the internal signals of the first semiconductor chip 311.

One embodiment of the present disclosure provides an interposer that includes an interposer configured to be secured to and electrically coupled with a chuck of a test device, and a first object disposed on a first surface of the interposer and electrically coupled with the interposer. The first object is configured to be analyzed by the test apparatus.

Another embodiment of the present disclosure provides an interposer that includes an interposer configured to be secured to and electrically coupled with a chuck of a test device, an upper connector disposed on a first surface and electrically coupled with the interposer, a lower connector disposed on a second surface and electrically coupled with the interposer, and a through-board via disposed in the interposer and configured to electrically couple with the upper connector and the lower connector. The first surface of the interposer is opposite to the second surface of the interposer.

Another embodiment of the present disclosure provides a method for manufacturing an interposer, including providing an interposer, forming a through-board via along the interposer, forming a through-board opening along the interposer, forming an upper connector on a first surface of the interposer, and forming a lower connector on a second surface of the interposer. Due to the design of the interposer 100 of the present disclosure, the internal signal of the first semiconductor chip 311 can be detected, and high-frequency failure mode and impact analysis can be performed.

Due to the design of the interposer 100 of the present disclosure, the internal signal of the first semiconductor chip 311 can be detected, and high-frequency failure mode and effect analysis can be performed.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or future developed that perform the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included within the scope of the present disclosure.

Claims (20)

1. A semiconductor device, comprising:

an interposer configured to be secured to and electrically coupled with a chuck of a test apparatus; and

a first object disposed on a first surface of the interposer and electrically coupled to the interposer;

Wherein the first object is configured to be analyzed by the test apparatus.

2. The semiconductor device of claim 1, further comprising a fixing unit disposed along the interposer and extending to the chuck to fix the interposer on the chuck.

3. The semiconductor device of claim 2, wherein the fixing unit is a screw.

4. The semiconductor device of claim 2, further comprising a lower connector disposed on a second surface of the interposer;

wherein the second surface is opposite to the first surface and faces the chuck.

5. The semiconductor device of claim 4, wherein the lower connector and the chuck are electrically coupled by a chuck connector.

6. The semiconductor device of claim 5, wherein the chuck connector is a spring pin.

7. The semiconductor device of claim 5, wherein the chuck connector is a conductive polymer.

8. The semiconductor device of claim 5, wherein the interposer includes a test pattern configured to electrically couple the first object and the lower connector.

9. The semiconductor device of claim 8, wherein the test pattern comprises at least one through board via disposed along the interposer and in contact with the lower connector.

10. The semiconductor device of claim 9, wherein the first object comprises:

a package substrate disposed on the first surface of the interposer and electrically coupled to the interposer;

a first semiconductor chip disposed on the package substrate; and

a wire is configured to electrically couple the first semiconductor chip and the package substrate.

11. The semiconductor device of claim 10, wherein the package substrate and the interposer are electrically coupled by an upper connector.

12. The semiconductor device of claim 11 wherein the upper connector is solder ball.

13. The semiconductor device of claim 12, further comprising a second semiconductor chip disposed on said package substrate, said second semiconductor chip being proximate to said first semiconductor chip and electrically coupled to said package substrate.

14. The semiconductor device of claim 13, wherein said first semiconductor chip and said second semiconductor chip have the same layout.

15. The semiconductor device of claim 14, wherein a thickness of the interposer is greater than a thickness of the package substrate.

16. A semiconductor device includes

An interposer configured to be secured to and electrically coupled with a chuck of a test apparatus;

An upper connector disposed on a first surface and electrically coupled to the interposer;

a lower connector disposed on a second surface and electrically coupled to the interposer; and

a through board via disposed in the interposer and configured to electrically couple with the upper connector and the lower connector;

wherein the first surface of the interposer is opposite to the second surface of the interposer.

17. The semiconductor device of claim 16, further comprising a first object disposed on and electrically coupled with the upper connector;

wherein the first object includes a first semiconductor chip.

18. A method of making an interposer, comprising;

providing an intermediate board;

forming a through board via along the interposer;

forming a through board opening along the interposer;

forming an upper connector on a first surface of the interposer; and

a lower connector is formed on a second surface of the interposer.

19. The method of manufacturing an interposer of claim 18, wherein the upper connector is solder ball.

20. The method of claim 18, wherein the interposer comprises an epoxy-based material, or an imine-triazene resin.

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