CN116013887A - Semiconductor device and method for fabricating interposer - Google Patents

Abstract

The invention discloses a semiconductor device and a preparation method of an intermediary structure. The semiconductor device includes an interposer and a first object configured to be fixed on and electrically coupled to a chuck of a testing device, the first object is disposed on a first surface of the interposer and electrically coupled with the interposer. The first object is configured to be analyzed by the testing device.

Description

Semiconductor device and method for fabricating interposer

This application claims priority from U.S. Patent Application Nos. 17/508,966 and 17/509,205 (i.e., with priority dates of "October 22, 2021" and "October 25, 2021"), the contents of which are reproduced in full Incorporated herein by reference.

technical field

The present disclosure relates to a semiconductor device with an intermediary structure, in particular to a semiconductor device with an interface structure in semiconductor element testing and a testing method thereof.

Background technique

Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. The dimensions of semiconductor components continue to shrink to meet the demands of ever-increasing computing power. Accordingly, various problems have arisen in the process of downsizing, and such problems have been increasing. During the manufacturing process of semiconductor components, multiple tests (or analyzes) are required to ensure their quality. The configuration of semiconductor devices used for testing still needs to be improved.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject matter of the present disclosure, and does not constitute the prior art of the present disclosure, and the above "prior art" Any description should not be considered as any part of the present invention.

Contents of the invention

The purpose of the present disclosure is to provide a method for fabricating a semiconductor device and an interposer, so as to solve at least one of the above-mentioned problems.

An embodiment of the present disclosure provides an interposer structure, including an interposer configured to be fixed on and electrically coupled to a chuck of a test device, and a first object disposed on a chuck of the interposer. The first surface is electrically coupled with the interposer. The first object is configured to be analyzed by the testing device.

In some embodiments, the intermediary structure includes a fixing unit disposed along the intermediary board and extending to the chuck, so as to fix the intermediary board on the chuck.

In some embodiments, the fixing unit is a screw.

In some embodiments, the interposer includes a lower connector disposed on a second surface of the interposer. The second surface is opposite to the first surface and faces the chuck.

In some embodiments, the lower connector and the chuck are electrically coupled via a chuck connector.

In some embodiments, the chuck connector is a pogo pin.

In some embodiments, the chuck connector is a conductive polymer.

In some embodiments, the interposer includes a test pattern configured to electrically couple the first object and the lower connector.

In some embodiments, the test pattern includes at least one through-board hole disposed along the interposer and contacting the lower connector.

In some embodiments, the first object includes a packaging substrate disposed on the first surface of the interposer and electrically coupled with the interposer, a first semiconductor chip disposed on the packaging substrate, and a wire , configured to electrically couple the first semiconductor chip and the packaging substrate.

In some embodiments, the package substrate and the interposer are electrically coupled through an upper connector.

In some embodiments, the upper connector is a solder ball.

In some embodiments, the intermediary structure includes a second semiconductor chip disposed on the packaging substrate, the second semiconductor chip is adjacent to the first semiconductor chip, and is electrically coupled to the packaging substrate.

In some embodiments, the first semiconductor chip and the second semiconductor chip have the same layout.

In some embodiments, a thickness of the interposer is greater than a thickness of the packaging substrate.

Another embodiment of the present disclosure provides an interposer comprising an interposer configured to be secured to and electrically coupled to a chuck of a test device, an upper connector disposed on a first surface and electrically coupled with the interposer, a lower connector disposed on a second surface and electrically coupled with the interposer, and a through-board via disposed in the interposer and configured to communicate with the upper connector and the lower The connectors are electrically coupled. The first surface of the interposer is opposite to the second surface of the interposer.

In some embodiments, the interposer includes a first object disposed on and electrically coupled to the upper connector. The first object includes a first semiconductor chip.

Another embodiment of the present disclosure provides a method for manufacturing an interposer structure, including providing an interposer, forming a through-plate through hole along the interposer, forming a through-plate opening along the interposer, and forming a through-plate opening on a first surface of the interposer. An upper connector is formed on the top, and a lower connector is formed on a second surface of the interposer.

In some embodiments, the upper connector is a solder ball.

In some embodiments, the interposer includes an epoxy-based material, or bismaleimide triazine (BT) resin.

Due to the design of the intermediary structure of the present disclosure, the internal signal of the object under test can be detected, and high-frequency failure mode and effect analysis can be performed.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages forming the subject of claims of the present disclosure will be described hereinafter. Those skilled in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which this disclosure pertains should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure as defined by the appended claims.

Description of drawings

A more complete understanding of the disclosure of the present invention can be obtained when considering the drawings with reference to the embodiments and the claims, in which like reference numerals refer to like elements.

FIG. 1 is a cross-sectional view illustrating an interposer structure according to one embodiment of the present disclosure.

2 and 3 are close-up cross-sectional views illustrating a portion of an interposer according to one embodiment of the present disclosure.

FIG. 4 is a cross-sectional view illustrating an interposer structure according to another embodiment of the present disclosure.

5 is a close-up cross-sectional view illustrating a portion of an interposer according to another embodiment of the present disclosure.

FIG. 6 is a cross-sectional view illustrating an interposer according to another embodiment of the present disclosure.

7 is a close-up cross-sectional view illustrating a portion of an interposer according to another embodiment of the present disclosure.

8 and 9 are cross-sectional views illustrating interposer structures of some embodiments of the present disclosure.

FIG. 10 is a flowchart illustrating a method for fabricating an interposer with a first object according to an embodiment of the present disclosure.

11 to 15 are cross-sectional views illustrating a fabrication process of an interposer with the first object according to an embodiment of the present disclosure.

The reference signs are as follows:

10: Preparation method

100: Intermediary structure

101:Intermediate board

101FS: First Surface

101SS: Second Surface

103: through hole

105: fixed unit

107: Welding pad of the first board

109:Second board welding pad

109O: opening

111: the first resist layer

111O: opening

113: Second resist layer

201: Upper connector

203: Lower connector

311: The first semiconductor chip

313:First Bonding Pad

315: Forming layer

315B: Bottom part

315L: side part

315O: opening

315U: upper part

317: passivation layer

321: the second semiconductor chip

323:Second bonding pad

401: package substrate

403: The first adhesion layer

405: the second adhesion layer

407: Solder ball pad

409: The third resist layer

409O: opening

411: wire

415: the fourth resist layer

415O: opening

417: Bump

419: Bottom fill layer

501: Chuck

503: chuck connector

505: Top connection pin

507: Bottom connection pin

509: shell

511: elastic connection unit

BO: through plate opening

S11: step

S13: step

S15: step

T1: Thickness

T2: Thickness

W1: width

W2: width

W3: width

W4: width

Z: Direction

Detailed ways

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, many of the descriptions are examples only and are not intended to be limiting. For example, the description below that a first feature is formed "over" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which Embodiments in which additional features may be formed within the range of the first feature and the second feature, so that the first feature may not be in direct contact with the second feature. For brevity and clarity, some features may be drawn arbitrarily at different scales, and parameter words/or letters repeated, do not in themselves determine the relationship between some embodiments and/or configurations discussed. In the drawings, some layers/features may be omitted for simplicity.

Additionally, for ease of illustration, spaces such as "beneath", "below", "lower", "above", "upper" may be used herein Relative relationship terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The elements may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein translated accordingly.

It should be noted that the use of the words "about", "approximately" to modify quantities of ingredients, components or reactants in the present disclosure means that variations in numerical quantities may occur, for example, by typical measurements used to manufacture concentrates or solutions and liquid handlers. In addition, inadvertent errors in measurement sequences, differences in manufacture, source or purity of ingredients used in making compositions or performing methods, etc. may also produce variations. In one embodiment, the terms "about" and "approximately" refer to within 10% of the reported value. In another embodiment, the terms "about" and "approximately" mean within 5% of the reported value. In another embodiment, the terms "about" and "about" refer to within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

It will be understood that although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by the terms. Unless stated otherwise, terms are only used to distinguish one element from another. Thus, for example, a first element, a first element or a first section discussed below could be termed a second element, a second element or a second section without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, terms such as "same", "equal", "planar" or "coplanar" are used herein when referring to orientation, layout, position, shape, size, quantity or other measures, not necessarily means exactly the same orientation, arrangement, position, shape, size, quantity or other measure, but means, within acceptable variations that may occur, for example, due to the manufacturing process, including nearly the same orientation, arrangement, position , shape, size, quantity or other measure. The term "substantially" may be used to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially flat" could be identical, equal, or flat, or the same, equal, or flat within acceptable variations, such as Variations may occur due to the manufacturing process.

In the description of the present disclosure, an X-Y-Z coordinate system is assumed, where X and Y refer to dimensions in a plane parallel to the main surface of the structure, and Z refers to a dimension perpendicular to that plane. When two features have substantially the same These features are topographically aligned when the X, Y coordinates of the

In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor properties, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

FIG. 1 is a cross-sectional view illustrating an interposer 100 according to one embodiment of the present disclosure. 2 and 3 are close-up cross-sectional views illustrating a portion of an interposer 100 according to one embodiment of the present disclosure. It should be noted that some elements have been omitted in the close-up section view for clarity.

Referring to FIG. 1 , an interposer 101 may be provided, which may include an epoxy-based material or bismaleimide triazine (BT) resin. In some embodiments, the interposer 101 may be a laminate sheet, but is not limited thereto. In some embodiments, the interposer 101 may be a printed circuit board. In some embodiments, the interposer 101 may have a thickness T1 of about 0.8 millimeters (mm) to about 1.2 mm. The interposer 101 may include a first surface 101FS and a second surface 101SS parallel to each other. In this embodiment, the first surface 101FS may face upward, and the second surface 101SS may face downward.

Referring to FIG. 1 , a plurality of through-board through holes 103 may be disposed in the interposer 101 . For simplicity, clarity and convenience of description, only one through-board through-hole 103 is described. In some embodiments, the through-board holes 103 may be disposed along the interposer 101 . That is, the upper surface of the through-board hole 103 may be substantially coplanar with the first surface 101FS. The bottom surface of the through-board hole 103 may be substantially coplanar with the second surface 101SS. In some embodiments, the through-hole plate via 103 may be disposed in the interposer 101 between the first surface 101FS and the second surface 101SS. In other words, the top surface of the through-board hole 103 may not be substantially coplanar with the first surface 101FS. The bottom surface of the through-board hole 103 may not be substantially coplanar with the second surface 101SS. In some embodiments, the fabrication technology of the through-board via 103 may be, for example, copper, aluminum or other suitable metals or metal alloys. In some embodiments, a plurality of through-board vias 103 may be configured as a test pattern. The test pattern can be specified according to a DUT.

Referring to FIG. 1 , an interposer 101 may be configured to be fixed on a chuck 501 of a test apparatus. In some embodiments, the test equipment may be automated test equipment including probe cards. The interposer 101 can be fixed on the chuck 501 through a plurality of fixing units 105 . For simplicity, clarity and ease of illustration, only one fixed unit 105 is depicted. The fixing unit 105 may be disposed along the interposer 101 and extend to the chuck 501 . In some embodiments, the fixing unit 105 may be a screw.

Referring to FIG. 1 , a plurality of upper connectors 201 may be disposed on the first surface 101FS of the interposer 101 . In some embodiments, the plurality of upper connectors 201 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the plurality of upper connectors 201 may be solder balls.

Referring to FIG. 1 , a plurality of lower connectors 203 may be disposed on the second surface 101SS of the interposer 101 . In some embodiments, the plurality of lower connectors 203 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, the plurality of lower connectors 203 may be solder balls. In some embodiments, plurality of lower connectors 203 may be pogo pins. The lower pins of the plurality of lower connectors 203 may have, for example, a crown, a pyramid crown, a saw-tooth shape, a cup shape, a cone shape, a ball shape, a flat shape, a half-moon shape, or a blade shape.

In some embodiments, the interposer 101 , the plurality of through-board vias 103 and the plurality of lower connectors 203 are jointly configured to form the interposer structure 100 . In some embodiments, interposer 100 may include a plurality of upper connectors 201 .

In some embodiments, a first object may be disposed on the interposer 100 and electrically coupled to the interposer 100 . The first object can be tested by the testing device. In some embodiments, the first object under test may be, for example, a semiconductor component, such as a semiconductor chip. The semiconductor chip may be part of a wafer. Furthermore, the semiconductor chip can be part of a chip stack to be tested.

Referring to FIG. 1 , the first object may include a first semiconductor chip 311 , a plurality of first bonding pads 313 , a molding layer 315 , a packaging substrate 401 , a first adhesion layer 403 and a plurality of wires 411 . The package substrate 401 may be disposed on the plurality of upper connectors 201 and may be electrically coupled with the plurality of upper connectors 201 . In some embodiments, the packaging substrate 401 may be a laminate, but is not limited thereto. In some embodiments, package substrate 401 may include an epoxy-based material or BT resin. In some embodiments, package substrate 401 may be a printed circuit board. In some embodiments, the packaging substrate 401 may have a thickness T2 that is smaller than the thickness T1 of the interposer 101 .

Referring to FIG. 1 , a first semiconductor chip 311 may be disposed on a package substrate 401 with a first adhesion layer 403 therebetween. The first semiconductor chip 311 may include a substrate and a circuit layer (for clarity, the substrate and the circuit layer are not shown separately). The base of the first semiconductor chip 311 may be disposed on the first adhesion layer 403 . The fabrication technology of the substrate of the first semiconductor chip 311 may be, for example, a bulk semiconductor substrate completely composed of at least one semiconductor material. The semiconductor material may include any material or stack of materials having semiconductor properties, including but not limited to silicon, germanium, silicon-germanium alloys, III-V compound semiconductors, or II-VI compound semiconductors.

The circuit layer of the first semiconductor chip 311 may be disposed on the substrate of the first semiconductor chip 311 . The circuit layer of the first semiconductor chip 311 may include an interlayer dielectric layer and/or an intermetal dielectric layer, including a plurality of functional blocks (not shown for clarity) and a plurality of conductive features (not shown for clarity) . The plurality of functional blocks may be transistors, such as Complementary Metal Oxide Semiconductor Transistors (CMOS), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Fin Field Effect Transistors (FinFETs), etc., or combinations thereof. The multiple functional blocks can cooperate to provide various functions, such as logic, input and output (I/O), memory, analog circuits, and the like. The cooperation of the multiple functional blocks can be realized through multiple conductive features. In the present disclosure, the configuration of the plurality of functional blocks and the plurality of conductive features may be referred to as a layout of the first semiconductor chip 311 .

The plurality of conductive features may include a plurality of conductive plugs, a plurality of conductive lines, a plurality of conductive holes, and a plurality of conductive pads, or other suitable conductive elements. The fabrication technology of the plurality of conductive features can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (such as nitride titanium), transition metal aluminides, or combinations thereof.

The fabrication technology of the interlayer dielectric layer and/or the intermetal dielectric layer can be, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric Constant (low-k) dielectric materials, etc., or combinations thereof. The low-k dielectric material may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0.

Referring to FIG. 1, the first adhesion layer 403 may be a die attach film (DAF), silver glue or the like. In some embodiments, the first adhesion layer 403 may also include gold, silver, aluminum oxide or boron nitride particles.

Referring to FIG. 1 , a plurality of first bonding pads 313 may be disposed in the first semiconductor chip 311 . Top surfaces of the plurality of first bonding pads 313 may be substantially coplanar with the top surface of the first semiconductor chip 311 . Specifically, a plurality of first bonding pads 313 may be disposed in the circuit layer of the first semiconductor chip 311 . Top surfaces of the plurality of first bonding pads 313 may be substantially coplanar with the top surface of the circuit layer of the first semiconductor chip 311 . The manufacturing technology of the plurality of first bonding pads 313 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (for example, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (eg, titanium nitride), transition metal aluminides, or combinations thereof.

Referring to FIG. 1 , a plurality of wires 411 may respectively electrically couple the plurality of first bonding pads 313 with the package substrate 401 . The fabrication technology of the plurality of wires 411 can be, for example, gold (Au).

Referring to FIG. 1 , the molding layer 315 may be disposed on the packaging substrate 401 to cover the first semiconductor chip 311 , the plurality of first bonding pads 313 , the first adhesion layer 403 , the plurality of wires 411 and the top surface of the packaging substrate 401 . The molding layer 315 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride.

Referring to FIG. 1 , the interposer 101 and the chuck 501 of the test device may be electrically coupled through a plurality of chuck connectors 503 . For simplicity, clarity and ease of illustration, only one chuck connector 503 is depicted. In some embodiments, the chuck connector 503 may be a conductive polymer, such as conductive rubber. In some embodiments, chuck connector 503 may be a pogo pin.

Referring to FIGS. 1 and 2 , specifically, a plurality of first board pads 107 may be disposed on the first surface 101FS of the interposer 101 . For simplicity, clarity and ease of illustration, only one first board pad 107 is depicted. The first board pad 107 may be disposed between the through-board hole 103 and the upper connector 201 . The first board pad 107 may electrically couple the through-board via 103 and the upper connector 201 . In some embodiments, the width W2 of the first board pad 107 may be greater than or equal to the width W1 of the through-board hole 103 . The fabrication technology of the first board pad 107 may be, for example, copper or other suitable metals or metal alloys.

Referring to FIGS. 1 and 2 , a first resist layer 111 may be disposed on the first surface 101FS of the interposer 101 . The first resist layer 111 may include a plurality of openings 111O to expose the plurality of first board pads 107 . In some embodiments, the plurality of first board pads 107 are solder-mask-defined solder pads, and the plurality of openings 1110 of the first resist layer 111 are smaller in size than the plurality of first board pads. welding pads 107 to cover the periphery of the plurality of welding pads 107 of the first board. The first resist layer 111 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride.

Referring to FIGS. 1 and 2 , a plurality of solder ball pads 407 may be disposed on the bottom surface of the package substrate 401 . For simplicity, clarity and ease of illustration, only one solder ball pad 407 is depicted. Solder ball pads 407 may be disposed between the package substrate 401 and the upper connector 201 . The solder ball pads 407 may electrically couple the package substrate 401 and the upper connector 201 . In some embodiments, the width W3 of the solder ball pad 407 may be the same as the width W1 of the first board pad 107 , but is not limited thereto. The fabrication technology of the solder ball pad 407 may be, for example, copper or other suitable metal or metal alloy.

Referring to FIGS. 1 and 2 , a third resist layer 409 may be disposed on the bottom surface of the package substrate 401 . The third resist layer 409 may include a plurality of openings 409O to expose the plurality of solder ball pads 407 . In some embodiments, the plurality of solder ball pads 407 are solder pads defined by a solder resist layer, and the plurality of openings 4090 of the third resist layer 409 are smaller in size than the plurality of solder ball pads 407 to cover the plurality of solder balls the perimeter of the pad 407 . The third resist layer 409 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride.

Referring to FIGS. 1 to 3 , a plurality of second board pads 109 may be disposed on the second surface 101SS of the interposer 101 . For simplicity, clarity and convenience of illustration, only one second board pad 109 is described. The second board pad 109 may be disposed between the through-board hole 103 and the lower connector 203 . The second board pad 109 may electrically couple the through-board via 103 and the lower connector 203 . In some embodiments, the width W4 of the second board pad 109 may be greater than or equal to the width W1 of the through-board hole 103 . The fabrication technology of the second board pad 109 may be, for example, copper or other suitable metal or metal alloy.

Referring to FIGS. 1 to 3 , a second resist layer 113 may be disposed on the second surface 101SS of the interposer 101 . The second resist layer 113 may include a plurality of openings 109O to expose the plurality of second board pads 109 . In some embodiments, the plurality of second board pads 109 are pads defined by a solder resist layer, and the plurality of openings 1090 of the second resist layer 113 are smaller in size than the plurality of second board pads 109 to cover more The periphery of the second board pad 109. The second resist layer 113 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride.

Referring to FIGS. 1 to 3 , although the chuck connector 503 is a pogo pin, the chuck connector 503 may include a top connection pin 505 , a bottom connection pin 507 , a housing 509 and an elastic connection unit 511 . The housing 509 may be disposed between the lower connector 203 and the chuck 501 . In some embodiments, housing 509 may have a hollow cylindrical shape. In some embodiments, the fabrication technique of the housing 509 may be, for example, an insulating material. The pogo pins may include a spring or a spring-like mechanism such that the contact between the chuck 501 and the lower connector 203 exerts less pressure on the lower connector 203 .

Referring to FIGS. 1 to 3 , a top connection pin 505 may be disposed between the lower connector 203 and the case 509 . The top connection pin 505 may have an upper end configured to contact the lower connector 203 , and a lower end connected to the upper surface of the housing 509 . In some embodiments, the upper end of the top connecting pin 505 may have a shape such as a crown, a pyramidal crown, a sawtooth, a cup, a cone, a ball, a flat, a half-moon, or a blade.

Referring to FIGS. 1 to 3 , a bottom connection pin 507 may be disposed between the chuck 501 and the housing 509 of the testing device. The bottom connection pin 507 may have a lower end configured to contact the chuck 501 of the test device, and an upper end connected to the lower surface of the housing 509 . In some embodiments, the lower end of the bottom connecting pin 507 may have a shape such as a crown, a pyramid crown, a sawtooth, a cup, a cone, a ball, a flat, a half-moon, or a blade.

Referring to FIGS. 1 to 3 , an elastic connection unit 511 may be disposed in the housing 509 . The elastic connection unit 511 can physically and electrically couple between the top connection pin 505 and the bottom connection pin 507 . In some embodiments, the elastic connection unit 511 may be a spring, such as an extension spring. The elastic connection unit 511 can be used as a shock absorber to reduce the stress on the lower connector 203 and as a method to ensure the contact between the lower connector 203 and the chuck connector 503 .

Usually, when analyzing a semiconductor device, a circuit board is fixed on the test device, and a chip is fixed on the lower surface of the circuit board, ie facing the test device. Due to the configuration of the board and chip, the chip is hidden by the board. Therefore, the probes of the probe card cannot directly contact the chip to analyze the internal signal of the chip.

In contrast, in the present disclosure, the presence of the interposer structure 100 completely exposes the object under test (eg, the first semiconductor chip 311 ), so that the probes can directly contact the object under test to analyze internal signals of the chip. Furthermore, the interposer 100 and the chuck 501 of the test device are electrically coupled only through the lower connector 203 and the chuck connector 503 instead of a long cable. Therefore, the shorter connection between the DUT and the testing device enables the first semiconductor chip 311 to be analyzed at high frequencies. In addition, the chuck connector 503 contacts the lower connector 203 of the interposer 100 instead of directly contacting the first semiconductor chip 311 or the packaging substrate 401 . Therefore, when an object is placed on the test device, the chance of the chuck connector 503 damaging the object under test can be avoided or mitigated.

FIG. 4 is a cross-sectional view illustrating another embodiment of the present disclosure. 5 is a close-up cross-sectional view illustrating a portion of another embodiment of the present disclosure. Elements in FIG. 4 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols, and repeated descriptions have been omitted. It should be noted that some elements have been omitted in the close-up section view for clarity.

Referring to FIG. 4, the first semiconductor chip 311 may be bonded to the packaging substrate 401 through a plurality of bumps 417 through a flip chip bonding process. For simplicity, clarity and ease of illustration, only one bump 417 is depicted. Bumps 417 are disposed between the package substrate 401 and the first semiconductor chip 311 . In some embodiments, bumps 417 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof.

An underfill layer 419 may be disposed between the package substrate 401 and the first semiconductor chip 311 to fill a space between the first semiconductor chip 311 and the package substrate 401 . An underfill layer 419 may surround the plurality of bumps 417 . In some embodiments, the underfill layer 419 can be formed by curing an underfill material made of cross-linked organic resin and inorganic particles with a low coefficient of thermal expansion (CTE). (up to 75% by weight) composition. In some embodiments, the underfill material may be cured with liquid resins (such as epoxy resins), hardeners (such as anhydrides or amines), elastomers for toughening, catalysts for promoting crosslinking, and Formulated with other additives for flow modification and adhesion.

The underfill layer 419 can be tightly attached to the first semiconductor chip 311, the plurality of bumps 417, and the packaging substrate 401, so that the underfill layer 419 can redistribute the components from the CTE mismatch and the entire chip area of the first semiconductor chip 311. Stress and strain of mechanical shock. Therefore, the generation and growth of cracks in the bump 417 can be prevented or significantly reduced. In addition, the underfill layer 419 can provide protection for the plurality of bumps 417 to improve the mechanical integrity of the configuration of the first semiconductor chip 311 and the packaging substrate 401; thus, the overall reliability of the configuration of the first semiconductor chip 311 and the packaging substrate 401 Sexuality can also be significantly improved. Additionally, the underfill layer 419 may provide partial protection from moisture ingress, and other forms of contamination.

Referring to FIG. 4 , the molding layer 315 may cover the top surfaces of the first semiconductor chip 311 , the underfill layer 419 and the package substrate 401 .

Referring to FIG. 4 and FIG. 5 , specifically, a plurality of solder ball pads 407 may also be disposed on the top surface of the packaging substrate 401 . Solder ball pads 407 may be disposed between the package substrate 401 and the bumps 417 . The solder ball pads 407 can electrically couple the package substrate 401 and the first semiconductor chip 311 . The fourth resist layer 415 may be disposed on the top surface of the package substrate 401 . The fourth resist layer 415 may include a plurality of openings 415O to expose the plurality of solder ball pads 407 disposed on the top surface of the package substrate 401 . In some embodiments, the plurality of solder ball pads 407 disposed on the top surface of the package substrate 401 are solder pads defined by a solder resist layer, and the size of the plurality of openings 4150 in the fourth resist layer 415 is smaller than that of the plurality of solder ball pads 407 to cover the perimeter of the plurality of solder ball pads 407 . The fourth resist layer 415 may include polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride.

Referring to FIGS. 4 and 5 , specifically, the lowermost portion of the first semiconductor chip 311 may be a passivation layer 317 . In some embodiments, the passivation layer 317 may include polybenzoxazole, polyimide, benzocyclobutene, benzocyclobutene build-up film, solder resist film, etc., or a combination thereof . The passivation layer 317, which is a polymer material by fabrication technology, can have many attractive properties, such as the ability to fill openings with high aspect ratios, relatively low dielectric constant (about 3.2), simple deposition process , reduction of sharp features or steps on the bottom layer, and high temperature resistance after curing. In some other embodiments, the passivation layer 317 may be a dielectric layer. The dielectric layer may include nitrides (such as silicon nitride), oxides (such as silicon oxide), oxynitrides (such as silicon oxynitride), silicon oxide nitride, phosphosilicate glass, borosilicate glass, Borodoped phosphosilicate glass, or the like, or combinations thereof.

It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than that of nitrogen. Silicon oxynitride refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than that of oxygen.

Referring to FIGS. 4 and 5 , specifically, a plurality of first bonding pads 313 may be disposed in the passivation layer 317 . For simplicity, clarity and convenience of description, only one first bonding pad 313 is described. The first bonding pad 313 may be disposed on the bump 417 and electrically coupled with the bump 417 . The manufacturing technology of the first bonding pad 313 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (such as nitrogen titanium oxide), transition metal aluminides, or combinations thereof.

FIG. 6 is a cross-sectional view illustrating another embodiment of the present disclosure. 7 is a close-up cross-sectional view illustrating a portion of another embodiment of the present disclosure. Elements in FIG. 6 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols, and repeated descriptions have been omitted. It should be noted that some elements have been omitted in the close-up section view for clarity.

Referring to FIGS. 6 and 7 , the shaping layer 315 may include a bottom portion 315B, an upper portion 315U, and side portions 315L. The upper portion 315U may be disposed on the top surface of the package substrate 401 and may cover the first semiconductor chip 311 , the plurality of first bonding pads 313 and the plurality of wires 411 . The thickness of the bottom portion 315B may be greater than that of the third resist layer 409 and may cover the third resist layer 409 to prevent moisture from intruding from the bottom surface of the package substrate 401 . In addition, the plurality of upper connectors 201 may not directly contact the opening 315O of the bottom portion 315B to avoid contact stress. The side part 315L may be disposed on a side wall of the package substrate 401, and may integrally connect the upper part 315U and the bottom part 315B, thus preventing intrusion of moisture from a side direction.

8 and 9 are cross-sectional views illustrating some embodiments of the present disclosure. Elements in FIGS. 8 and 9 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols, and repeated descriptions have been omitted.

Referring to FIG. 8 , the second semiconductor chip 321 may be disposed beside the first semiconductor chip 311 . The second semiconductor chip 321 can be fixed on the packaging substrate 401 through the first adhesive layer 403 . A plurality of second bonding pads 323 may be disposed in the second semiconductor chip 321 . Top surfaces of the plurality of second bonding pads 323 may be substantially coplanar with the top surface of the second semiconductor chip 321 . The plurality of wires 411 can electrically couple the plurality of second bonding pads 323 to the package substrate 401 . The molding layer 315 may cover the first semiconductor chip 311 and the second semiconductor chip 321 .

In some embodiments, the second semiconductor chip 321 may have a different layout than the first semiconductor chip 311 . In some embodiments, the second semiconductor chip 321 may have the same layout as the first semiconductor chip 311 . In some embodiments, the first semiconductor chip 311 and the second semiconductor chip 321 may provide the same functionality, but are not limited thereto. In some embodiments, the second semiconductor chip 321 may be bonded to the package substrate 401 through a plurality of bumps 417 (as shown in FIG. 4 ). Through the configuration of this embodiment, internal detection can be performed on the first semiconductor chip 311 and the second semiconductor chip 321 at the same time. Signals of the first semiconductor chip 311 and the second semiconductor chip 321 may be observed simultaneously.

Referring to FIG. 9 , the second semiconductor chip 321 may be disposed over the first semiconductor chip 311 . The second semiconductor chip 321 may be fixed on the first semiconductor chip 311 through the second adhesive layer 405 . The second adhesion layer 405 may be a die attach film (DAF), silver paste, or the like. In some embodiments, the second adhesion layer 405 may also include gold, silver, aluminum oxide or boron nitride particles. The plurality of wires 411 can electrically couple the plurality of second bonding pads 323 with the package substrate 401 . The molding layer 315 may cover the first semiconductor chip 311 and the second semiconductor chip 321 .

It should be noted that the terms "forming", "formed" and "form" can refer to and include creating, building, patterning, implanting or depositing elements, dopants or materials any method. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

It should be noted that the functions or steps noted therein may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently, or may sometimes be executed in the reverse order, depending upon the functions or steps involved.

FIG. 10 is a flowchart illustrating a method 10 of fabricating an interposer 100 having a first object according to an embodiment of the present disclosure. 11 to 15 are cross-sectional views illustrating the fabrication process of the interposer structure 100 having the first object according to an embodiment of the present disclosure.

Referring to FIGS. 10 and 11 , in step S11 , an interposer 101 may be provided, and a plurality of through-board through-holes 103 may be formed along the interposer 101 .

Referring to FIG. 11 , the interposer 101 may be a laminate including an epoxy-based material or BT resin. In some embodiments, the through-board via 103 may be formed by drilling the interposer 101 to form a hole and then electroplating the hole. In some embodiments, the through-board holes 103 may be configured by vertically arranged micro-vias.

Referring to FIGS. 10 and 12 , in step S13 , a plurality of lower connectors 203 may be formed on the second surface 101SS of the interposer 101 , and a plurality of through-board openings BO may be formed along the interposer 101 .

Referring to FIG. 12, the plurality of lower connectors 203 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel or alloys thereof. In some embodiments, the plurality of lower connectors 203 may be solder balls. Solder balls can be preliminarily formed with a layer of tin by evaporation, electroplating, printing, solder transfer or ball placement, with a thickness of about 10 microns (μm) to 100 microns. Once the tin layer is formed on the second surface 101SS of the interposer 101, a reflow process may be performed to mold the tin layer into a desired shape and form solder balls. A plurality of through-board openings BO may be formed by drilling holes in the interposer 101 .

The interposer 101 , the plurality of through-board through holes 103 and the plurality of lower connectors 203 can be configured together to form the interposer structure 100 .

Referring to FIG. 10 and FIGS. 13 to 15, in step S15, the first semiconductor chip 311 may be fixed on the packaging substrate 401, a plurality of upper connectors 201 may be formed on the bottom surface of the packaging substrate 401, and the packaging substrate 401 may pass through multiple The upper connectors 201 are bonded to the first surface 101FS of the interposer 101, and the interposer 101 can be fixed to the test equipment by a plurality of fixing units 105 disposed along the plurality of through-board openings BO and extending to the chuck 501. on the chuck 501.

Referring to FIG. 13 , the first semiconductor chip 311 may be fixed on the packaging substrate 401 through the first adhesive layer 403 . Fixing the first semiconductor chip 311 on the packaging substrate 401 may include the following process: an adhesive material layer may be formed under the first semiconductor chip 311 . The layer of adhesive material may comprise a flowable material. The first semiconductor chip 311 having the adhesive material layer may be bonded on the packaging substrate 401 . Thereafter, a curing process may be performed subsequently, so that the adhesive material layer may be cross-linked and cured to form the first adhesion layer 403 .

The package substrate 401 can be used to carry the first semiconductor chip 311 . The packaging substrate 401 may be electrically coupled to the plurality of first bonding pads 313 of the first semiconductor chip 311 through a plurality of wires 411 . The fabrication technology of the plurality of wires 411 can be, for example, gold (Au). The plurality of wires 411 may be formed through a ball-wedge process or a wedge-wedge process by using ultrasonic bonding, thermoacoustic bonding, or thermocompression bonding. The first semiconductor chip 311 , the packaging substrate 401 , the first adhesion layer 403 and the plurality of wires 411 together constitute the first object.

Referring to FIG. 13 , a molding layer 315 may be formed on the package substrate 401 to cover the first semiconductor chip 311 and the plurality of wires 411 . The molding layer 315 can be formed of a molding compound, such as polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride. The molding layer 315 can be formed by compression molding, transfer molding, liquid encapsulation molding, and the like. For example, the molding compound can be dispensed in liquid form. Subsequently, a curing process is performed to cure the molding compound. The formation of the molding compound may overflow the first semiconductor chip 311 such that the molding compound covers the first semiconductor chip 311 . Planarization processes such as mechanical polishing, chemical mechanical polishing, or other etch-back techniques may be used to remove excess portions of the molding compound and provide a substantially flat surface.

Referring to FIG. 13, the plurality of upper connectors 201 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel or alloys thereof. In some embodiments, the plurality of upper connectors 201 may be solder balls. The solder balls can be initially formed with a layer of tin by evaporation, electroplating, printing, solder transfer or ball placement with a thickness of about 10 microns to about 100 microns. Once the tin layer is formed on the bottom surface of the package substrate 401, a reflow process can be performed to shape the tin layer into a desired shape and form solder balls.

In some embodiments, the plurality of upper connectors 201 may be formed on the first surface 101FS of the interposer 101 while the plurality of lower connectors 203 are formed. In some embodiments, interposer 100 may include a plurality of upper connectors 201 .

Referring to FIG. 14 , a package substrate 401 may be bonded on the first surface 101FS of the interposer 101 . A reflow process can be used.

Referring to FIG. 15 , a plurality of fixing units 105 may be vertically arranged into a plurality of through-board openings BO, respectively. A plurality of fixing units 105 may extend into the chuck 501 of the test device, so that the plurality of lower connectors 203 are in contact with the plurality of chuck connectors 503 of the test device.

The positions of the plurality of fixing units 105 may be adjusted to determine contact stress between the plurality of lower connectors 203 and the plurality of chuck connectors 503 . In the process of analyzing the first semiconductor chip 311, the molding layer 315 may be removed. Probes of the probe card may directly contact the top surface of the first semiconductor chip 311 to detect internal signals of the first semiconductor chip 311 .

An embodiment of the present disclosure provides an interposer structure, including an interposer configured to be fixed on and electrically coupled to a chuck of a test device, and a first object disposed on a chuck of the interposer. The first surface is electrically coupled with the interposer. The first object is configured to be analyzed by the testing device.

Another embodiment of the present disclosure provides an interposer comprising an interposer configured to be secured to and electrically coupled to a chuck of a test device, an upper connector disposed on a first surface and electrically coupled with the interposer, a lower connector disposed on a second surface and electrically coupled with the interposer, and a through-board via disposed in the interposer and configured to communicate with the upper connector and the lower The connectors are electrically coupled. The first surface of the interposer is opposite to the second surface of the interposer.

Another embodiment of the present disclosure provides a method for manufacturing an interposer structure, including providing an interposer, forming a through-plate through hole along the interposer, forming a through-plate opening along the interposer, and forming a through-plate opening on a first surface of the interposer. An upper connector is formed on the top, and a lower connector is formed on a second surface of the interposer. Due to the design of the interposer 100 of the present disclosure, internal signals of the first semiconductor chip 311 can be detected, and high-frequency failure mode and effect analysis can be performed.

Due to the design of the interposer structure 100 of the present disclosure, internal signals of the first semiconductor chip 311 can be detected, and high-frequency failure mode and effect analysis can be performed.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and alterations can be made without departing from the spirit and scope of the disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure to use existing or future developed processes, machines, manufactures, materials according to the present disclosure, which have the same function or achieve substantially the same results as the corresponding embodiments described herein. composition, means, method, or steps. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the patent scope of the present disclosure.

Claims (20)

1. A semiconductor device comprising: an interposer configured to be secured to and electrically coupled to a chuck of a test apparatus; and a first object disposed on a first surface of the interposer and electrically coupled with the interposer; Wherein the first object is configured to be analyzed by the testing device. 2. The semiconductor device as claimed in claim 1, further comprising a fixing unit disposed along the interposer and extending to the chuck to fix the interposer on the chuck. 3. The semiconductor device as claimed in claim 2, wherein the fixing unit is a screw. 4. The semiconductor device according to claim 2, further comprising a lower connector disposed on a second surface of the interposer; Wherein the second surface is opposite to the first surface and faces the chuck. 5. The semiconductor device as claimed in claim 4, wherein the lower connector and the chuck are electrically coupled through a chuck connector. 6. The semiconductor device as claimed in claim 5, wherein the chuck connector is a pogo pin. 7. The semiconductor device of claim 5, wherein the chuck connector is a conductive polymer. 8. The semiconductor device of claim 5, wherein the interposer comprises a test pattern configured to electrically couple the first object and the lower connector. 9. The semiconductor device of claim 8, wherein the test pattern comprises at least one through-board hole disposed along the interposer and contacting the lower connector. 10. The semiconductor device according to claim 9, wherein the first object comprises: a packaging substrate disposed on the first surface of the interposer and electrically coupled with the interposer; a first semiconductor chip disposed on the packaging substrate; and A wire configured to electrically couple the first semiconductor chip and the packaging substrate. 11. The semiconductor device of claim 10, wherein the package substrate and the interposer are electrically coupled through an upper connector. 12. The semiconductor device as claimed in claim 11, wherein the upper connector is a solder ball. 13. The semiconductor device according to claim 12, further comprising a second semiconductor chip disposed on the packaging substrate, the second semiconductor chip is adjacent to the first semiconductor chip and electrically coupled to the packaging substrate. 14. The semiconductor device according to claim 13, wherein the first semiconductor chip and the second semiconductor chip have the same layout. 15. The semiconductor device according to claim 14, wherein a thickness of the interposer is greater than a thickness of the packaging substrate. 16. A semiconductor device comprising an interposer configured to be secured to and electrically coupled to a chuck of a test apparatus; an upper connector disposed on a first surface and electrically coupled with the interposer; a lower connector disposed on a second surface and electrically coupled to the interposer; and a through-board through-hole disposed in the interposer and configured to be electrically coupled with the upper connector and the lower connector; Wherein the first surface of the interposer is opposite to the second surface of the interposer. 17. The semiconductor device according to claim 16, further comprising a first object disposed on the upper connector and electrically coupled with the upper connector; Wherein the first object includes a first semiconductor chip. 18. A method for preparing a mesostructure, comprising; providing an interposer; forming a plate through hole along the intermediate plate; forming a through-plate opening along the intermediate plate; forming an upper connector on a first surface of the interposer; and A connector is formed on a second surface of the interposer. 19. The fabrication method of the interposer as claimed in claim 18, wherein the upper connector is a solder ball. 20. The method of fabricating an interposer as claimed in claim 18, wherein the interposer comprises an epoxy-based material, or imine-triazine resin.

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