CN116013854B

CN116013854B - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN116013854B
Application number: CN202310313697.7A
Authority: CN
Inventors: 李双
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-06-30
Anticipated expiration: 2043-03-28
Also published as: CN116013854A

Abstract

Disclosed are a semiconductor structure and a method of manufacturing the same, the method comprising: providing an initial structure comprising a substrate, a plurality of bit line structures of an active region and a plurality of isolation barriers, wherein the bit line structures and the isolation barriers are mutually intersected to define a plurality of openings exposing the active region, and the bit line structures comprise bit line layers, sacrificial layers covering the side walls of the bit line layers and first dielectric layers at least covering the sacrificial layers; forming a storage node contact plug in the opening; removing the sacrificial layer to form a gap; forming a second dielectric layer which at least covers the inner wall of the gap and closes the top opening of the gap by adopting a selective rapid plasma nitrogen treatment process, wherein the area of the gap which is not filled by the second dielectric layer is defined as an air gap; and forming a contact pad covering part of the second dielectric layer on the storage node contact plug.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method of manufacturing the same.

Background

Semiconductor structures, such as Dynamic Random Access Memories (DRAMs), typically include multiple bit line layers for transmitting signals. With the increase in integration and decrease in size of semiconductor structures, air gap structures are typically formed on the sidewalls of the bit line layers in order to reduce parasitic capacitance between adjacent bit line layers and between the bit line layers and other structures.

However, the existing air gap structure has complex manufacturing process, is easy to generate process defects, and is difficult to effectively reduce parasitic capacitance.

Disclosure of Invention

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps:

providing an initial structure, wherein the initial structure comprises a substrate and an active region positioned in the substrate; a plurality of bit line structures and a plurality of isolation barriers are formed on the substrate, and the bit line structures and the isolation barriers are intersected with each other to define a plurality of openings exposing the active area; the bit line structure comprises a bit line layer, a sacrificial layer and a first dielectric layer, wherein the sacrificial layer covers the side wall of the bit line layer;

forming a storage node contact plug filling a lower portion of the opening and covering a portion of a sidewall of the first dielectric layer and the active region exposed by the opening;

opening the top of the first dielectric layer and removing the sacrificial layer, and forming a gap between the first dielectric layer and the side wall of the bit line layer;

forming a second dielectric layer on the substrate by adopting a selective rapid plasma nitrogen treatment process, wherein the second dielectric layer at least covers the inner wall of the gap and closes the top opening of the gap, and the area of the gap which is not filled by the second dielectric layer is defined as an air gap;

And forming a contact pad on the storage node contact plug, wherein the contact pad covers part of the second dielectric layer.

In some embodiments, providing an initial structure includes:

providing a substrate;

forming an isolation structure within the substrate, the isolation structure defining a plurality of active regions within the substrate;

forming a plurality of bit line layers extending in a first direction on the substrate;

forming a sacrificial layer and a first dielectric layer on the substrate in sequence, wherein the sacrificial layer covers the side wall of the bit line layer, and the first dielectric layer covers the bit line layer, the sacrificial layer and the substrate;

forming a filling layer, wherein the filling layer covers the first dielectric layer and fills gaps between adjacent bit line structures;

etching the filling layer to form a plurality of grooves extending along a second direction in the filling layer;

filling insulating material in the grooves to form a plurality of isolation barriers;

removing the filling layer, wherein the isolation fence and the bit line structure mutually intersect to define a plurality of initial openings;

and etching the bottom of the initial opening to expose the active region, thereby forming the opening.

In some embodiments, opening the top of the first dielectric layer and removing the sacrificial layer includes:

Removing the first dielectric layer and the top of the sacrificial layer to expose the top and part of the side wall of the bit line layer, and simultaneously exposing the sacrificial layer;

and removing the remaining sacrificial layer.

In some embodiments, an etching process is performed on the remaining sacrificial layer using an etching gas including gaseous hydrogen fluoride to remove the remaining sacrificial layer.

In some embodiments, forming the second dielectric layer using a selective rapid plasma nitrogen treatment process includes:

placing the substrate in a first reaction cavity, wherein at least one pair of alternating electromagnetic polar plates and at least one pair of alternating electrode plates are arranged in the first reaction cavity;

introducing a first nitrogen source gas into the first reaction cavity;

and applying radio frequency signals to the alternating electromagnetic polar plate and the alternating electrode plate to form an alternating magnetic field and an alternating electric field in the first reaction cavity, wherein the first nitrogen source gas is dissociated into plasma, the plasma is guided to the surfaces of the bit line layer and the first medium layer, the top of the storage node contact plug and the inner wall of the gap under the action of the alternating magnetic field and the alternating electric field, and the density of the plasma positioned at the upper part of the inner wall of the gap is higher than that of the plasma positioned at the lower part of the inner wall of the gap.

In some embodiments, the second dielectric layer is formed using a selective rapid plasma nitrogen treatment process, further comprising:

placing the substrate in a second reaction chamber;

introducing a first silicon source gas into the second reaction cavity, wherein the first silicon source gas is adsorbed on the plasma;

introducing a second nitrogen source gas into the second reaction cavity to deposit a second dielectric layer on the substrate, wherein the second dielectric layer covers the surfaces of the bit line layer and the first dielectric layer, the top of the storage node contact plug and the inner wall of the gap; the thickness of the second dielectric layer covering the upper part of the inner wall of the gap is larger than that of the second dielectric layer covering the lower part of the inner wall of the gap;

and the step of introducing a first silicon source gas and a second nitrogen source gas into the second reaction cavity to form the second dielectric layer is executed again until the second dielectric layer seals the top opening of the gap, so that the air gap is formed.

In some embodiments, any pair of alternating electromagnetic plates are respectively arranged on two opposite sides of the substrate, and any pair of alternating electrode plates are respectively arranged above and below the substrate.

In some embodiments, the number of alternating electromagnetic plates is 2 pairs, 3 pairs, or 4 pairs.

In some embodiments, the frequency of the alternating magnetic field is greater than 0 and less than or equal to 2000MHz, and the frequency of the alternating electric field is greater than 0 and less than or equal to 2000MHz.

In some embodiments, before forming the contact pad on the storage node contact plug, further comprising: removing the second dielectric layer covering the top of the storage node contact plug;

forming a contact pad on the storage node contact plug, comprising:

forming a conductive material layer, wherein the conductive material layer fills the opening and covers the second dielectric layer;

and etching the conductive material layer to form a plurality of discrete contact pads, wherein the contact pads cover the storage node contact plugs and part of the second dielectric layer.

In some embodiments, the substrate includes an array region and a peripheral region, the isolation barrier and the bit line structure being formed in the array region; the initial structure further comprises a device structure positioned in the peripheral region and an insulating layer covering the device structure and the substrate of the peripheral region;

the method further comprises the steps of: forming at least one peripheral contact hole in the peripheral region, wherein the peripheral contact hole penetrates through the insulating layer and exposes the device structure;

Forming a conductive material layer, further comprising: forming the conductive material layer in the peripheral region, wherein the conductive material layer fills the peripheral contact hole and covers the insulating layer; wherein the conductive material layer filling the peripheral contact hole forms a peripheral contact plug;

while etching the conductive material layer to form a plurality of discrete contact pads, the method further comprises: and etching the conductive material layer covering the insulating layer to form at least one metal layer, wherein the metal layer is electrically connected with the peripheral contact plug.

The disclosed embodiments also provide a semiconductor structure, comprising:

a substrate and an active region within the substrate;

a plurality of bit line layers and a plurality of isolation barriers on the substrate, the bit line layers and the isolation barriers intersecting one another to define a plurality of openings exposing the active region;

the first dielectric layer covers the side wall of the bit line layer, and a gap is formed between the first dielectric layer and the side wall of the bit line layer;

a storage node contact plug filling a lower portion of the opening and covering a portion of a sidewall of the first dielectric layer and the active region exposed by the opening;

a second dielectric layer formed by a selective rapid plasma nitrogen treatment process and covering at least the inner wall of the gap and closing the top opening of the gap, wherein the region of the gap not filled by the second dielectric layer is defined as an air gap;

And the contact pad is positioned on the storage node contact plug and covers part of the second dielectric layer.

In some embodiments, the thickness of the second dielectric layer covering the upper portion of the inner wall of the gap formed by the selective rapid plasma nitrogen treatment process is greater than the thickness of the second dielectric layer covering the lower portion of the inner wall of the gap, such that the second dielectric layer closes the top opening of the gap.

In some embodiments, the substrate includes an array region and a peripheral region, the isolation barrier and the bit line layer being formed in the array region; the semiconductor structure further includes: a device structure located in the peripheral region and an insulating layer covering the device structure and the substrate of the peripheral region; at least one peripheral contact hole located in the peripheral region, penetrating the insulating layer and exposing the device structure; a peripheral contact plug filling the peripheral contact hole; and at least one metal layer positioned on the insulating layer and electrically connected with the peripheral contact plug.

The embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing an initial structure, wherein the initial structure comprises a substrate and an active region positioned in the substrate; a plurality of bit line structures and a plurality of isolation barriers are formed on the substrate, and the bit line structures and the isolation barriers are intersected with each other to define a plurality of openings exposing the active area; the bit line structure comprises a bit line layer, a sacrificial layer and a first dielectric layer, wherein the sacrificial layer covers the side wall of the bit line layer; forming a storage node contact plug filling a lower portion of the opening and covering a portion of a sidewall of the first dielectric layer and the active region exposed by the opening; opening the top of the first dielectric layer and removing the sacrificial layer, and forming a gap between the first dielectric layer and the side wall of the bit line layer; forming a second dielectric layer on the substrate by adopting a selective rapid plasma nitrogen treatment process, wherein the second dielectric layer at least covers the inner wall of the gap and closes the top opening of the gap, and the area of the gap which is not filled by the second dielectric layer is defined as an air gap; and forming a contact pad on the storage node contact plug, wherein the contact pad covers part of the second dielectric layer. In the embodiment of the disclosure, the gap is formed before the contact pad is formed, and the second dielectric layer is formed to close the top opening of the gap so as to form the air gap, so that compared with the formation of the air gap after the contact pad is formed, the manufacturing process of the semiconductor structure is simplified, the process cost is reduced, and on the other hand, the semiconductor structure is relatively simple, the process difficulty of removing the sacrificial layer and closing the top opening of the gap is reduced, the formation of the air gap with a larger volume is facilitated, the parasitic capacitance between adjacent bit line layers and between the bit line layer and the storage node contact plug is effectively reduced, and the performance of the semiconductor structure is improved; meanwhile, the embodiment of the disclosure forms the second dielectric layer by adopting a selective rapid plasma nitrogen treatment process, which comprises the step of performing selective plasma nitridation treatment on the semiconductor structure, so that nitrogen-containing plasma is more easily adsorbed on the upper part of the semiconductor structure, and the second dielectric layer is more easily deposited at the top opening of the gap when the second dielectric layer is deposited, so that the second dielectric layer can more rapidly close the top opening of the gap, and the volume of the air gap is further improved.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will be apparent from the accompanying drawings of the specification.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 2 is a process flow diagram of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 3 is a second process flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 4 is a process flow diagram three of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 5 is a process flow diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 6 is a process flow diagram fifth of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

Fig. 7 is a process flow diagram sixth of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 8 is a process flow diagram seventh of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 9 is a process flow diagram eight of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 10 is a process flow diagram nine of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 11 is a process flow diagram ten of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 12 is a process flow diagram eleven of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 13 is a process flow diagram twelve of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 14 is a process flow chart thirteenth of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 15 is a process flow chart fourteen of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 16 is a process flow diagram fifteen of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 17 is a process flow diagram sixteen of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

fig. 18 is a process flow chart seventeen of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

However, the existing air gap structure has complex manufacturing process, is easy to generate process defects, and is difficult to effectively reduce parasitic capacitance. Specifically, in the related art, an air gap is generally formed on the sidewall of the bit line layer by: firstly, forming a sacrificial layer on the side wall of a bit line layer and a dielectric layer covering the sacrificial layer; forming storage node contact plugs between adjacent bit line layers, and forming contact pads on the storage node contact plugs, wherein the contact pads cover the sacrificial layer and the dielectric layer; the contact pads are then etched to form recesses exposing the sacrificial layer, and the sacrificial layer is removed through the recesses to form air gaps. However, the semiconductor structure after the contact pad is formed is complicated, it is difficult to form a recess exposing the sacrificial layer by an etching process, and the sacrificial layer is difficult to be completely removed, so that parasitic capacitance cannot be effectively reduced.

Based on this, the following technical solutions of the embodiments of the present disclosure are provided:

the embodiment of the disclosure provides a method for manufacturing a semiconductor structure, and particularly please refer to fig. 1. As shown, the method includes the steps of:

step S101, providing an initial structure, wherein the initial structure comprises a substrate and an active area positioned in the substrate; a plurality of bit line structures and a plurality of isolation barriers formed on the substrate, the bit line structures and the isolation barriers intersecting one another to define a plurality of openings exposing the active region; the bit line structure comprises a bit line layer, a sacrificial layer and a first dielectric layer, wherein the sacrificial layer covers the side wall of the bit line layer;

step S102, forming a storage node contact plug, wherein the storage node contact plug fills the lower part of the opening and covers part of the side wall of the first dielectric layer and the active area exposed by the opening;

step S103, opening the top of the first dielectric layer and removing the sacrificial layer, and forming a gap between the first dielectric layer and the side wall of the bit line layer;

step S104, forming a second dielectric layer on the substrate by adopting a selective rapid plasma nitrogen treatment process, wherein the second dielectric layer at least covers the inner wall of the gap and closes the top opening of the gap, and the area of the gap not filled by the second dielectric layer is defined as an air gap;

Step S105, forming a contact pad on the storage node contact plug, wherein the contact pad covers a part of the second dielectric layer.

The manufacturing method provided by the embodiment of the disclosure can be used for manufacturing Dynamic Random Access Memories (DRAMs). But is not limited thereto, the fabrication method may also be used to fabricate any semiconductor structure.

The following detailed description of specific embodiments of the present disclosure refers to the accompanying drawings. In describing embodiments of the present disclosure in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the disclosure.

Fig. 2 to 18 are process flow diagrams of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure, wherein fig. 2 and 5 are schematic top views, fig. 3 and 6 are schematic cross-sectional structures taken along a line AA' of fig. 2 and 5, fig. 11 is a schematic structural view of a first chamber, fig. 12 is a schematic top view of fig. 11, and fig. 13, 14 and 15 are schematic partial views of the semiconductor structure. The method of manufacturing the semiconductor device according to the embodiments of the present disclosure will be described in further detail below with reference to fig. 2 to 18.

First, step S101 is performed, as shown in fig. 2 to 6, an initial structure 20 is provided, the initial structure 20 including a substrate 10 and an active region 12 located within the substrate 10; a plurality of bit line structures BL and a plurality of barrier ribs 32 are formed on the substrate 10, the bit line structures BL and the barrier ribs 32 intersecting each other to define a plurality of openings S2 exposing the active regions 12; the bit line structure BL includes a bit line layer 13, a sacrificial layer 15 covering a sidewall of the bit line layer 13, and a first dielectric layer 16 covering at least the sacrificial layer 15.

Specifically, an initial structure 20 is provided, comprising:

providing a substrate 10; forming an isolation structure 11 within the substrate 10, the isolation structure 11 defining a plurality of active regions 12 within the substrate 10; forming a plurality of bit line layers 13 extending in a first direction on a substrate 10; a sacrificial layer 15 and a first dielectric layer 16 are sequentially formed on the substrate 10, the sacrificial layer 15 covers the side wall of the bit line layer 13, and the first dielectric layer 16 covers the bit line layer 13, the sacrificial layer 15 and the substrate 10; forming a filling layer 17, wherein the filling layer 17 covers the first dielectric layer 16 and fills gaps between adjacent bit line structures BL; etching the filling layer 17 to form a plurality of trenches T extending in the second direction within the filling layer 17; filling the trench T with an insulating material to form a plurality of barrier ribs 32;

the fill layer 17 is removed and the isolation barrier 32 and bit line structure BL are interdigitated to define a plurality of initial openings

；

Etching the initial opening

To expose the active region 12, forming an opening S2.

Here, the substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a particular embodiment, the substrate 10 is a silicon substrate, which may be doped or undoped. In some embodiments, active region 12 is the same material as substrate 10.

As shown in fig. 3, in an embodiment, the substrate 10 further includes an interlayer dielectric layer L on a surface, and the interlayer dielectric layer L is used to electrically isolate the bit line layer 13 from the substrate 10.

In one embodiment, the bit line layer 13 includes a bit line conductive layer 132 and a bit line cap layer 133 covering the bit line conductive layer 132, wherein the bit line conductive layer 132 may have a multi-layered structure. The material of the bit line conductive layer 132 includes polysilicon, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. In one embodiment, the bit line conductive layer 132 includes a polysilicon layer, a tungsten layer overlying the polysilicon layer, and a titanium nitride layer between the polysilicon layer and the tungsten layer. The material of bit line cap layer 133 includes, but is not limited to, silicon nitride.

In one embodiment, the substrate 10 has a bit line contact hole S1 exposing the active region 12 formed therein, and the bit line layer 13 further includes a bit line contact plug 131 located in the bit line contact hole S1 and covering a portion of the active region 12, the bit line contact plug 131 being located under the bit line conductive layer 132, and the bit line layer 13 being electrically connected to the active region 12 through the bit line contact plug 131. The material of the bit line contact plug 131 includes, but is not limited to, polysilicon.

In one embodiment, the bit line layer 13 further includes a protection layer 134, where the protection layer 134 at least covers the bit line contact plug 131, the bit line conductive layer 132, and the sidewall of the bit line cap layer 133, so as to protect the bit line layer 13 from being damaged or contaminated in subsequent process steps. In some embodiments, the protection layer 134 also covers the sidewalls and bottom surface of the bit line contact hole S1, and the sacrificial layer 15 covers the sidewalls of the protection layer 134 and fills the remaining space of the bit line contact hole S1.

The material of the protective layer 134 and the material of the first dielectric layer 16 include, but are not limited to, nitrides, such as silicon nitride; the material of the sacrificial layer 15 includes, but is not limited to, an oxide, such as silicon oxide.

In one embodiment, as shown in fig. 3, the plurality of bit line layers 13 extend in a first direction and are arranged in a second direction, and the plurality of isolation barriers 32 extend in the second direction and are arranged in the first direction within the filling layer 17. The first direction and the second direction may be disposed perpendicular to each other. But is not limited thereto, the first direction and the second direction may also be diagonal. The material of the filler layer 17 includes, but is not limited to, silicon oxide; the material of the barrier fence 32 includes, but is not limited to, silicon nitride.

Referring again to fig. 4, after removal of the fill layer 17, it is located in the initial opening

The underlying active region 12 is surrounded by the opening located initially +.>

The bottom first dielectric layer 16 and the interlayer dielectric layer L are covered, so that, as shown in fig. 6, after removing the filling layer 17, the opening +.>

The bottom part of the first dielectric layer 16, part of the interlayer dielectric layer L, part of the active region 12 and part of the isolation structure 11 form an opening S2 exposing the active region 12.

In one embodiment, the substrate 10 includes an array region 101 and a peripheral region 102, isolation structures 11 and active regions 12 are formed in both the array region 101 and the peripheral region 102, and isolation barrier 32 and bit line structures BL are formed in the array region 101. In some embodiments, device structure 18 and insulating layer 19 covering device structure 18 and substrate 10 at peripheral region 102 are formed on peripheral region 102.

In one embodiment, device structure 18 includes a transistor formed on active region 12, the transistor including a gate conductive layer 181, a gate cap layer 182 overlying gate conductive layer 181, a gate sidewall layer 183 overlying sidewalls of gate conductive layer 181 and sidewalls and an upper surface of gate cap layer 182, and a source (not identified) and a drain (not identified) located on opposite sides of gate conductive layer 181 and formed within active region 12. The gate conductive layer 181 may have a multi-layered structure. In some embodiments, gate conductive layer 181 and gate cap layer 182 are formed in the same step as bit line conductive layer 132 and bit line cap layer 133.

The insulating layer 19 may also have a multi-layered structure, and the multi-layered structure may be formed through different process steps. In a specific embodiment, the insulating layer 19 includes a first insulating layer 191 and a second insulating layer 192 covering the first insulating layer 191, the material of the first insulating layer 191 includes, but is not limited to, an oxide, and the material of the second insulating layer 192 includes, but is not limited to, a nitride.

Next, step S102 is performed, as shown in fig. 7, a storage node contact plug 21 is formed, and the storage node contact plug 21 fills the lower portion of the opening S2 and covers a portion of the sidewall of the first dielectric layer 16 and the active region 12 exposed by the opening S2.

The storage node contact plugs 21 may be formed using a Chemical Vapor Deposition (CVD), a Plasma Enhanced Chemical Vapor Deposition (PECVD), an Atomic Layer Deposition (ALD), or the like. The material of the storage node contact plug 21 includes, but is not limited to, polysilicon, which may be doped or undoped.

Next, step S103 is performed, as shown in fig. 8 to 9, to open the top of the first dielectric layer 16 and remove the sacrificial layer 15, forming a gap 14 between the first dielectric layer 16 and the sidewall of the bit line layer 13.

Specifically, opening the top of the first dielectric layer 16 and removing the sacrificial layer 15 includes:

Removing the top of the first dielectric layer 16 and the sacrificial layer 15 to expose the top and part of the sidewalls of the bit line layer 13 while exposing the sacrificial layer 15;

the remaining sacrificial layer 15 is removed.

In one embodiment, a gap 14 is formed on both sidewalls of the bit line layer 13, the gap 14 being sandwiched between the protective layer 134 and the first dielectric layer 16.

In one embodiment, an etching process is performed on the remaining sacrificial layer 15 using an etching gas including gaseous hydrogen fluoride to remove the remaining sacrificial layer 15. The gaseous hydrogen fluoride has better diffusion performance, is favorable for fully removing the sacrificial layer 15, so that a gap 14 with larger volume is obtained, an air gap 22 (see fig. 10) with larger volume is obtained, and the effect of reducing parasitic capacitance between the bit line layers 13 and the storage node contact plugs 21 is improved. In some embodiments, the concentration of hydrogen fluoride in the gaseous hydrogen fluoride is greater than 0 and equal to or less than 100%, e.g., 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%.

As shown in fig. 8, in an embodiment, the upper surface of the remaining first dielectric layer 16 is higher than the upper surface of the storage node contact plug 21. In some embodiments, the upper surface of the remaining first dielectric layer 16 is also higher than the upper surface of the bit line conductive layer 132 in the bit line layer 13. In this way, the upper surface of the finally formed air gap 22 (see fig. 10) can be ensured to be higher than the upper surface of the bit line conductive layer 132, thereby improving the effect of reducing parasitic capacitance.

In the embodiment of the present disclosure, the sacrificial layer 15 also fills part of the bit line contact hole S1, so that a gap 14 can be formed between the sidewall of the bit line contact plug 131 and the substrate 10, thereby forming an air gap 22 (see fig. 10) between the sidewall of the bit line contact plug 131 and the substrate 10 in a subsequent process, reducing parasitic capacitance between the bit line contact plug 131 and the storage node contact plug 21.

Next, step S104 is performed, as shown in fig. 10, to form a second dielectric layer 23 on the substrate 10 by using a selective plasma nitrogen treatment process, where the second dielectric layer 23 covers at least the inner wall of the gap 14 and closes the top opening of the gap 14, and the area of the gap 14 not filled with the second dielectric layer 23 is defined as an air gap 22.

Specifically, first, as shown in fig. 11 to 13, a selective plasma nitrogen treatment process is used to form the second dielectric layer 23, including:

placing the substrate 10 in a first reaction chamber 24, wherein at least one pair of alternating electromagnetic plates 25 and at least one pair of alternating electrode plates 26 are arranged in the first reaction chamber 24;

introducing a first nitrogen source gas into the first reaction chamber 24;

a radio frequency signal is applied to the alternating electromagnetic plate 25 and the alternating electrode plate 26 to form an alternating magnetic field 27 and an alternating electric field 28 in the first reaction chamber 24, the first nitrogen source gas is dissociated into plasma 29, the plasma 29 is guided to the surfaces of the bit line layer 13 and the first dielectric layer 16, the top of the storage node contact plug 21 and the inner wall of the gap 14 under the action of the alternating magnetic field 27 and the alternating electric field 28, and the density of the plasma 29 located at the upper part of the inner wall of the gap 14 is greater than the density of the plasma 29 located at the lower part of the inner wall of the gap 14.

In one embodiment, the first nitrogen source gas includes, but is not limited to, nitrogen (N) ₂ ) Nitrogen oxide (N) ₂ O), ammonia (NH) ₃ ) One or a combination of these, e.g. ammonia (NH) ₃ ) The plasma 29 is a nitrogen-containing plasma.

In one embodiment, any pair of alternating electromagnetic plates 25 are disposed on opposite sides of the substrate 10. The number of alternating electromagnetic plates 25 shown in fig. 12 is 2 pairs, with 2 pairs of alternating electromagnetic plates 25 disposed around the substrate 10. But is not limited thereto, the number of alternating electromagnetic plates 25 may also be 3 pairs, 4 pairs or more. In some embodiments, any pair of alternating electrode plates 26 are disposed above and below the substrate 10, respectively. Fig. 11 shows the number of alternating electrode plates 26 as 1 pair, but is not limited thereto, and the number of alternating electrode plates 26 may be more, for example, 2 pairs, 3 pairs, or 4 pairs.

In the embodiment of the disclosure, the alternating electromagnetic plate 25 and the alternating electrode plate 26 are arranged in the first reaction cavity 24 to form the alternating magnetic field 27 and the alternating electric field 28, so that the selective plasma nitridation treatment is carried out on the semiconductor structure, and the plasma 29 is more easily adsorbed at the top opening of the gap 14. Specifically, the alternating electromagnetic polar plate 25 is arranged on the side surface of the substrate 10 to form an alternating magnetic field 27 in the horizontal direction, and the plasma 29 moves horizontally under the action of the alternating magnetic field 27, so that the plasma 29 is more easily adsorbed on the bit line layer 13, the first dielectric layer 16 and the side wall of the gap 14; meanwhile, alternating electrode plates 26 are respectively disposed above and below the substrate 10 to form alternating electric fields 28 in a vertical direction, and plasma 29 is moved upward or downward by changing a bias voltage of the alternating electric fields 28, so that a sinking speed of the plasma 29 is adjusted, so that the plasma 29 is more easily adsorbed to upper portions of the bit line layer 13, the first dielectric layer 16, and sidewalls of the gap 14 while sinking, and only a small amount of the plasma 29 reaches a lower portion of the gap 14, so that a density of the plasma 29 located at an upper portion of an inner wall of the gap 14 is greater than a density of the plasma 29 located at a lower portion of the inner wall of the gap 14.

In one embodiment, the frequency of the alternating magnetic field 27 is greater than 0 and less than or equal to 2000MHz, such as 1MHz, 250MHz, 500MHz, 750MHz, 1000MHz, 1250MHz, 1500MHz, 1750MHz, 2000MHz; the frequency of the alternating electric field 28 is greater than 0 and less than or equal to 2000MHz, such as 1MHz, 250MHz, 500MHz, 750MHz, 1000MHz, 1250MHz, 1500MHz, 1750MHz, 2000MHz. In some embodiments, the frequency of alternating magnetic field 27 and the frequency of alternating electric field 28 are maintained consistent when performing nitrogen treatment on the semiconductor structure, so that plasma 29 is directed faster and more precisely at the top opening of gap 14, improving the effectiveness of the nitrogen treatment.

Next, the second dielectric layer 23 may be continuously deposited through a Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), etc., such as an Atomic Layer Deposition (ALD) process. In one embodiment, as shown in fig. 14 to 15, the second dielectric layer 23 is formed by using a selective plasma nitrogen treatment process, and further includes:

placing the substrate 10 in a second reaction chamber; introducing a first silicon source gas into the second reaction chamber, wherein the first silicon source gas is adsorbed on the plasma 29; introducing a second nitrogen source gas into the second reaction cavity to deposit a second dielectric layer 23 on the substrate 10, wherein the second dielectric layer 23 covers the surfaces of the bit line layer 13 and the first dielectric layer 16, the top of the storage node contact plug 21 and the inner wall of the gap 14; wherein, the thickness of the second dielectric layer 23 covering the upper part of the inner wall of the gap 14 is larger than the thickness of the second dielectric layer 23 covering the lower part of the inner wall of the gap 14;

The step of introducing the first silicon source gas and the second nitrogen source gas into the second reaction chamber to form the second dielectric layer 23 is performed again until the second dielectric layer 23 closes the top opening of the gap 14, thereby forming the air gap 22.

In practice, after the step of introducing the first silicon source gas into the second reaction chamber, which is adsorbed on the plasma 29, and the step of introducing the second nitrogen source gas into the second reaction chamber to deposit the second dielectric layer 23 on the substrate 10 are performed, a purge gas is introduced into the second reaction chamber to exhaust the excessive first silicon source gas, second nitrogen source gas, or reaction by-products. The purge gas may be an inert gas such as nitrogen or argon.

Here, the second reaction chamber may be the same reaction chamber as the first reaction chamber, and thus, process stability may be increased and process costs may be reduced. But is not limited thereto, the second reaction chamber and the first reaction chamber may be different.

In one embodiment, the second nitrogen source gas includes, but is not limited to, nitrogen (N) ₂ ) Nitrogen oxide (N) ₂ O), ammonia (NH) ₃ ) The second nitrogen source gas and the first nitrogen source gas may be the same or different. In one embodiment, the second nitrogen source gas and the first nitrogen source gas are both ammonia (NH) ₃ ). The first silicon source gas includes silane or a silane-derived material. Here, the silane includes SiH ₄ 、Si ₂ H ₆ Or Si (or) _n H _2n+2 (n is greater than 2), the silane-derived material comprises chlorosilane or iodosilane.

In one embodiment, the second dielectric layer 23 may be generated by subjecting the first silicon source gas and the second nitrogen source gas to a thermal decomposition reaction. However, the method is not limited thereto, and after the second nitrogen source gas is introduced into the second reaction chamber, a radio frequency electric field may be applied to the second nitrogen source gas to form active radicals, and the active radicals react with the first silicon source gas to form the second dielectric layer 23. The material of the second dielectric layer 23 comprises silicon nitride.

When the second dielectric layer 23 is formed, the plasma 29 is first formed in the first reaction chamber 24, and the plasma 29 is selectively adsorbed on the surface of the semiconductor structure, so that the thickness of the finally formed second dielectric layer 23 covering the upper portion of the inner wall of the gap 14 is greater than that of the second dielectric layer 23 covering the lower portion of the inner wall of the gap 14, so that the second dielectric layer 23 closes the opening of the gap 14 faster, and the gap 14 is closed while ensuring that the air gap 22 has a sufficient volume, thereby improving the effect of reducing parasitic capacitance.

In one embodiment, due to the difference in material properties, the density of the plasma 29 guided to the top of the storage node contact plug 21 is small, and thus the thickness of the second dielectric layer 23 is formed to be thin, which is convenient for subsequent removal.

In one embodiment, second dielectric layer 23 also covers the top of insulating layer 19 at peripheral region 102 and the top and portions of the sidewalls of barrier ribs 32 at array region 101.

Next, step S105 is performed, as shown in fig. 17 to 18, to form a contact pad LP on the storage node contact plug 21, the contact pad LP covering a part of the second dielectric layer 23.

As shown in fig. 16, in an embodiment, before forming the contact pad LP on the storage node contact plug 21, further includes: the second dielectric layer 23 covering the top of the storage node contact plug 21 is removed. In some embodiments, the second dielectric layer 23 covering the tops of the insulating layer 19, the bit line layer 13, and the barrier ribs 32 is removed at the same time as the second dielectric layer 23 covering the tops of the storage node contact plugs 21 is removed.

Referring again to fig. 17 to 18, forming the contact pad LP on the storage node contact plug 21 includes:

forming a conductive material layer 31, wherein the conductive material layer 31 fills the opening S2 and covers the second dielectric layer 23;

the conductive material layer 31 is etched to form a plurality of discrete contact pads LP that cover the storage node contact plugs 21 and portions of the second dielectric layer 23.

The layer of conductive material 31 may be deposited by one or more thin film deposition processes, such as Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof. Conductive material The material of layer 31 includes tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSi) _x 、CoSi _x 、NiSi _x 、AlSi _x Etc.), a metal alloy, or any combination thereof, e.g., tungsten.

Referring again to fig. 17, the method further comprises: forming at least one peripheral contact hole S3 in the peripheral region 102, the peripheral contact hole S3 penetrating the insulating layer 19 and exposing the device structure 18; forming the conductive material layer 31 further includes: forming a conductive material layer 31 in the peripheral region 102, the conductive material layer 31 filling the peripheral contact hole S3 and covering the insulating layer 19; the conductive material layer 31 filling the peripheral contact hole S3 forms a peripheral contact plug V, and the peripheral contact plug V is electrically connected to the device structure 18. In one embodiment, the peripheral contact plugs V are electrically connected to source electrodes (not shown) and drain electrodes (not shown) located on both sides of the gate conductive layer 181.

Referring again to fig. 18, while etching the conductive material layer 31 to form a plurality of discrete contact pads LP, further includes: the conductive material layer 31 covering the insulating layer 19 is etched to form at least one metal layer M electrically connected to the peripheral contact plugs V. The metal layer M located in the peripheral region 102 is formed in the same step as the contact pad LP located in the array region 101, simplifying the process.

It can be seen that, in the embodiment of the disclosure, before the contact pad LP is formed, the sacrificial layer 15 is removed to form the gap 14, and the second dielectric layer 23 is formed to close the top opening of the gap 14 to form the air gap 22, compared with the formation of the air gap after the contact pad is formed in the related art, on the one hand, the manufacturing process of the semiconductor structure is simplified, the process cost is reduced, on the other hand, the semiconductor structure is relatively simple, the etching capability of etching gas on the sacrificial layer 15 can be improved, the process difficulty of removing the sacrificial layer 15 and closing the gap 14 is reduced, the formation of the complete air gap 22 is facilitated, the parasitic capacitance between the adjacent bit line layers 13 and between the bit line layer 13 and the storage node contact plug 21 is effectively reduced, and the performance of the semiconductor structure is improved.

It should be noted that one skilled in the art could make possible variations between the above-described sequence of steps without departing from the scope of the present disclosure.

The embodiment of the disclosure further provides a semiconductor structure, as shown in fig. 18, including: a substrate 10 and an active region 12 within the substrate 10; a plurality of bit line layers 13 and a plurality of barrier ribs 32 (see fig. 5) on the substrate 10, the bit line layers 13 and the barrier ribs 32 intersecting each other to define a plurality of openings S2 exposing the active regions 12; a first dielectric layer 16 covering the sidewalls of the bit line layer 13, the first dielectric layer 16 and the sidewalls of the bit line layer 13 having a gap 14 therebetween; a storage node contact plug 21 filling a lower portion of the opening S2 and covering a portion of a sidewall of the first dielectric layer 16 and the active region 12 exposed by the opening S2; a second dielectric layer 23 formed by a selective rapid plasma nitrogen treatment process and covering at least the inner wall of the gap 14 and closing the top opening of the gap 14, the region of the gap 14 not filled by the second dielectric layer 23 being defined as an air gap 22; the contact pad LP is located on the storage node contact plug 21 and covers a portion of the second dielectric layer 23.

In an embodiment, the semiconductor structure further comprises an isolation structure 11 located within the substrate 10, the isolation structure 11 being for electrically isolating the plurality of active regions 12.

In one embodiment, the substrate 10 further includes an interlayer dielectric layer L on the surface of the substrate 10, where the interlayer dielectric layer L is used to electrically isolate the bit line layer 13 from the substrate 10.

In one embodiment, the substrate 10 has a bit line contact hole S1 exposing the active region 12 formed therein, the bit line layer 13 further includes a bit line contact plug 131 located in the bit line contact hole S1 and covering a portion of the active region 12, the bit line contact plug 131 is located under the bit line conductive layer 132, and the bit line layer 13 is electrically connected to the active region 12 through the bit line contact plug 131. The material of the bit line contact plug 131 includes, but is not limited to, polysilicon.

In one embodiment, the bit line layer 13 further includes a protection layer 134, where the protection layer 134 at least covers the bit line contact plug 131, the bit line conductive layer 132, and the sidewall of the bit line cap layer 133, so as to protect the bit line layer 13 from being damaged or contaminated during the actual manufacturing process. In some embodiments, the protection layer 134 also covers sidewalls and bottom surfaces of the bit line contact hole S1.

Referring to fig. 5, in an embodiment, the plurality of bit line layers 13 extend along a first direction and are arranged along a second direction, the plurality of isolation barriers 32 extend along the second direction and are arranged along the first direction, the storage node contact plugs 21 are located in openings S2 surrounded by adjacent bit line layers 13 and isolation barriers 32, and the storage node contact plugs 21 also cover a portion of the outer sidewalls of the first dielectric layer 16. The first direction and the second direction may be disposed perpendicular to each other. But is not limited thereto, the first direction and the second direction may also be diagonal.

The material of the protective layer 134 and the material of the first dielectric layer 16 include, but are not limited to, nitride. The material of the storage node contact plug 21 includes, but is not limited to, polysilicon, which may be doped or undoped.

In one embodiment, a gap 14 is formed on both sidewalls of the bit line layer 13, and the gap 14 is sandwiched between the first dielectric layer 16 and the protection layer 134. In some embodiments, the gap 14 further includes a region within the bit line contact hole S1 that is not filled with the protection layer 134 and the bit line contact plug 131.

In one embodiment, the upper surface of the first dielectric layer 16 is lower than the upper surface of the bit line layer 13 and higher than the upper surface of the storage node contact plug 21, and the second dielectric layer 23 covers the inner wall of the gap 14, the top of the first dielectric layer 16, the sidewall of the top of the bit line layer 13, and the sidewall of the top of the barrier rib 32.

The second dielectric layer 23 in the embodiment of the present disclosure is formed by a selective rapid plasma nitrogen treatment process, and the selective plasma nitridation treatment is performed on the semiconductor structure, so that the nitrogen-containing plasma is more easily absorbed on the upper portion of the semiconductor structure, and when the second dielectric layer 23 is deposited, the second dielectric layer 23 is more easily deposited at the top opening of the gap 14, that is, the thickness of the second dielectric layer 23 formed by the selective rapid plasma nitrogen treatment process and covering the upper portion of the inner wall of the gap 14 is greater than the thickness of the second dielectric layer 23 covering the lower portion of the inner wall of the gap 14, so that the opening of the gap 14 is sealed faster by the second dielectric layer 23, and thus, the gap 22 is ensured to have a sufficiently large volume while the gap 14 is sealed, and the effect of reducing parasitic capacitance is improved.

Specifically, referring to fig. 11 to 15, in actual operation, the second dielectric layer 23 is formed by a selective rapid plasma nitrogen treatment process, including: first, the substrate 10 is placed in the first reaction chamber 24, and at least one pair of alternating electromagnetic plates 25 and at least one pair of alternating electrode plates 26 are disposed in the first reaction chamber 24; then, introducing a first nitrogen source gas into the first reaction cavity 24, and applying radio frequency signals to the alternating electromagnetic polar plate 25 and the alternating electrode plate 26 to form an alternating magnetic field 27 and an alternating electric field 28 in the first reaction cavity 24, wherein the first nitrogen source gas is dissociated into plasmas 29, the plasmas 29 are guided to the surface of the semiconductor structure and the inner wall of the gap 14 under the action of the alternating magnetic field 27 and the alternating electric field 28, and the density of the plasmas 29 positioned at the upper part of the inner wall of the gap 14 is higher than that of the plasmas 29 positioned at the lower part of the inner wall of the gap 14; next, the deposition of the second dielectric layer 23 is continued using one or more thin film processes.

In actual operation, the alternating electromagnetic polar plate 25 is arranged on the side surface of the substrate 10 to form an alternating magnetic field 27 in the horizontal direction, and the plasma 29 moves horizontally under the action of the alternating magnetic field 27, so that the plasma 29 is more easily adsorbed on the bit line layer 13, the first dielectric layer 16 and the side wall of the gap 14; meanwhile, the alternating electrode plates 26 are respectively arranged above and below the substrate 10 to form an alternating electric field 28 in the vertical direction, the plasma 29 is moved upwards or downwards by changing the bias voltage of the alternating electric field 28, so that the sinking speed of the plasma 29 is regulated, the plasma 29 is more easily absorbed at the upper parts of the side walls of the bit line layer 13, the first dielectric layer 16 and the gap 14, namely, the top opening of the gap 14 when sinking, and only a small amount of the plasma 29 reaches the lower part of the gap 14, so that the density of the plasma 29 at the upper part of the inner wall of the gap 14 is higher than that of the plasma 29 at the lower part of the inner wall of the gap 14, and thus, the thickness of the finally formed second dielectric layer 23 covering the upper part of the inner wall of the gap 14 is higher than that of the second dielectric layer 23 covering the lower part of the inner wall of the gap 14 by selectively absorbing the plasma at the surface of the semiconductor structure, so that the second dielectric layer 23 can rapidly close the opening of the gap 22, and the gap 22 can be ensured to have a sufficient volume while closing the gap 14, and the effect of reducing parasitic capacitance is improved. More specifically, when the nitrogen treatment is performed on the semiconductor structure, the frequency of the alternating magnetic field 27 and the frequency of the alternating electric field 28 are kept uniform, so that the plasma 29 is more quickly and accurately guided to the top opening of the gap 14, and the effect of the nitrogen treatment is improved. The material of the second dielectric layer 23 comprises a nitride, for example silicon nitride.

In one embodiment, the air gap 22 extends into the bit line contact hole S1, so that parasitic capacitance between the bit line contact plug 131 and the storage node contact plug 21 can be reduced. In some embodiments, the upper surface of the air gap 22 is higher than the upper surface of the bit line conductive layer 132, which can improve the effect of reducing parasitic capacitance.

In practice, the contact pads LP may be deposited by one or more thin film deposition processes, such as Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), electroplating, chemical Vapor Deposition (CVD)Plating, sputtering, evaporating, or any combination thereof. The material of the contact pad LP comprises tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSi) _x 、CoSi _x 、NiSi _x 、AlSi _x Etc.), a metal alloy, or any combination thereof, e.g., tungsten.

In actual operation, the second dielectric layer 23 may be formed after the storage node contact plugs 21 are formed and before the contact pads LP are formed, so that the finally formed contact pads LP also cover part of the second dielectric layer 23. In the embodiment of the disclosure, the gap 14 is formed before the contact pad LP is formed, and the second dielectric layer 23 is formed to close the gap 14 to form the air gap 22, so that compared with the formation of the air gap after the contact pad is formed in the related art, the manufacturing process of the semiconductor structure is simplified, the process cost is reduced, and on the other hand, the semiconductor structure is relatively simple, the process difficulty of forming the gap 14 and closing the gap 14 is reduced, the formation of the complete air gap 22 is facilitated, the parasitic capacitance between the adjacent bit line layers 13 and between the bit line layers 13 and the storage node contact plugs 21 is effectively reduced, and the performance of the semiconductor structure is improved.

In one embodiment, substrate 10 includes an array region 101 and a peripheral region 102, and isolation barrier 32 and bit line layer 13 are formed in array region 101; the semiconductor structure further includes: a device structure 18 located in the peripheral region 102 and an insulating layer 19 of the substrate 10 covering the device structure 18 and the peripheral region 102; at least one peripheral contact hole S3 located in the peripheral region 102, penetrating the insulating layer 19 and exposing the device structure 18; a peripheral contact plug V filling the peripheral contact hole S3; at least one metal layer M is located on the insulating layer 19 and electrically connected to the peripheral contact plugs V. The metal layer M is electrically connected to the device structure 18 through the peripheral contact plugs V.

In one embodiment, the isolation structures 11 and the active region 12 are formed in the array region 101 and the peripheral region 102, and the device structure 18 is a transistor formed on the active region 12, and the transistor includes a gate conductive layer 181, a gate cap layer 182 covering the gate conductive layer 181, a gate sidewall layer 183 covering sidewalls of the gate conductive layer 181 and sidewalls and an upper surface of the gate cap layer 182, and a source (not identified) and a drain (not identified) located on both sides of the gate conductive layer 181 and formed in the active region 12. The gate conductive layer 181 may have a multi-layered structure. In some embodiments, gate conductive layer 181 and gate cap layer 182 are formed in the same step as bit line conductive layer 132 and bit line cap layer 133. In one embodiment, the peripheral contact plugs V are electrically connected to source electrodes (not shown) and drain electrodes (not shown) located on both sides of the gate conductive layer 181.

The insulating layer 19 may also have a multilayer structure. In a specific embodiment, the insulating layer 19 includes a first insulating layer 191 and a second insulating layer 192 covering the first insulating layer 191, the material of the first insulating layer 191 includes, but is not limited to, an oxide (e.g., silicon oxide), and the material of the second insulating layer 192 includes, but is not limited to, a nitride (e.g., silicon nitride).

It should be noted that the foregoing description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application, but any modifications, equivalents, improvements, etc. made within the spirit and principles of the present application are intended to be included in the scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing an initial structure, wherein the initial structure comprises a substrate and an active region positioned in the substrate; a plurality of bit line structures and a plurality of isolation barriers are formed on the substrate, and the bit line structures and the isolation barriers are intersected with each other to define a plurality of openings exposing the active area; the bit line structure comprises a bit line layer, a sacrificial layer and a first dielectric layer, wherein the sacrificial layer covers the side wall of the bit line layer, the first dielectric layer at least covers the sacrificial layer, and the bit line layer at least comprises a bit line conducting layer;

opening the top of the first dielectric layer and removing the sacrificial layer, forming a gap between the first dielectric layer and the side wall of the bit line layer, wherein the gap and the storage node contact plug are separated by the first dielectric layer, and the upper surface of the reserved first dielectric layer is higher than the upper surface of the storage node contact plug;

forming a second dielectric layer on the substrate by adopting a selective rapid plasma nitrogen treatment process, comprising: introducing a first nitrogen source gas to form plasma, wherein the plasma is guided to the inner wall of the gap under the combined action of an alternating magnetic field and an alternating electric field, and the density of the plasma on the upper part of the inner wall of the gap is higher than that of the plasma on the lower part of the inner wall of the gap; introducing a first silicon source gas, wherein the first silicon source gas is adsorbed on the plasma; introducing a second nitrogen source gas to form a second medium layer at least covering the inner wall of the gap, wherein the thickness of the second medium layer at the upper part of the inner wall of the gap is larger than that at the lower part of the inner wall of the gap; the step of introducing the first silicon source gas and the second nitrogen source gas is carried out again until the second dielectric layer closes the top opening of the gap, the area of the gap not filled by the second dielectric layer is defined as an air gap, and the upper surface of the air gap is higher than the upper surface of the bit line conducting layer;

2. The method of manufacturing of claim 1, wherein providing the initial structure comprises:

providing a substrate;

3. The method of manufacturing of claim 1, wherein opening the top of the first dielectric layer and removing the sacrificial layer comprises:

and removing the remaining sacrificial layer.

4. A method of manufacturing according to claim 3, wherein an etching process is performed on the remaining sacrificial layer using an etching gas comprising gaseous hydrogen fluoride to remove the remaining sacrificial layer.

5. The method of manufacturing of claim 1, wherein forming the second dielectric layer using a selective rapid plasma nitrogen treatment process comprises:

the substrate is placed in a first reaction cavity, at least one pair of alternating electromagnetic polar plates and at least one pair of alternating electrode plates are arranged in the first reaction cavity, radio frequency signals are applied to the alternating electromagnetic polar plates and the alternating electrode plates so as to form an alternating magnetic field and an alternating electric field in the first reaction cavity, and the plasma is further guided to the surfaces of the bit line layer and the first medium layer and the top of the storage node contact plug under the action of the alternating magnetic field and the alternating electric field.

6. The method of manufacturing of claim 5, wherein forming the second dielectric layer using a selective rapid plasma nitrogen treatment process further comprises:

and placing the substrate in a second reaction cavity, and introducing the first silicon source gas and the second nitrogen source gas into the second reaction cavity to form a second dielectric layer, wherein the second dielectric layer also covers the surfaces of the bit line layer and the first dielectric layer and the top of the storage node contact plug.

7. The method according to claim 5, wherein any one pair of alternating electromagnetic plates is provided on opposite sides of the substrate, and any one pair of alternating electrode plates is provided above and below the substrate, respectively.

8. The method of manufacturing according to claim 5, wherein the number of alternating electromagnetic plates is 2 pairs, 3 pairs or 4 pairs.

9. The method according to claim 5, wherein the frequency of the alternating magnetic field is equal to or more than 0 and equal to or less than 2000MHz, and the frequency of the alternating electric field is equal to or more than 0 and equal to or less than 2000MHz.

10. The method of manufacturing according to claim 6, further comprising, before forming a contact pad on the storage node contact plug: removing the second dielectric layer covering the top of the storage node contact plug;

Forming a contact pad on the storage node contact plug, comprising:

11. The method of manufacturing of claim 10, wherein the substrate includes an array region and a peripheral region, the isolation barrier and the bit line structure being formed in the array region; the initial structure further comprises a device structure positioned in the peripheral region and an insulating layer covering the device structure and the substrate of the peripheral region;

12. A semiconductor structure, comprising:

a substrate and an active region within the substrate;

a plurality of bit line layers and a plurality of isolation barriers on the substrate, the bit line layers and the isolation barriers intersecting one another to define a plurality of openings exposing the active region, the bit line layers including at least a bit line conductive layer;

a storage node contact plug filling a lower portion of the opening and covering a portion of a sidewall of the first dielectric layer and the active region exposed by the opening, the gap and the storage node contact plug being separated by the first dielectric layer, and an upper surface of the first dielectric layer being higher than an upper surface of the storage node contact plug;

the second dielectric layer is formed by a selective rapid plasma nitrogen treatment process; wherein forming the second dielectric layer comprises: introducing a first nitrogen source gas to form plasma, wherein the plasma is guided to the inner wall of the gap under the combined action of an alternating magnetic field and an alternating electric field, and the density of the plasma on the upper part of the inner wall of the gap is higher than that of the plasma on the lower part of the inner wall of the gap; introducing a first silicon source gas, wherein the first silicon source gas is adsorbed on the plasma; introducing a second nitrogen source gas to form a second medium layer at least covering the inner wall of the gap, wherein the thickness of the second medium layer at the upper part of the inner wall of the gap is larger than that at the lower part of the inner wall of the gap; the step of introducing the first silicon source gas and the second nitrogen source gas is carried out again until the second dielectric layer closes the top opening of the gap, the area of the gap not filled by the second dielectric layer is defined as an air gap, and the upper surface of the air gap is higher than the upper surface of the bit line conducting layer;

13. The semiconductor structure of claim 12, wherein the substrate comprises an array region and a peripheral region, the isolation barrier and the bit line layer being formed in the array region; the semiconductor structure further includes: a device structure located in the peripheral region and an insulating layer covering the device structure and the substrate of the peripheral region; at least one peripheral contact hole located in the peripheral region, penetrating the insulating layer and exposing the device structure; a peripheral contact plug filling the peripheral contact hole; and at least one metal layer positioned on the insulating layer and electrically connected with the peripheral contact plug.