CN116010311A

CN116010311A - Phase adjustment method, apparatus, electronic device, and readable storage medium

Info

Publication number: CN116010311A
Application number: CN202310297569.8A
Authority: CN
Inventors: 鲁勇; 丁萌; 刘波
Original assignee: Beijing Intengine Technology Co Ltd
Current assignee: Beijing Intengine Technology Co Ltd
Priority date: 2023-03-24
Filing date: 2023-03-24
Publication date: 2023-04-25

Abstract

The application discloses a phase adjustment method, a device, an electronic device and a readable storage medium, wherein the phase adjustment method comprises the following steps: obtaining a preset storage capacity of a virtual memory; setting the initial phase to a preset value; starting a BIST circuit, and performing phase scanning on the control of the BIST circuit based on the set initial phase; when the BIST circuit is detected to scan to a termination phase, an optimal phase is calculated, and phase adjustment is performed based on the optimal phase. The phase adjustment scheme provided by the application can ensure that the phase adjustment is carried out quickly and with heavy load, and no extra circuit is required to be added.

Description

Phase adjustment method, apparatus, electronic device, and readable storage medium

Technical Field

The present invention relates to the field of communications, and in particular, to a phase adjustment method, a phase adjustment device, an electronic device, and a readable storage medium.

Background

With the rapid development of portable devices and mobile terminal products, various applications previously applied to a PC (personal computer) are also applied to a handheld terminal, and such applications are increasingly complex, and the complexity of the applications necessarily requires that the memory access bandwidths of a baseband processor and an application processor applied to the handheld terminal be sufficiently large, so that the DDR (double data Rate) controller can be increasingly applied to a baseband chip, an application processor chip or an SOC chip of the handheld terminal.

DQS (Bidirectional data strobe), bi-directional data filtered signal) phase delay technology is an important technical point on DDR. In the cycle of reading DDR data, DQ signals output by the DDR are in edge alignment with DQS signals, and in order to acquire DQ signals by using DQS as a strobe signal, DQS signals sent by an interface are delayed by 1/4SDCLK (clock period) relative to the DQ signals, so that DQS is ensured to be in the center of an effective data window, and the stability and the accuracy of data reading are ensured.

In the current phase adjustment scheme, the read equalization module in the port physical layer is utilized for processing, and the method has the advantages of heavy and fast load, but requires an additional circuit for realizing; if the port physical layer does not have a read equalization module, the phase adjustment needs to be performed by software, and the load is low and the speed is low.

Disclosure of Invention

In view of the above technical problems, the present application provides a phase adjustment method, apparatus, electronic device, and readable storage medium, which can ensure that the phase adjustment is performed quickly and with a heavy load, and without adding additional circuits.

In order to solve the above technical problems, the present application provides a phase adjustment method, including:

obtaining a preset storage capacity of a virtual memory;

setting the initial phase to a preset value;

starting a BIST circuit, and performing phase scanning on the control of the BIST circuit based on the set initial phase;

when the BIST circuit is detected to scan to a termination phase, an optimal phase is calculated.

Optionally, in some embodiments of the present application, the calculating the optimal phase when the BIST circuit is detected to scan to a termination phase includes:

when the BIST circuit is detected to scan to a termination phase, detecting whether the scanned phase is correct;

and calculating an optimal phase based on the detection result, and performing phase adjustment based on the optimal phase.

Optionally, in some embodiments of the present application, the calculating the optimal phase based on the detection result includes:

extracting a correct phase from the detection result;

determining a longest correct phase segment based on the timing of the correct phase;

and taking the median value of the correct phase section to determine the optimal phase.

Optionally, in some embodiments of the present application, further includes:

when the BIST circuit is detected not to scan to the termination phase, the step of starting the BIST circuit is returned to be executed until the BIST circuit scans to the termination phase.

Optionally, in some embodiments of the present application, the performing, based on the set initial phase, phase scanning at the control of the BIST circuit includes:

determining the phase number to be scanned;

based on the set initial phase, determining a first usable phase value of the left phase and a last usable phase value of the right phase of the initial phase;

and according to the determined phase value, performing phase scanning under the control of the BIST circuit.

Correspondingly, the application also provides a phase adjustment device, which comprises:

the acquisition module is used for acquiring the preset storage capacity of the virtual memory;

the setting module is used for setting the initial phase to a preset value;

a start module for starting the BIST circuit;

the scanning module is used for carrying out phase scanning on the basis of the set initial phase and the control of the BIST circuit;

and the calculating module is used for calculating the optimal phase when the BIST circuit is detected to scan to the termination phase.

Optionally, in some embodiments of the present application, the computing module includes:

a detection unit for detecting whether the scanned phase is correct when the BIST circuit is detected to scan to a termination phase;

and a calculation unit for calculating an optimal phase based on the detection result and performing phase adjustment based on the optimal phase.

Optionally, in some embodiments of the present application, the computing unit is configured to: extracting a correct phase from the detection result; determining a longest correct phase segment based on the timing of the correct phase; and taking the median value of the correct phase section to determine the optimal phase.

The application also provides an electronic device comprising a memory storing a computer program and a processor implementing the steps of the method as described above when executing the computer program.

The present application also provides a computer storage medium storing a computer program which, when executed by a processor, implements the steps of the method as described above.

As described above, the present application provides a phase adjustment method, apparatus, electronic device, and readable storage medium, the phase adjustment method including: obtaining a preset storage capacity of a virtual memory; setting the initial phase to a preset value; starting a BIST circuit, and performing phase scanning on the control of the BIST circuit based on the set initial phase; when the BIST circuit is detected to scan to a termination phase, an optimal phase is calculated, and phase adjustment is performed based on the optimal phase. In the phase adjustment scheme provided by the application, the BIST circuit is utilized to perform phase scanning, the optimal phase is calculated based on the scanning result, and finally, the phase adjustment is performed according to the optimal phase, so that the phase adjustment can be performed quickly and with a heavy load, and no additional circuit is required to be added.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a phase adjustment system according to an embodiment of the present disclosure;

fig. 2 is a schematic flow chart of a phase adjustment method according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a phase adjustment device according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an intelligent terminal provided in an embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present application, and are not of specific significance per se. Thus, "module," "component," or "unit" may be used in combination.

The embodiments related to the present application are specifically described below, and it should be noted that the order of description of the embodiments in the present application is not limited to the priority order of the embodiments.

The embodiment of the application provides a phase adjustment method, a phase adjustment device, a storage medium and electronic equipment. Specifically, the phase adjustment method of the embodiment of the present application may be an electronic device, where the electronic device may be a terminal. The electronic device may be an electronic device such as a smart phone, a tablet computer, a notebook computer, a touch screen, a game console, a personal computer (PC, personalComputer), a personal digital assistant (Personal Digital Assistant, PDA), etc., and the electronic device may further include a client, which may be a phase adjustment client or other clients. The electronic device can be connected with the server in a wired or wireless mode, the server can be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, and a cloud server for providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, basic cloud computing services such as big data and artificial intelligent platforms and the like.

For example, when the phase adjustment method is operated in the electronic device, the electronic device acquires a preset storage capacity of the virtual memory, then the electronic device sets an initial phase to a preset value, then the electronic device starts the BIST circuit, performs phase scanning under control of the BIST circuit based on the set initial phase, calculates an optimal phase when the BIST circuit detects a scan-to-end phase, and performs phase adjustment based on the optimal phase.

Referring to fig. 1, fig. 1 is a schematic system diagram of a phase adjustment device according to an embodiment of the present application. The system may include at least one electronic device 1000, at least one server or personal computer 2000. The electronic device 1000 held by the user may be connected to different servers or personal computers through a network. The electronic device 1000 may be an electronic device having computing hardware capable of supporting and executing software products corresponding to multimedia. In addition, the electronic device 1000 may also have one or more multi-touch sensitive screens for sensing and obtaining input from a user through touch or slide operations performed at multiple points of the one or more touch sensitive display screens. In addition, the electronic device 1000 may be connected to a server or a personal computer 2000 through a network. The network may be a wireless network or a wired network, such as a Wireless Local Area Network (WLAN), a Local Area Network (LAN), a cellular network, a 2G network, a 3G network, a 4G network, a 5G network, etc. In addition, the different electronic devices 1000 may be connected to other embedded platforms or to a server, a personal computer, or the like using their own bluetooth network or hotspot network. The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, basic cloud computing services such as big data and artificial intelligent platforms.

The embodiment of the application provides a phase adjustment method which can be executed by electronic equipment. The electronic equipment comprises a touch display screen and a processor, wherein the touch display screen is used for presenting a graphical user interface and receiving an operation instruction generated by a user acting on the graphical user interface. When a user operates the graphical user interface through the touch display screen, the graphical user interface can control local content of the electronic equipment by responding to a received operation instruction, and can also control content of a server side by responding to the received operation instruction. For example, the user-generated operational instructions acting on the graphical user interface include instructions for processing the initial audio data, and the processor is configured to launch a corresponding application upon receiving the user-provided instructions. Further, the processor is configured to render and draw a graphical user interface associated with the application on the touch-sensitive display screen. A touch display screen is a multi-touch-sensitive screen capable of sensing touch or slide operations performed simultaneously by a plurality of points on the screen. The user performs touch operation on the graphical user interface by using a finger, and when the graphical user interface detects the touch operation, the graphical user interface controls the graphical user interface of the application to display the corresponding operation.

According to the phase adjustment scheme, the BIST circuit is utilized for carrying out phase scanning, the optimal phase is calculated based on the scanning result, and finally, the phase adjustment is carried out according to the optimal phase, so that the phase adjustment can be carried out quickly and with a heavy load, and no additional circuit is required.

The following will describe in detail. It should be noted that the following description order of embodiments is not a limitation of the priority order of embodiments.

A phase adjustment method, comprising: obtaining a preset storage capacity of a virtual memory; setting the initial phase to a preset value; starting the BIST circuit, and performing phase scanning on the control of the BIST circuit based on the set initial phase; when the BIST circuit is detected to scan to the final phase, an optimal phase is calculated, and phase adjustment is performed based on the optimal phase.

Referring to fig. 2, fig. 2 is a flow chart of a phase adjustment method according to an embodiment of the present application. The specific flow of the digital phase adjustment method can be as follows:

101. and obtaining the preset storage capacity of the virtual memory.

Virtual memory is a technique for memory management in computer systems. It allows the application to assume that it has continuous available memory (a continuous complete address space), while in practice it is typically divided into multiple physical memory fragments, with portions temporarily stored on external disk storage for data exchange when needed. Most operating systems use virtual memory, and user programs in virtual memory space are programmed according to virtual addresses and stored in auxiliary memory. When the program runs, the address conversion mechanism calls a part of the program into real memory according to the real address space allocated to the program at the time. When each access is performed, it is first determined whether the portion corresponding to the virtual address is in real memory: if yes, address conversion is carried out, and the main memory is accessed by using a real address; otherwise, the partial program in the auxiliary memory is scheduled into the memory according to a certain algorithm, and then the main memory is accessed according to the same method.

The preset storage capacity of the virtual memory may be 4000 bytes (byte), 8000 bytes, 16000 bytes, or specifically set according to practical situations. In some embodiments, 4000 bytes are used as the preset storage capacity for virtual memory.

102. The initial phase is set to a preset value.

For example, the initial phase of the bi-directional data filter signal (Bidirectionaldata strobe, DQS) may be set by software, the DQS functioning as a clock signal primarily to accurately distinguish each transmission cycle in one clock cycle and to facilitate accurate receipt of data by the receiver. Each 8bit DRAM chip has a DQS signal line which is bi-directional and is used to transmit DQS signals from the master chip during writing, and DQS signals are generated by the DRAM chip to the master for transmission during reading, and DQS signals and data signals are generated simultaneously during reading. Whereas the CL in DDR memory, i.e., the interval from CAS issue to DQS generation, the time interval during which data is actually present on the data I/O bus relative to DQS triggering is called tAC. In fact, when DQS is generated, the pre-fetching inside the chip is done, and due to the pre-fetching, the actual data out may occur ahead of DQS (data out ahead of DQS). Because of the parallel transfer, DDR memory also has a certain requirement for tAC, the allowable range of tAC is + -0.75 ns for DDR266, + -0.7 ns for DDR333, where CL includes a period of DQS lead-in.

DQS is transmitted synchronously with the data during read and is not based on the upper and lower edges of DQS during reception, if there is a significant risk of distinguishing data periods based on the upper and lower edges of DQS. Because of the prefetch operation of the chip, the synchronization at output is difficult to control, and can only be limited to a certain time range, the data may appear at a certain interval from DQS at a certain time of occurrence of each I/O port, which is why there is a tAC rule. While on the receiving side everything has to guarantee synchronous reception, there cannot be deviations such as tAC. Thus, during writing, the DRAM chip does not generate DQS by itself, and takes DQS transmitted by the sender as a reference, and delays for a certain time correspondingly, and the middle part of the DQS is used for selecting a division point (the division point is the upper edge and the lower edge during reading) of a data period, so that two transmission periods are separated. This has the advantage that since each data signal has a logic level hold period, even if not synchronized during transmission, it is in the hold period at both the DQS upper and lower edges, where the accuracy of the data reception trigger is undoubtedly highest.

Specifically, the initial phase of DQS may be set to 0by software, or may be set to other values, which may be specifically selected according to the actual situation, which is not described herein.

103. The BIST circuit is started, and based on the set initial phase, phase scanning is performed under control of the BIST circuit.

BIST (built-in self Test) technology is one implementation of a testability design, and "built-in" means that the Test vectors of the pointer to the memory are automatically generated by built-in memory Test logic, rather than by an external Test Equipment (ATE), and BIST can be broadly divided into two types: logicBIST (LBIST) and MemoryBIST (MBIST) , LBSIT is typically used to test random logic circuits, typically using a pseudo-random test pattern generator to generate input test patterns for use in device internal mechanisms; and a multiple input register (MISR) is employed as the get output signal generator. The MBSIT is used only for memory testing, and a typical MBSIT contains test circuitry for loading, reading and comparing test patterns. It can be seen that the solution of the present application does not need to add an additional circuit, but adopts an internal BIST circuit, i.e. the BIST circuit for testing is applied to the phase adjustment, and then, after the BIST circuit is started, the phase scanning can be performed under the control of the BIST circuit based on the set initial phase, for example, the number of phases to be scanned can be determined, and the phase scanning can be performed based on the initial phase, i.e. optionally, in some embodiments, the step of "starting the BIST circuit and performing the phase scanning under the control of the BIST circuit based on the set initial phase" may specifically include:

(11) Determining the phase number to be scanned;

(12) Based on the set initial phase, determining a first usable phase value of the left phase and a last usable phase value of the right phase of the initial phase;

(13) Based on the determined phase value, a phase scan is performed under control of the BIST circuit.

For example, all 256 phases are scanned starting from 0 (initial phase). The left Bian Xiangwei finds the first usable phase value, the right phase finds the last usable phase (termination phase), and the phase scan is performed under control of the BIST circuit according to the determined phase value.

104. When the BIST circuit is detected to scan to the final phase, an optimal phase is calculated, and phase adjustment is performed based on the optimal phase.

Upon detecting the BIST scan to the termination phase, it may be detected whether the phase of its scan is correct, and the phase adjustment may be performed based on the detection result, that is, optionally, in some embodiments, the step of "calculating the optimum phase when the BIST circuit scan to the termination phase is detected" may specifically include:

(21) When the BIST circuit is detected to scan to a termination phase, detecting whether the scanned phase is correct;

(22) The optimal phase is calculated based on the detection result.

For example, in particular, the correct phase may be extracted, and the optimal phase is determined based on the longest correct phase segment, i.e. optionally, in some embodiments, the step of "calculating the optimal phase based on the detection result" may specifically include:

(31) Extracting a correct phase from the detection result;

(32) Determining a longest correct phase segment based on the timing of the correct phase;

(33) The median value of the correct phase segment is taken to be determined as the best phase.

For example, detecting the correct phase is: phase a, phase B, phase C, phase D, phase E, phase F, phase G, phase H and phase I, wherein phase a is a discrete phase, phase B, phase C and phase D are continuous phase segments, and phase E, phase F, phase G, phase H and phase I are continuous phase segments, so phase E-phase I can be determined as the longest correct phase segment, and then the median of the correct phase segment can be taken to determine as the optimal phase.

In addition, it should be noted that when the BIST circuit is detected not to scan to the termination phase, the step of starting the BIST circuit is returned to be executed until the BIST circuit scans to the termination phase, that is, it may be understood that after the BIST circuit is started, the software may record the scan result of the BIST circuit, then, after the BIST circuit is turned off, it is detected whether the BIST circuit scans to the termination phase, and when the BIST circuit is detected not to scan to the termination phase, the step of starting the BIST circuit is returned to be executed until the BIST circuit scans to the termination phase.

The above completes the phase adjustment flow of the present application.

As can be seen from the foregoing, the present application provides a phase adjustment method, which obtains a preset storage capacity of a virtual memory, then sets an initial phase to a preset value, then starts a BIST circuit, performs phase scanning under control of the BIST circuit based on the set initial phase, calculates an optimal phase when the BIST circuit scans to a final phase is detected, performs phase adjustment based on the optimal phase, performs phase scanning using the BIST circuit according to the phase adjustment scheme provided in the present application, calculates an optimal phase based on a scanning result, and finally performs phase adjustment based on the optimal phase, so that a load can be ensured, and the phase adjustment can be performed quickly without adding an additional circuit.

In order to facilitate better implementation of the phase adjustment method, the application also provides a phase adjustment device based on the above. Where the meaning of the terms is the same as in the phase adjustment method described above, specific implementation details may be referred to in the description of the method embodiments.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a phase adjustment device provided in the present application, where the phase adjustment device may include an acquisition module 201, a setting module 202, a starting module 203, a scanning module 204, and a calculating module 205, and may specifically be as follows:

the obtaining module 201 is configured to obtain a preset storage capacity of the virtual memory.

A setting module 202, configured to set the initial phase to a preset value.

For example, the initial phase of the bi-directional data filtering signal (Bidirectional data strobe, DQS) may be set by software, specifically, the initial phase of DQS may be set to 0by software, or of course, may be set to other values, specifically, may be selected according to the actual situation, which is not described herein.

A start module 203 for starting the BIST circuit.

A scanning module 204, configured to perform phase scanning under control of the BIST circuit based on the set initial phase.

For example, the scanning module 204 may determine the number of phases to be scanned, and perform phase scanning based on the initial phase, that is, optionally, in some embodiments, the scanning module 204 may specifically be configured to: determining the phase number to be scanned; based on the set initial phase, determining a first usable phase value of the left phase and a last usable phase value of the right phase of the initial phase; based on the determined phase value, a phase scan is performed under control of the BIST circuit.

A calculation module 205 for calculating an optimal phase when the BIST circuit scan to a final phase is detected, and performing phase adjustment based on the optimal phase.

Upon detecting that the BIST scans to a termination phase, the computing module 205 may detect whether the phase of its scan is correct and make a phase adjustment based on the detection result, i.e., optionally, in some embodiments, the computing module 205 may specifically include:

a detection unit for detecting whether the scanned phase is correct when the BIST circuit is detected to scan to the termination phase;

and a calculation unit for calculating an optimal phase based on the detection result.

Alternatively, in some embodiments, the computing unit may be specifically configured to: extracting a correct phase from the detection result; determining a longest correct phase segment based on the timing of the correct phase; the median value of the correct phase segment is taken to be determined as the best phase.

Alternatively, in some embodiments, the computing module 205 may be configured to: when it is detected that the BIST circuit does not scan to the termination phase, the step of starting the BIST circuit is returned until the BIST circuit scans to the termination phase.

The above completes the phase adjustment flow of the present application.

As can be seen from the foregoing, the present application provides a phase adjustment device, in which the acquisition module 201 acquires a preset storage capacity of a virtual memory, the setting module 202 sets an initial phase to a preset value, the starting module 203 starts a BIST circuit, the scanning module 204 performs phase scanning under control of the BIST circuit based on the set initial phase, the calculation module 205 calculates an optimal phase when detecting that the BIST circuit scans to a final phase, performs phase adjustment based on the optimal phase, performs phase scanning using the BIST circuit in the phase adjustment scheme provided in the present application, calculates an optimal phase based on a scanning result, and finally performs phase adjustment according to the optimal phase, so as to ensure that the load is heavy and the phase adjustment is performed quickly, and no additional circuit is required.

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor.

The embodiment of the present invention further provides an electronic device 500, as shown in fig. 4, where the electronic device 500 may integrate the above-mentioned phase adjustment device, and may further include a Radio Frequency (RF) circuit 501, a memory 502 including one or more computer readable storage media, an input unit 503, a display unit 504, a sensor 505, an audio circuit 506, a wireless fidelity (WiFi, wireless Fidelity) module 507, a processor 508 including one or more processing cores, and a power supply 509. Those skilled in the art will appreciate that the electronic device 500 structure shown in fig. 4 is not limiting of the electronic device 500 and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components. Wherein:

the RF circuit 501 may be configured to receive and send information or signals during a call, and in particular, after receiving downlink information of a base station, the downlink information is processed by one or more processors 508; in addition, data relating to uplink is transmitted to the base station. Typically, RF circuitry 501 includes, but is not limited to, an antenna, at least one amplifier, a tuner, one or more oscillators, a subscriber identity Module (SIM, subscriberIdentity Module) card, a transceiver, a coupler, a low noise amplifier (LNA, low NoiseAmplifier), a duplexer, and the like. In addition, RF circuitry 501 may also communicate with networks and other devices via wireless communications. The wireless communication may use any communication standard or protocol including, but not limited to, global system for mobile communications (GSM, global Systemof Mobile communication), universal packet Radio Service (GPRS, generalPacket Radio Service), code division multiple access (CDMA, code DivisionMultiple Access), wideband code division multiple access (WCDMA, wideband CodeDivision Multiple Access), long term evolution (LTE, long TermEvolution), email, short message Service (SMS, shortMessaging Service), and the like.

The memory 502 may be used to store software programs and modules, and the processor 508 executes the software programs and modules stored in the memory 502 to perform various functional applications and information processing. The memory 502 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function (such as a sound playing function, a target data playing function, etc.), and the like; the storage data area may store data created according to the use of the electronic device 500 (such as audio data, phonebooks, etc.), and the like. In addition, memory 502 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 502 may also include a memory controller to provide access to the memory 502 by the processor 508 and the input unit 503.

The input unit 503 may be used to receive input numeric or character information and to generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control. In particular, in one particular embodiment, the input unit 503 may include a touch-sensitive surface, as well as other input devices. The touch-sensitive surface, also referred to as a touch display screen or a touch pad, may collect touch operations thereon or thereabout by a user (e.g., operations thereon or thereabout by a user using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection means according to a predetermined program. Alternatively, the touch-sensitive surface may comprise two parts, a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device and converts it into touch point coordinates, which are then sent to the processor 508, and can receive commands from the processor 508 and execute them. In addition, touch sensitive surfaces may be implemented in a variety of types, such as resistive, capacitive, infrared, and surface acoustic waves. The input unit 503 may comprise other input devices besides a touch-sensitive surface. In particular, other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, mouse, joystick, etc.

The display unit 504 may be used to display information entered by a user or provided to a user as well as various graphical user interfaces of the electronic device 500, which may be composed of graphics, text, icons, video, and any combination thereof. The display unit 504 may include a display panel, which may be optionally configured in the form of a liquid crystal display (LCD, liquid Crystal Display), an Organic Light-emitting diode (OLED), or the like. Further, the touch-sensitive surface may overlay a display panel, and upon detection of a touch operation thereon or thereabout, the touch-sensitive surface is passed to the processor 508 to determine the type of touch event, and the processor 508 then provides a corresponding visual output on the display panel based on the type of touch event. Although in fig. 4 the touch sensitive surface and the display panel are implemented as two separate components for input and output functions, in some embodiments the touch sensitive surface may be integrated with the display panel to implement the input and output functions.

The electronic device 500 may also include at least one sensor 505, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor that may adjust the brightness of the display panel according to the brightness of ambient light, and a proximity sensor that may turn off the display panel and/or backlight when the electronic device 500 is moved to the ear. As one of the motion sensors, the gravitational acceleration sensor may detect the acceleration in each direction (generally, three axes), and may detect the gravity and direction when stationary, and may be used for applications of recognizing the gesture of a mobile phone (such as horizontal/vertical screen switching, related games, magnetometer gesture calibration), vibration recognition related functions (such as pedometer, and knocking), and other sensors such as gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, which may be further configured in the electronic device 500, will not be described herein.

Audio circuitry 506, speakers, and a microphone may provide an audio interface between the user and the electronic device 500. The audio circuit 506 may transmit the received electrical signal after audio data conversion to a speaker, where the electrical signal is converted into a sound signal for output; on the other hand, the microphone converts the collected sound signals into electrical signals, which are received by the audio circuit 506 and converted into audio data, which are processed by the audio data output processor 508 for transmission via the RF circuit 501 to, for example, another electronic device 500, or which are output to the memory 502 for further processing. Audio circuitry 506 may also include an ear bud jack to provide communication of the peripheral ear bud with electronic device 500.

WiFi belongs to a short-distance wireless transmission technology, and the electronic equipment 500 can help a user to send and receive emails, browse webpages, access streaming media and the like through the WiFi module 507, so that wireless broadband Internet access is provided for the user. Although fig. 4 shows a WiFi module 507, it is understood that it does not belong to the necessary constitution of the electronic device 500, and may be omitted entirely as needed within a range that does not change the essence of the invention.

The processor 508 is a control center of the electronic device 500, connects various parts of the entire handset using various interfaces and lines, and performs various functions of the electronic device 500 and processes data by running or executing software programs and/or modules stored in the memory 502, and invoking data stored in the memory 502, thereby performing overall monitoring of the handset. Optionally, the processor 508 may include one or more processing cores; preferably, the processor 508 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 508.

The electronic device 500 also includes a power supply 509 (e.g., a battery) for powering the various components, which may be logically connected to the processor 508 via a power management system that performs functions such as managing charge, discharge, and power consumption. The power supply 509 may also include one or more of any of a direct current or alternating current power supply, a recharging system, a power failure detection circuit, a power converter or inverter, a power data indicator, and the like.

Although not shown, the electronic device 500 may further include a camera, a bluetooth module, etc., which will not be described herein. In particular, in this embodiment, the processor 508 in the electronic device 500 loads executable files corresponding to the processes of one or more application programs into the memory 502 according to the following instructions, and the processor 508 executes the application programs stored in the memory 502, so as to implement various functions:

obtaining a preset storage capacity of a virtual memory; setting the initial phase to a preset value; starting the BIST circuit, and performing phase scanning on the control of the BIST circuit based on the set initial phase; when the BIST circuit is detected to scan to the final phase, the optimal phase is calculated.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and the portions of an embodiment that are not described in detail in the foregoing embodiments may be referred to in the detailed description of the phase adjustment method, which is not repeated herein.

As can be seen from the above, the electronic device 500 according to the embodiment of the invention can utilize the BIST circuit to perform phase scanning, calculate the optimal phase based on the scanning result, and finally perform phase adjustment according to the optimal phase, so as to ensure that the electronic device is loaded and performs phase adjustment quickly, and no additional circuit is required.

To this end, embodiments of the present application also provide a storage medium having stored thereon a plurality of instructions adapted to be loaded by a processor to perform the steps of the above-described phase adjustment method.

The specific implementation of each operation above may be referred to the previous embodiments, and will not be described herein.

Wherein the storage medium may include: read Only Memory (ROM), random access memory (RAM, random AccessMemory), magnetic or optical disk, and the like.

The steps in any phase adjustment method provided by the embodiment of the present invention can be executed by the instructions stored in the storage medium, so that the beneficial effects that any phase adjustment method provided by the embodiment of the present invention can be achieved, and detailed descriptions of the previous embodiments are omitted herein.

The phase adjustment method, device, system and storage medium provided by the embodiments of the present invention are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the description of the above embodiments is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.

Claims

1. A phase adjustment method, comprising:

obtaining a preset storage capacity of a virtual memory;

setting the initial phase to a preset value;

when the BIST circuit is detected to scan to a termination phase, an optimal phase is calculated, and phase adjustment is performed based on the optimal phase.

2. The method of claim 1, wherein calculating the optimal phase when the BIST circuit is detected to scan to a termination phase comprises:

the optimal phase is calculated based on the detection result.

3. The method of claim 2, wherein calculating the optimal phase based on the detection result comprises:

extracting a correct phase from the detection result;

4. A method according to any one of claims 1 to 3, further comprising:

5. A method according to any one of claims 1 to 3, wherein the phase scanning at the control of the BIST circuit based on the set initial phase comprises:

determining the phase number to be scanned;

6. A phase adjustment device, comprising:

the setting module is used for setting the initial phase to a preset value;

a start module for starting the BIST circuit;

and the calculation module is used for calculating the optimal phase when the BIST circuit is detected to scan to the termination phase, and carrying out phase adjustment based on the optimal phase.

7. The apparatus of claim 6, wherein the computing module comprises:

8. The apparatus of claim 7, wherein the computing unit is configured to: extracting a correct phase from the detection result; determining a longest correct phase segment based on the timing of the correct phase; and taking the median value of the correct phase section to determine the optimal phase.

9. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the phase adjustment method of any one of claims 1 to 5 when the computer program is executed.

10. A readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the phase adjustment method according to any of claims 1 to 5.