CN115995442A

CN115995442A - Package frame, semiconductor package structure and manufacturing method thereof

Info

Publication number: CN115995442A
Application number: CN202211254027.4A
Authority: CN
Inventors: 甘志超
Original assignee: Joulwatt Technology Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2022-10-13
Filing date: 2022-10-13
Publication date: 2023-04-21

Abstract

The invention relates to the technical field of chip packaging, and provides a packaging frame, a semiconductor packaging structure and a manufacturing method thereof, wherein the packaging frame comprises the following components: a plurality of pins, wherein at least one welding point is arranged on the first surface of each pin; and the at least one penetrating groove is arranged on the first surface of a target pin in the plurality of pins and penetrates through the first surface of the target pin, and the target pin corresponds to a pin with the length larger than a preset value in the plurality of pins. The invention can effectively relieve the local thermal stress of the soldering tin between the packaging frame and the semiconductor chip in the process of temperature circulation, and is beneficial to improving the reliability of the packaging structure.

Description

Package frame, semiconductor package structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of chip packaging, in particular to a packaging frame, a semiconductor packaging structure and a manufacturing method thereof.

Background

"packaging technology" is a technology that packages integrated circuits with insulating plastic or ceramic materials. Packaging is important for chips, on one hand, because the chips must be isolated from the outside to prevent corrosion of the chip circuitry by impurities in the air from causing degradation of electrical performance, and on the other hand, the packaged chips are more convenient to install and transport. The quality of packaging technology directly affects the performance of the chip itself and the design and manufacture of the PCB (printed circuit board) to which it is connected, and is therefore of paramount importance.

After the chip is packaged, a series of package reliability checks are needed to be oriented to the market. Currently, flip chips are mainly made of copper materials (e.g., CET) of package frames (e.g., package frames or substrates) due to mismatch of Coefficient of Thermal Expansion (CTE) of materials inside the package _{Copper (Cu)} =17 ppm/°c) with the silicon material of the chip (e.g. CET _{Silicon (Si)} The difference in thermal expansion coefficient between =2.8 ppm/°c) is large, so that the expansion or contraction amount of the package frame is far greater than that of the flip chip in the test process of temperature cycle, so that solder between the copper pillar of the chip and the package frame is subjected to a local thermal stress, fatigue fracture is caused in the continuous cycle process, electrical failure of the chip is caused, and reliability is poor.

Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.

Disclosure of Invention

In order to solve the technical problems, the invention provides a packaging frame, a semiconductor packaging structure and a manufacturing method thereof, wherein through the arrangement of the through groove on the packaging frame, when the packaging frame expands or contracts in the temperature cycle process, part of expansion and contraction can be released through the through groove, so that the local thermal stress of soldering tin between the packaging frame and a semiconductor chip in the temperature cycle process is effectively relieved, and the reliability of the packaging structure is improved.

According to a first aspect of the present invention, there is provided a package frame comprising:

a plurality of pins, wherein at least one welding point is arranged on the first surface of each pin;

and the at least one penetrating groove is arranged on the first surface of a target pin in the plurality of pins and penetrates through the first surface of the target pin, and the target pin corresponds to a pin with the length larger than a preset value in the plurality of pins.

Optionally, the number of the at least one through slot is 1, and is close to the center position of the target pin.

Optionally, the cross-sectional shape of the through groove is one of a positive trapezoid and an inverted trapezoid.

Optionally, the number of the at least one through groove is 2 or more, including at least one first through groove and at least one second through groove which are alternately arranged.

Optionally, the cross-sectional shape of each of the at least one first through-slot is one of a positive trapezoid and an inverted trapezoid, and the cross-sectional shape of each of the at least one second through-slot is the other one of a positive trapezoid and an inverted trapezoid.

Optionally, the at least one first through groove and the at least one second through groove are alternately arranged along the length direction of the target pin.

Optionally, each of the at least one through slot extends in a width direction of the target pin.

Optionally, the first surface of the target pin is provided with a plurality of welding points arranged at intervals, and the at least one penetrating groove penetrates through the first surface of the target pin from a gap of the plurality of welding points.

According to a second aspect of the present invention, there is provided a semiconductor package structure comprising:

a package frame as described above;

the semiconductor chip is fixedly welded on the first surface of the packaging frame in a flip-chip mode, and the semiconductor chip is electrically connected with a plurality of welding points on the packaging frame through a plurality of conductive posts;

and the packaging colloid coats the packaging frame and the semiconductor chip.

Optionally, at least one through groove in the packaging frame is filled with plastic packaging materials.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor package structure, comprising:

providing a packaging frame provided with at least one through slot;

fixedly welding a semiconductor chip on the first surface of the packaging frame in a flip-chip mode;

the encapsulation frame and the semiconductor chip are subjected to plastic encapsulation,

the at least one through groove is arranged on the first surface of a target pin of the packaging frame and penetrates through the first surface of the target pin, and the target pin corresponds to a pin with the length larger than a preset value in a plurality of pins of the packaging frame.

Optionally, the number of the at least one through slot is 1;

the method for arranging at least one through groove on the packaging frame comprises the following steps:

determining a target pin in the package frame;

and etching a through groove extending along the width direction of the target pin at a position close to the center of the target pin.

Optionally, the number of the at least one through groove is 2 or more;

determining a target pin in the package frame;

and etching along the length direction of the target pin to form at least one first through groove and at least one second through groove which are alternately arranged.

The beneficial effects of the invention at least comprise:

according to the embodiment of the invention, the through groove penetrating through the first surface of the target pin is arranged on the first surface of the target pin of the packaging frame, so that when the packaging frame expands or contracts in the temperature cycle process, part of expansion and contraction can be released through the through groove, the local thermal stress of soldering tin between the packaging frame and the semiconductor chip in the temperature cycle process is effectively relieved, the dislocation of the packaging frame and the semiconductor chip in the temperature cycle process and the risk of soldering tin fracture are avoided, and the reliability of the packaging structure is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

Fig. 1 is a schematic structural view of a conventional package frame;

fig. 2 shows a top view of a package frame provided according to a first embodiment of the present invention;

FIG. 3 shows a schematic cross-sectional view of the target pin of FIG. 2;

FIG. 4 shows a schematic cross-sectional view of the first through slot of FIG. 3;

FIG. 5 shows a schematic cross-sectional view of the second through slot of FIG. 3;

fig. 6 shows a top view of a package frame provided according to a second embodiment of the present invention;

FIG. 7 shows a schematic cross-sectional view of the target pin of FIG. 6;

fig. 8 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention;

fig. 9 is a schematic flow chart of a method for manufacturing a semiconductor package according to an embodiment of the present invention.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.

The semiconductor chip package structure is generally composed of a plastic package material, a semiconductor chip (which may also be simply referred to as a chip herein), a package frame (which may also be simply referred to as a frame herein), a conductive post, and solder between the conductive post and the package frame, and the thermal expansion coefficients of the components in the semiconductor chip package structure are inconsistent. As shown in fig. 1, the conventional package frame 10 generally includes a plurality of pins 11 and bonding pads 12 on the plurality of pins 11. Wherein the conductive posts are soldered with the solder joints 12 by solder, thereby realizing electrical connection between the semiconductor chip and the plurality of pins 11.

Taking a flip chip in QFN (Quad Flat No-leads Package) as an example, due to the specificity of the flip chip, the conductive pillars (e.g. copper pillars) on the surface of the chip are relatively dense, so the pins 11 on the corresponding Package frame 10 need to be made relatively slender to draw out the electrical properties of the copper pillars. However, the more the elongated pins 11 are, the larger the expansion amount in the length direction is when the temperature is raised by one degree celsius, and the more the temperature is lowered and shrunk, so that the more the solder on the elongated pins 11 is subjected to larger local thermal stress generated by dislocation between the copper posts on the chip and the welding surface of the frame in the temperature cycle process, and the breakage of the solder at the welding surface of the chip and the frame is easily caused in the repeated temperature raising and lowering processes. Illustratively, in fig. 1, taking the pin 111 in the dashed box as an example, the length of the pin is longest, and the expansion and contraction amount in the temperature cycle test process is greatest, so that the solder on the pin 111 is subjected to larger local thermal stress and is more prone to break than the solder on other pins.

In view of the above problems, the present invention provides a new package frame solution, and when designing a package frame, a through groove penetrating through a first surface of a target pin of the package frame is provided on the first surface of the target pin, so that when the package frame expands or contracts in a temperature cycle process, part of expansion and contraction can be released through the through groove, thereby effectively relieving local thermal stress of solder between the package frame and a semiconductor chip in the temperature cycle process, avoiding dislocation of the package frame and the semiconductor chip in the temperature cycle process and risk of solder fracture, and improving reliability of the package structure.

Example 1

Referring to fig. 2, 3, 4 and 5, the package frame 20 provided in the embodiment of the present invention includes: a plurality of pins 21 and at least one through slot provided on the first surface of the target pin 211. Wherein the target pin 211 corresponds to a pin of the plurality of pins 21 having a length greater than a preset value, in other words, the target pin 211 corresponds to a pin of the plurality of pins 21 having an expansion amount and/or a contraction amount greater than a preset threshold value occurring during a temperature cycle.

It should be noted that, in the package frame disclosed in the present invention, the number of target pins may be one or more, which is not limited in the present invention. When the number of the target pins is multiple, at least one through groove is arranged on each target pin, and the number of the through grooves actually arranged is specifically determined according to the actual length and the shape structure of the corresponding target pin. The corresponding figures of the embodiments of the present invention are merely exemplary illustrations of the package frame having one target pin.

The pins 21 are spaced apart from each other, and the first surface of each pin 21 is provided with at least one solder joint 22, and the solder joint 22 is used for being soldered with a conductive pillar of the semiconductor chip through soldering tin in a subsequent packaging process so as to realize electrical interconnection between the semiconductor chip and the pins 21, except for useless pins. Illustratively, the plurality of pins 21 are each formed of a material having good electrical conductivity, such as copper.

In some examples, the number of bond pads 22 provided on each pin is positively correlated with the length and/or area of the pin, i.e., the longer the length and/or larger the area of a pin, the greater the number of bond pads 22 provided thereon, thereby facilitating ensuring the electrical signal transmission from the pin. For example, the first surface of the target pin 211 is provided with a plurality of soldering points 22 arranged at intervals, and at this time, at least one through slot provided on the target pin 211 penetrates the first surface of the target pin 211 from the gaps of the plurality of soldering points 22. In this way, the influence of the through-grooves on the preset plurality of welding points 22 can be reduced, and the existing finished packaging frame can be reworked to form at least one through-groove. Of course, the through groove may be formed on the target pin 211 first, and then the plurality of solder joints may be formed on the target pin, where at least one through groove on the target pin 211 is still located at the gaps of the plurality of solder joints 22.

Each of the at least one through groove penetrates the first surface of the target pin 211 and extends in the width direction of the target pin 211. Because each target pin 211 is provided with a through groove penetrating through the surface of the target pin, when the target pin expands or contracts, part of expansion and contraction can be released through the through groove, so that the local thermal stress of the soldering tin on the target pin 211 in the process of temperature circulation is effectively relieved, and the risks of dislocation of the target pin 211 and the semiconductor chip in the process of temperature circulation and solder breakage are avoided.

In this embodiment, as shown in fig. 2 and 3, the number of through slots provided on each target pin 211 is 2 or more, and specifically includes at least one first through slot 212 and at least one second through slot 213 that are alternately arranged. In some preferred examples, the at least one first through groove 212 and the at least one second through groove 213 are alternately arranged along the length direction of the target pin 211, so that more through grooves are provided on the target pin 211, the effect of the through grooves on releasing the expansion and/or contraction of the target pin 211 during the temperature cycle is more remarkable, the effect of relieving the local thermal stress of the solder on the target pin 211 during the temperature cycle is better, and the reliability can be further improved. The positions of each first through slot 212 and each second through slot 213 on the target pin 211 may be reasonably set according to the structure of the target pin 211 and the distribution of the solder joints 22 thereon.

In some preferred examples, each of the at least one first through-slot 212 has one of a positive trapezoid and an inverted trapezoid in cross-sectional shape, and each of the at least one second through-slot 213 has the other of a positive trapezoid and an inverted trapezoid in cross-sectional shape. In other words, in the present embodiment, the penetrating grooves provided on each target pin 211 include positive trapezoid penetrating grooves and inverted trapezoid penetrating grooves alternately arranged. It can be understood that the penetrating groove of the regular trapezoid structure can effectively release the shrinkage of the target pin 211 in the temperature cycle process, the penetrating groove of the inverted trapezoid structure can effectively release the expansion of the target pin 211 in the temperature cycle process, and the penetrating groove of the regular trapezoid structure and the penetrating groove of the inverted trapezoid structure which are alternately arranged can effectively release the expansion and the shrinkage of the target pin 211 in the temperature cycle process, so that the effect is better. For example, the cross-sectional shape of each first through groove 212 is a right trapezoid, as shown in fig. 4; and each of the second penetration grooves 213 has an inverted trapezoidal cross-sectional shape as shown in fig. 5.

It should be noted that the descriptions of the cross-sectional shapes of the first through groove 212 and the second through groove 213 in fig. 4 and 5 are merely exemplary. For example, in other embodiments of the present invention, the cross-sectional shape of the first through groove 212 may be a rectangular, parallelogram, or other conventional shape that is easy to process, and similarly, the cross-sectional shape of the second through groove 213 may be a rectangular, parallelogram, inverted triangle, or other conventional shape that is easy to process.

Further, the present embodiment also provides a semiconductor package structure, as shown in fig. 8, including: the package frame 20, the semiconductor chip 40, and the encapsulant 50.

Example two

This embodiment provides another package frame 30 as shown in fig. 6 and 7.

As can be seen from fig. 6 and 7, the package frame 30 provided in this embodiment has substantially the same structure as the package frame 20 provided in the first embodiment, and the same points are understood with reference to the corresponding description of the first embodiment, and are not repeated here.

The difference is that: in the present embodiment, as shown in fig. 6 and 7, the number of through slots provided on each target pin 311 is 1, and is close to the center position of the target pin 311. Illustratively, the cross-sectional shape of the through slot 312 is one of a regular trapezoid, an inverted trapezoid, a rectangle, a parallelogram, an inverted triangle, and other conventional shapes that are easy to machine.

The number of the through slots provided on the target pins in the present embodiment is smaller, so that the support capability of the target pins 311 to the semiconductor chip is stronger, and the time cost and the process cost required for forming the through slots are reduced.

Example III

The embodiment provides a semiconductor packaging structure.

As shown in fig. 8, the semiconductor package structure provided in this embodiment includes: the package frame 20 shown in the foregoing embodiment one (or the package frame 30 shown in the embodiment two), the semiconductor chip 40, and the encapsulant 50.

The structure of the package frame 20 (or the package frame 30) may be understood with reference to the corresponding description in the foregoing embodiment one (or embodiment two). The semiconductor chip 40 is fixedly soldered to the first surface of the package frame 20 (or the package frame 30) in a flip-chip manner, and the semiconductor chip 40 is electrically connected to the plurality of soldering points 22 (the plurality of soldering points 32) on the package frame 20 (or the package frame 30) through the plurality of conductive posts 41. The encapsulant 50 encapsulates the package frame 20 (or package frame 30) and the semiconductor chip 40. Wherein, at least one through groove in the packaging frame 20 (or the packaging frame 30) is filled with plastic packaging material.

It can be appreciated that in the embodiment of the present invention, the at least one through groove separates the first surface of the target pin in the package frame into a plurality of segments, and after the package is completed, the at least one through groove in the package frame is filled with the molding compound. Because the elastic quantity of the plastic packaging material is large, the multi-section expansion quantity of the target pins in the packaging frame in the expansion or contraction process can be buffered in the through grooves, so that the local thermal stress of soldering tin between the packaging frame and the semiconductor chip in the temperature circulation process can be effectively relieved, the dislocation of the packaging frame and the semiconductor chip in the temperature circulation process and the risk of soldering tin fracture are avoided, and the reliability of the semiconductor packaging structure is improved.

Example IV

The present embodiment provides a method of manufacturing a semiconductor package structure for manufacturing and forming the semiconductor package structure shown in fig. 8.

As shown in fig. 9, the manufacturing method includes performing the steps of:

in step S1, a package frame provided with at least one through slot is provided. At least one through groove is arranged on the first surface of the target pin of the packaging frame and penetrates through the first surface of the target pin. And the target pins correspond to pins with lengths larger than a preset value in a plurality of pins of the package frame, or the target pins correspond to pins with expansion and/or contraction larger than a preset threshold in the plurality of pins of the package frame in the process of temperature cycling.

Optionally, the package frame is the package frame shown in the first embodiment or the second embodiment. That is, the number of the through grooves provided in the package frame may be 1, or may be 2 or more.

In some embodiments, when the number of through slots provided on the encapsulation frame is 1, the method of providing at least one through slot on the encapsulation frame includes: determining a target pin in the package frame; a through groove extending in the width direction of the target pin is etched and formed at a position close to the center of the target pin. Wherein, the cross section shape of the formed penetrating groove is one of a positive trapezoid and an inverted trapezoid.

In other embodiments, when the number of through slots provided on the package frame is 2 or more, the method of providing at least one through slot on the package frame includes: determining a target pin in the package frame; at least one first through groove and at least one second through groove which are alternately arranged are etched along the length direction of the target pin. Wherein, the cross section shape of each first through groove in the formed at least one first through groove is one of a positive trapezoid and an inverted trapezoid, and the cross section shape of each second through groove in the formed at least one second through groove is the other one of a positive trapezoid and an inverted trapezoid.

In step S2, the semiconductor chip is fixedly soldered to the first surface of the package frame in a flip-chip manner.

The semiconductor chip is provided with a plurality of conductive columns, each pin of the packaging frame is provided with at least one welding point, and further, the step S2 further comprises welding the plurality of conductive columns on the semiconductor chip with the welding points on the packaging frame.

In step S3, the package frame and the semiconductor chip are subjected to plastic packaging.

The package frame and the semiconductor chip may be plastic-encapsulated with a material having insulating properties and strong bonding force, such as epoxy, to form a semiconductor package structure as shown in fig. 8.

In summary, the embodiment of the invention sets the penetrating groove penetrating the first surface of the target pin on the first surface of the target pin of the packaging frame, so that when the packaging frame expands or contracts in the temperature cycle process, part of expansion and contraction can be released through the penetrating groove, thereby effectively relieving the local thermal stress of soldering tin between the packaging frame and the semiconductor chip in the temperature cycle process, avoiding dislocation of the packaging frame and the semiconductor chip in the temperature cycle process and the risk of solder fracture, and improving the reliability of the packaging structure.

Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims

1. A package frame, comprising:

2. The package frame of claim 1, wherein the at least one through slot is 1 in number and is near a center position of the target pin.

3. The package frame of claim 2, wherein the cross-sectional shape of the through groove is one of a positive trapezoid and an inverted trapezoid.

4. The package frame of claim 1, wherein the at least one through slot has a number of 2 or more, including at least one first through slot and at least one second through slot alternately arranged.

5. The package frame of claim 4, wherein each of the at least one first through-slot has a cross-sectional shape of one of a positive trapezoid and an inverted trapezoid, and each of the at least one second through-slot has a cross-sectional shape of the other of a positive trapezoid and an inverted trapezoid.

6. The package frame of claim 4, wherein the at least one first through slot and the at least one second through slot are alternately arranged along a length direction of the target pin.

7. The package frame of any of claims 1-6, wherein each of the at least one through slot extends in a width direction of the target pin.

8. The package frame of claim 1, wherein the first surface of the target pin is provided with a plurality of soldering points arranged at intervals, and the at least one through slot penetrates the first surface of the target pin from a gap of the plurality of soldering points.

9. A semiconductor package structure, comprising:

the package frame of any one of claims 1-8;

and the packaging colloid coats the packaging frame and the semiconductor chip.

10. The semiconductor package according to claim 9, wherein at least one through slot in the package frame is filled with a molding compound.

11. A method of manufacturing a semiconductor package, comprising:

providing a packaging frame provided with at least one through slot;

12. The manufacturing method of a semiconductor package structure according to claim 11, wherein the number of the at least one through slot is 1;

determining a target pin in the package frame;

13. The manufacturing method of the semiconductor package according to claim 12, wherein the cross-sectional shape of the through groove is one of a positive trapezoid and an inverted trapezoid.

14. The manufacturing method of a semiconductor package according to claim 11, wherein the number of the at least one through groove is 2 or more;

determining a target pin in the package frame;

15. The method of manufacturing a semiconductor package according to claim 14, wherein a cross-sectional shape of each of the at least one first through-slot is one of a positive trapezoid and an inverted trapezoid, and a cross-sectional shape of each of the at least one second through-slot is the other one of a positive trapezoid and an inverted trapezoid.