CN115981944A

CN115981944A - Memory test method, device, equipment and storage medium

Info

Publication number: CN115981944A
Application number: CN202310004896.XA
Authority: CN
Inventors: 连军委
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-03
Filing date: 2023-01-03
Publication date: 2023-04-18

Abstract

The disclosure provides a memory test method, a device, equipment and a storage medium, and relates to the technical field of memory test. The method comprises the steps of obtaining a plurality of memory test units without intersection; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; and matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, and testing the memory based on the matching relation between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection. According to the memory test method, the device, the equipment and the storage medium, the memory is bound with the kernel under the condition that no operating system exists, and the test efficiency is improved.

Description

Memory test method, device, equipment and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory test method, a memory test apparatus, a test device, and a computer-readable storage medium.

Background

DRAM (Dynamic Random Access Memory), also called Memory, is the most common system Memory. DRAM memory is one of the important components in computers, and it is the bridge to communicate with the CPU. All programs in the computer are executed in the memory, so the performance of the memory bank has a great influence on the computer. How to test the memory bank is very important to ensure the normal operation of the memory.

However, most of the memory tests are performed in the operating system, and the multi-core computer runs the multi-process test program for testing, which requires a process scheduler to schedule between different processes. The operating system occupies most of the contents, and accordingly, the testable memory is reduced, and the test efficiency is reduced.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a memory testing method, apparatus, device and storage medium, which at least to some extent overcomes the problem of low testing efficiency of the existing memory provided in the related art.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a memory test method, including: acquiring a plurality of non-intersection memory test units; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; and matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, so as to test the memory based on the matching relation between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

In an embodiment of the present disclosure, the testing the memory based on the matching relationship between the kernel and the memory test unit group includes: determining a target thread corresponding to the kernel according to a preset kernel thread binding relationship; and binding the target thread with the kernel, binding the target thread with the memory test unit group corresponding to the kernel until the kernel is bound with the memory test unit group, and starting the test.

In an embodiment of the present disclosure, the binding the target thread to the memory test unit group corresponding to the core includes: acquiring test parameters of a memory test unit group corresponding to the core; and inputting the test parameters into the target thread to bind the memory test unit group with the target thread.

In an embodiment of the present disclosure, before the determining, according to a preset kernel thread binding relationship, a target thread corresponding to the one kernel, the method further includes: and according to a preset binding rule, constructing a kernel thread binding relationship between kernels and threads.

In one embodiment of the present disclosure, the binding the target thread with the one kernel includes: and binding the target thread with the kernel based on a unified extensible firmware interface.

In an embodiment of the present disclosure, the obtaining a plurality of non-intersecting memory test units includes: determining the number of the memory test units according to the number of the memory particles and the number of the CPU cores; and dividing the memory into a plurality of non-intersection memory test units according to the number of the memory test units, wherein the capacity of each memory test unit is the same.

In an embodiment of the present disclosure, the testing each memory test unit by using a plurality of cores to obtain a test time of each core to each memory test unit includes: and storing the test time of each kernel to each memory test unit in a test time matrix table.

In an embodiment of the present disclosure, the matching, according to the test time of each core to each memory test unit, a memory test unit group for each core includes: dividing the plurality of memory test units into a plurality of memory test unit groups based on the number of the cores; calculating the test time of the plurality of memory test unit groups according to the test time of each kernel to each memory test unit; and if the difference value between the testing time of any two memory testing units is within a preset time range, matching the plurality of memory testing unit groups with the plurality of cores, wherein the memory testing units in one memory testing unit group belong to the same memory particle, and one memory testing unit group corresponds to one core.

In one embodiment of the present disclosure, the method further comprises: if the difference value between the testing time of the two memory testing unit groups is not in the preset time range, adjusting part of the memory testing units in the two memory testing unit groups until the difference value between the testing time of the two memory testing unit groups is in the preset time range.

In an embodiment of the present disclosure, the matching, according to the test time of each core to each memory test unit, a memory test unit group for each core includes: dividing the plurality of memory test units into a plurality of memory test unit groups based on the number of the cores; calculating the average test time value of the memory test unit groups and the test time of the plurality of memory test unit groups according to the test time of each core to each memory test unit; and if the difference value between the testing time of each memory testing unit group and the testing time average value of the memory testing unit groups is within the preset time range, matching the plurality of memory testing unit groups with the plurality of cores, wherein the memory testing units in one memory testing unit group belong to the same memory grain, and one memory testing unit group corresponds to one core.

In one embodiment of the present disclosure, the method further comprises: if the difference value between the testing time of one memory testing unit group and the testing time average value of the memory testing unit groups is not in the preset time range, sequencing the memory testing unit groups according to a preset sequence, and determining a first memory testing unit group corresponding to the maximum testing time and a second memory testing unit group corresponding to the minimum testing time; and exchanging at least one memory test unit in the first memory test unit group and the second memory test unit group until the difference value between the test time of the exchanged memory test unit group and the test time average value of the memory test units is within the preset time range.

In an embodiment of the present disclosure, the test time of the memory test unit group is a sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is an average value of the test times of the memory test units in the memory test unit group.

According to another aspect of the present disclosure, there is also provided a memory test apparatus, including: the acquisition module is used for acquiring a plurality of memory test units without intersection; the time consuming module is used for testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; and the matching module is used for matching the memory test unit groups for the cores according to the test time of each core on each memory test unit, and testing the memory based on the matching relation between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

According to another aspect of the present disclosure, there is also provided a test apparatus comprising a processor and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the memory test method via execution of the executable instructions.

According to another aspect of the present disclosure, there is also provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the memory testing method described above.

According to another aspect of the present disclosure, there is also provided a computer program product comprising a computer program or computer instructions, which is loaded and executed by a processor, so as to make a computer implement the above-mentioned memory test method.

The disclosure provides a memory test method, a device, equipment and a storage medium, which are characterized in that a plurality of non-intersection memory test units are obtained; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and the running time of the cores is close to that of the memory test unit groups bound for each core; the memory test units in each memory test unit group do not have intersection, so that a plurality of memory test units are prevented from being tested by one kernel, the test time is shortened, the physical addresses of the memory test unit groups are independent and do not influence each other, the binding of the memory to the kernel is realized, the test equipment does not need an operating system, thread switching is not needed, and the memory test efficiency is greatly improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural diagram illustrating a multi-CPU multi-core memory test provided in an embodiment of the present disclosure;

FIG. 2 illustrates a diagram of the relationship between programs, processes, and threads in an operating system in an embodiment of the present disclosure;

FIG. 3 illustrates a single-threaded and multi-threaded operation in the same process in an embodiment of the disclosure;

FIG. 4 illustrates a many-to-many model diagram between kernels and threads in an embodiment of the disclosure;

FIG. 5 is a diagram illustrating a one-to-one model between a kernel and a thread provided by an embodiment of the present disclosure;

FIG. 6 is a diagram illustrating a model of a memory, a thread, and a kernel provided by an embodiment of the present disclosure;

fig. 7 shows a flowchart of a memory testing method provided by the embodiment of the present disclosure;

fig. 8 is a flowchart illustrating a method for matching a memory test unit group and a kernel according to an embodiment of the present disclosure;

fig. 9 is a flowchart illustrating another method for matching a memory test unit group and a kernel according to an embodiment of the present disclosure;

fig. 10 is a flowchart illustrating another method for testing a memory according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of a memory test apparatus according to an embodiment of the disclosure;

FIG. 12 is a block diagram of a test apparatus provided by an embodiment of the present disclosure;

fig. 13 shows a schematic diagram of a computer program product provided by an embodiment of the present disclosure.

Detailed Description

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terms "first", "second" and "first" are used herein for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more unless explicitly stated otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In performing DRAM testing, the test equipment typically employs a multi-CPU, multi-core architecture, such as a multi-CPU, multi-core computer. Fig. 1 shows a schematic structural diagram of a multi-CPU multi-core memory test provided in an embodiment of the present disclosure. As shown in fig. 1, the test apparatus includes four CPUs, each CPU includes two cores, each core is connected to a corresponding DRAM to be tested, and test data is stored in a Cache.

In an operating system of a testing device, a program refers to a set of instructions instructing the testing device (e.g., a computer or other device with information processing capability) to perform actions or make decisions, and is usually written in a programming language, and run on a target computer architecture, for example, the program may be written in a C language, a Java language, or the like.

The process is a running activity of a software program in a computer on a certain data set, is a resource such as a basic unit, a memory, a variable and the like for performing resource allocation kernel scheduling by an operating system, and is a foundation of an operating system structure.

A thread is an entity in a process, and is a basic unit allocated by a system independent scheduling core, and the thread does not own resources of an operating system, but can share all resources owned by the process, such as memory, code segments and the like, with other threads of the same process.

It should be noted that a process is an entity of a program, a thread is an entity of a process, and a process is a container of a thread.

Fig. 2 is a diagram illustrating a relationship between a program and a process in an operating system and threads in an embodiment of the present disclosure. As shown in fig. 2, two programs, namely a program a and a program B, are developed in an operating system, where the program a binds to two processes, namely a process 1 and a process 2, the process 1 binds to a thread 1, and the process 2 binds to two threads 1; program B binds a process, program 3 in fig. 2, and program 3 binds a thread 1.

FIG. 3 is a diagram illustrating single-threaded and multi-threaded operations in the same process in an embodiment of the disclosure. As shown in fig. 3, in each single thread or multi-thread, a plurality of time slices are divided. For a single thread, a set program may be executed at each time slice to implement a DRAM test. For multithreading, a plurality of threads share all resources owned by the process, only one of the threads in the multithreading is used for running in a certain time slice, the rest threads in the multithreading are all in a ready state, and only after the threads in the running state run, the scheduler can schedule the rest threads in the ready state.

As shown in fig. 4, in the many-to-many model between CPU cores and threads, there is resource sharing among multiple threads, and the use of shared resources is coordinated with each other, so as to give or obtain the use right of the CPU to execute a slice.

In a scheduling period, when a CPU scheduling time slice arrives, the thread in the running state is saved with context and suspended, the CPU resource is redistributed to the corresponding thread according to a preset algorithm, the current time slice is executed, and after the current time slice is executed, the next scheduling period is started until all the time slices are completed. For example, in a scheduling cycle, when a CPU scheduling time slice arrives, the threads 1 to 3 store the context and suspend, the scheduler allocates the CPU resource (kernel K1) to the thread 1 to execute the current time slice according to a preset algorithm, and the thread 1 enters the next scheduling cycle after finishing executing the current time slice; and the thread 1 to the thread 3 store the context and suspend, and the scheduler redistributes the CPU resource (the kernel K1) to the thread 2 to execute the time slice until all the threads are executed.

In summary, it can be seen that, when a multi-process test program is used to test a DRAM, a scheduler is required to schedule among processes in the presence of an operating system, and the operating system occupies a large portion of memory, and accordingly, the testable memory is reduced; on the other hand, due to the switching between processes and the access time difference of the memory of the core pair, in an extreme case, the testing speed of the memory of one core pair is very slow, while the access efficiency of some memories to some cores is very high, and the random property of the scheduler cannot access the memories, thereby causing the technical problem of low testing efficiency.

Therefore, how to improve the memory testing efficiency becomes one of the problems to be solved urgently.

In order to facilitate a general understanding of the technical solutions provided by the embodiments of the present disclosure, a binding model between a kernel and a thread provided by the embodiments of the present disclosure is described next.

Fig. 5 illustrates a one-to-one model diagram between a kernel and a thread provided by an embodiment of the present disclosure. As shown in fig. 5, for the one-to-one model, one kernel is uniquely used by one thread, the threads and the kernels correspond to each other one by one, and different threads execute independently and concurrently, so that CPU calling can be omitted, switching between threads does not exist, memory testing can be realized without an operating system, and each thread shares CPU resources independently, thereby avoiding occurrence of mutual exclusion or deadlock until program operation is finished.

For example, in fig. 5, the test device includes four kernels K0 to K3, and four threads are set, which are respectively threads 1 to 4, specifically, the kernel K0 is bound to the thread 4, and the kernels K1 to K3 are bound to the threads 1 to 3, respectively, so as to construct a one-to-one model between the CPU kernels and the threads.

Fig. 6 shows a schematic diagram of a model among a memory to be tested, a thread, and a kernel according to an embodiment of the present disclosure. As shown in fig. 6, the parallel mode from the thread perspective means that there is no data sharing or communication among multiple threads, multiple threads can be run by using the parallel capability of the CPU, and the memory test efficiency can be improved without switching the operating system in a one-to-one mode.

Based on this, in the technical scheme provided by the embodiment of the disclosure, a plurality of memory test units without intersection are obtained; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and the running time of the cores is close to that of the memory test unit groups bound for each core; the memory test units in each memory test unit group do not have intersection, so that a plurality of memory test units are prevented from being tested by one kernel, the test time is shortened, the physical addresses of the memory test unit groups are independent and not influenced mutually, the binding of the memory to the kernel is realized, the test equipment does not need an operating system, thread switching is not needed, and the memory test efficiency is greatly improved.

The present exemplary embodiment will be described in detail below with reference to the drawings and examples.

First, an embodiment of the present disclosure provides a memory testing method, which can be executed by any electronic device with computing and processing capabilities.

Fig. 7 shows a flowchart of a memory test method according to an embodiment of the present disclosure. As shown in fig. 7, in an embodiment, a memory testing method includes:

s702, obtaining a plurality of memory test units without intersection.

In one embodiment, the memory test units may be characterized by parameters such as a memory ID, a start address, an end address, and the like, on one hand, address intervals formed by the start address and the end address of different memory test units do not intersect, so that the memory test units are ensured to be independent from each other, and on the other hand, the start address and the end address of adjacent memory test units are continuous, so that the memory can be completely contained in the corresponding memory test unit.

There are various ways to divide the memory into multiple memory test units, for example, the memory test units may be divided according to the number of memory particles and the number of cores of the CPU, or according to multiples of the number of memory particles and the number of cores of the CPU, as long as the divided memory test units have no intersection, which is not particularly limited in this disclosure.

It should be noted that, for the number of the memory test units, on one hand, the memory needs to be divided into the memory test units without intersection as many as possible, and when the test time difference of different threads is large, the test time between each thread is close to that by adjusting part of the memory test units, so as to improve the adjustment flexibility.

S704, testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit.

The purpose of testing the memory test unit by the kernel is to record the time length of once writing data and reading data so as to estimate the time length of the memory test unit when executing the test task.

The testing of each memory test unit by using the plurality of kernels can be realized by writing a certain data into one memory test unit through one kernel, reading data from the memory test unit, comparing whether the written data and the written data are consistent, recording the data writing time and the data reading time, and taking the difference value between the data reading time and the data writing time as the test time of the memory test unit; sequentially testing all the memory test units through the kernel to obtain the test time of the kernel to each memory test unit; and continuously and sequentially testing the residual kernel on each memory test unit to obtain the test time of the residual kernel on each memory test unit.

In one embodiment, the step S704 further includes: and storing the test time of each kernel to each memory test unit in a test time matrix table, wherein the test time matrix table is used for representing the corresponding relation between the test time of each kernel and each memory test unit so as to facilitate follow-up tracking and timely confirm abnormity.

It should be noted that, besides the testing time of the kernel to the memory testing unit is recorded by using the testing time matrix table, the testing time may also be represented in the form of a scatter diagram, etc., which is not specifically limited in this disclosure.

And S706, matching the memory test unit groups for the cores according to the test time of each core on each memory test unit, and testing the memory based on the matching relation between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

The memory test unit group may include at least one memory test unit, and when there are a plurality of memory test units in the memory test unit group, the plurality of memory test units have no intersection to ensure that any two memory test unit groups have no intersection, are independent of each other, do not affect each other, and can implement independent operation of threads.

The test time of the memory test unit group is determined by the test time of the memory test units in the memory test unit group, and may be the sum of the test times of the memory test units in the memory test unit group, or the average value of the test times of the memory test units in the memory test unit group.

The difference value of the test time of the memory test unit groups corresponding to any two cores is limited within a preset time range, so that the test time of each memory test unit group is basically the same, namely, the memory test unit groups start and end at the same time, and the total test time of the memory is shortened.

The preset time range may be preset in the matching module of the testing device, and the preset time range may be determined according to actual conditions, for example, the preset time range may be [0,5ms ], and the like, and is not particularly limited.

It should be noted that the preset time range mentioned above is only an example provided for illustrating the embodiment of the present disclosure, and should not be considered as a limitation of the protection scope of the present disclosure. The value of the preset time range can be determined according to specific conditions.

The memory test method provided by the embodiment of the disclosure includes acquiring a plurality of intersection-free memory test units; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and the running time of the cores is close to that of the memory test unit groups bound for each core; the memory test units in each memory test unit group do not have intersection, so that a plurality of memory test units are prevented from being tested by one kernel, the test time is shortened, the physical addresses of the memory test unit groups are independent and not influenced mutually, the binding of the memory to the kernel is realized, the test equipment does not need an operating system, thread switching is not needed, and the memory test efficiency is greatly improved.

In one embodiment, the plurality of non-intersecting memory test cells in S702 are obtained by: determining the number of memory test units according to the number of the memory particles and the number of the CPU cores; according to the number of the memory test units, the memory is divided into a plurality of non-intersection memory test units, the capacity of each memory test unit is the same, so that the test time of different memory test units is close to or basically the same, and meanwhile, if the capacity of a certain memory test unit is large, one kernel only corresponds to one memory test unit, so that the follow-up kernel cannot be completely distributed to each memory test unit group.

Assuming that the number of memory granules is M, the number of cores of the CPU is K, and the number of memory test units N = M × K, the memory test units segmented by the number of memory granules and the number of cores are independent of each other, and there is no intersection between the memory test units. The memory test unit may be identified with a memory ID, a start address, and an end address for distinguishing the plurality of memories to be tested.

And acquiring the total capacity V of the memory which can be tested by the test system, wherein the capacity E = V/N of each memory test unit.

The memory test units are numbered as a memory test unit 0, a memory test unit 1, \8230, and a memory test unit N-1 in sequence; the inner cores are marked as inner core 0, inner core 1, \8230andinner core K-1 in sequence.

The test units 0-K-1 are tested by using the cores 1-K-1 respectively, and the test time of the cores 1-K-1 to the memory test units 0-K-1 is obtained.

Exemplarily, if the number of the memory granules is 64 and the number of the CPU cores is 4, the memory may be divided into 256 memory test units, and the memory test units are labeled as memory test unit 0, memory test unit 1, \8230, and memory test unit 255; the cores are labeled core 0, core 1, \ 8230;, core 3.

According to the method, the memory test units without intersection are divided through the particle number of the memory and the kernel number of the CPU, on one hand, the memory test units are ensured to be independent and have no intersection, and the divided memory test units have enough number; on the other hand, the divided memory test units can cover all addresses of the memory, and the integrity of the memory test is ensured.

Fig. 8 shows a flowchart of a method for matching a memory test unit group and a kernel according to an embodiment of the present disclosure. As shown in fig. 8, in an embodiment, the step S706, according to the test time of each core to each memory test unit, of matching a memory test unit group for each core includes:

s802, dividing the memory test units into a plurality of memory test unit groups based on the number of the cores.

For the memory test unit division, the memory test unit division is realized according to the number of memory particles and the number of cores, and in order to facilitate operation, a plurality of memory test units are divided into a plurality of memory test unit groups according to the number of cores.

It should be noted that, because the test times of different memory test units are different, each memory test unit group may include the same number of memory test units, or may include different numbers of memory test units, and may be adjusted according to actual conditions.

S804, according to the test time of each core to each memory test unit, the test time of a plurality of memory test unit groups is calculated.

The test time of the memory test unit group may be the sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group may also be the average value of the test times of the memory test units in the memory test unit group. It should be noted that, when the number of the memory test units in the memory test unit group is different, the sum of the test times of the memory test units in the memory test unit group can be only used as the test time of the memory test unit group.

In one embodiment, the testing time of each memory testing unit group, the memory testing unit ID in each memory testing unit group, and other information may be recorded in the testing time statistical table, so as to adjust the memory testing units according to the testing time statistical table.

S806, if the difference between the test times of any two memory test units is within the preset time range, matching the plurality of memory test unit groups with the plurality of cores, where the memory test units in one memory test unit group belong to the same memory granule, and one memory test unit group corresponds to one core.

Calculating the difference value between the test time of any two memory test unit groups, comparing the relation between the difference value and a preset time range, and when the difference value between the test time of any two memory test unit groups is within the preset time range, indicating that the test time of any two memory test unit groups is close, matching the memory test unit groups with the kernels, wherein one memory test unit group corresponds to one kernel, so that the binding of the memory to the kernels is ensured, the memory test efficiency is improved, and the memory test time is shortened.

For example, when the number of cores is 4 and the number of memory test units is 256, the memory test unit group may be divided into 4 memory test unit groups (memory test unit groups 0 to 3) based on the number of cores, and each memory test unit group initially includes 64 memory test units.

Respectively calculating the test time of 64 memory test units in the memory test unit groups 0-3 to obtain the test time of the memory test unit groups 0-3, respectively calculating the difference value of the test time of the memory test unit group 0 and the memory test unit groups 1-3, the difference value of the test time of the memory test unit group 1 and the memory test unit groups 2-3 and the difference value of the test time of the memory test unit group 2 and the memory test unit group 3, judging whether the difference values are in a preset time range, if so, indicating that the test time of the memory test unit groups 0-3 is close, and matching the memory test unit groups 0-3 with the kernels 0-3.

The memory test units in the memory test unit group belong to the same memory grain, so that the test time difference caused by the physical position difference of the grains can be improved.

Optionally, the memory test method provided in the embodiment of the present disclosure further includes: if the difference value between the testing time of the two memory testing unit groups is not in the preset time range, adjusting part of the memory testing units in the two memory testing unit groups until the difference value between the testing time of the two memory testing unit groups is in the preset time range.

In an embodiment, when the difference between the test times of the two memory test unit groups is not within the preset time range, it indicates that the difference between the test times of the two memory test unit groups is large, and it cannot be guaranteed that the threads are simultaneously started and simultaneously ended, which results in long memory test time.

For the two memory test unit groups, the memory test unit in the memory test unit group with longer test time can be exchanged with the memory test unit in the memory test unit group with shorter test time. For example, two memory test unit groups each include 64 memory test units, the test time of one memory test unit group is 3s, the test time of the other memory test unit group is 4s, the difference between the two is 1s, and the preset time range is [0,0.8s ], so that the difference is not within the preset time range, the memory test units in the two memory test unit groups need to be adjusted, when adjusting, a memory test unit with a test time of 200ms in the other memory test unit group may be adjusted into the one memory test unit group, a memory test unit with a test time of 300ms in the other memory test unit group may be adjusted into the one memory test unit group, and a memory test unit with a test time of 100ms in the one memory test unit group may be adjusted into the other memory test unit group.

It should be noted that there are various ways of adjusting the memory test units in the memory test unit groups to make the difference between the test times of the two memory test unit groups within the preset time range, and the above are only examples provided for illustrating the embodiment of the disclosure, and should not be construed as limiting the scope of the disclosure. In an actual implementation process, the memory test units and the number thereof in the memory test unit group that need to be adjusted may be selected according to specific situations, and the disclosure is not limited specifically.

The memory test method provided by the embodiment of the disclosure divides a plurality of memory test units into a plurality of memory test unit groups based on the number of cores, indicates that the test time of each memory test unit group is close when the difference value of the test time of any two memory test unit groups is within a preset time range, matches the memory test unit groups with the cores, indicates that the test time of the two memory test unit groups is different too much when the difference value of the test time of the two memory test unit groups is not within the preset time range, cannot ensure that threads are simultaneously started and simultaneously ended, and makes the test time of the memory test unit groups close by adjusting part of the memory test units.

Fig. 9 is a flowchart illustrating another method for matching a memory test unit group and a kernel according to an embodiment of the present disclosure. As shown in fig. 9, in an embodiment, the step S706 matches, according to the test time of each core to each memory test unit, a memory test unit group for each core, and includes:

s902, dividing the memory test units into a plurality of memory test unit groups based on the number of the cores.

For the memory test unit division, the memory test unit division is realized according to the number of memory particles and the number of cores, and in order to facilitate operation, a plurality of memory test units are divided into a plurality of memory test unit groups according to the number of cores. When the memory test unit groups are initially divided, the number of the memory test units in each memory test unit group is the same.

And S904, calculating the average test time value of the memory test unit groups and the test time of the memory test unit groups according to the test time of each core to each memory test unit.

The test time of the memory test unit group may be the sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is the average value of the test times of the memory test units in the memory test unit group. It should be noted that, when the number of the memory test units in the memory test unit group is different, the test time of the memory test unit is taken as the test time of the memory test unit group after the test time of the memory test unit.

The average test time value of the memory test unit group is obtained according to the test time of the memory test units in the memory test unit group and the number of the memory test units, and the average test time value of the memory test unit group is used as the reference for adjustment.

And S906, if the difference value between the testing time of each memory testing unit group and the testing time average value of the memory testing unit groups is within a preset time range, matching the plurality of memory testing unit groups with the plurality of cores, wherein the memory testing units in one memory testing unit group belong to the same memory grain, and one memory testing unit group corresponds to one core.

In one embodiment, a difference between the test time of each memory test unit group and the average value of the test time of the memory test unit group is calculated, and whether to adjust the memory test unit in the memory test unit group is determined according to a relationship between the difference and a preset time range.

The predetermined time range is configured in the matching module of the testing device in advance, for example, the predetermined time range is [ -0.5s,0.5s ], which may be determined according to practical situations, and the disclosure is not particularly limited.

Optionally, the memory test method provided in the embodiment of the present disclosure further includes: if the difference value between the testing time of one memory testing unit group and the testing time average value of the memory testing unit groups is not within the preset time range, sequencing the memory testing unit groups according to a preset sequence, and determining a first memory testing unit group corresponding to the maximum testing time and a second memory testing unit group corresponding to the minimum testing time; and exchanging at least one memory test unit in the first memory test unit group and the second memory test unit group until the difference value between the test time of the exchanged memory test unit group and the test time average value of the memory test units is within a preset time range.

The preset sequence may be arranged in the memory test unit groups from large to small, or arranged in the memory test unit groups from small to large, the first memory test unit group corresponding to the maximum test time value and the second memory test unit group corresponding to the minimum test time value are selected from the sequencing result, and part of the memory test units in the two memory test unit groups are exchanged until the difference value between the test time value and the test time average value of the two memory test unit groups after exchange is within a preset range.

It should be noted that, when exchanging part of the memory test units, reference may be made to the implementation of the foregoing embodiment, and details are not described here again.

The memory test method provided by the embodiment of the disclosure divides a plurality of memory test units into a plurality of memory test unit groups based on the number of cores, takes the test time average value of the memory test unit groups as an adjustment reference, when the difference value between the test time of the memory test unit groups and the test time average value is within a preset time range, the test time of each memory test unit group is close, and the memory test unit groups are matched with the cores.

Fig. 10 is a flowchart illustrating another memory testing method provided in the embodiment of the present disclosure. On the basis of the embodiment of fig. 7, steps S708 to S710 are added to bind the kernel, the thread, and the memory test unit group, so as to test the memory based on the matching relationship between the kernel and the memory test unit group. In one embodiment, as shown in fig. 10, the method includes S702 to S710, specifically including:

s708, determining a target thread corresponding to one kernel according to the preset kernel thread binding relationship;

and S710, binding the target thread with one kernel, binding the target thread with a memory test unit group corresponding to the kernel until the kernel is bound with the memory test unit group, and starting the test.

In an embodiment, before determining, in S708, according to the preset kernel thread binding relationship, a target thread corresponding to a kernel, the method further includes: and according to a preset binding rule, constructing a kernel thread binding relationship between kernels and threads.

The preset binding rules are used for determining the corresponding relationship between the kernel and the thread, default that the kernel ID and the thread ID are in one-to-one correspondence from small to large, and can also be adjusted according to instructions of testers without specific limitations.

The kernel thread binding relationship is used for indicating the corresponding relationship between the kernel and the thread, and the kernel thread binding relationship can be stored in a binding module of the test equipment in the form of a kernel thread binding relationship table. The kernel thread binding relation table comprises a kernel ID and a thread ID, so that the corresponding relation between the kernel ID and the thread ID is determined, and the target thread can be determined quickly.

And binding the kernel and the thread through a unified extensible firmware interface.

In an embodiment, the step S710 of binding the target thread to the memory test unit group corresponding to the core includes: acquiring test parameters of a memory test unit group corresponding to one core; and inputting the test parameters into the target thread to bind the memory test unit group with the target thread.

The kernel and the memory test unit group corresponding to the kernel realize the test of the memory test unit group through the target thread, and the target thread may be determined according to actual conditions, for example, by presetting a kernel thread binding relationship, and determining the target thread corresponding to the kernel.

The test parameters of the memory test unit group include a memory ID, a start address and an end address of the memory test unit in the memory test unit group, and the like, and the binding of the memory test unit group and the target thread can be realized by inputting the test parameters of the memory test unit group to the target thread.

The method and the device determine the target thread by presetting the binding relationship of the kernel thread, bind the kernel, the target thread and the memory, start the test without a process scheduler, greatly reduce the difficulty of engineering realization, realize the parallel test of the memory test process, improve the test efficiency, and avoid the problems of test influence such as jamming of mutually exclusive resources, transient process jamming and the like.

To facilitate an understanding of the memory test method provided by the present disclosure, the following description is made with reference to specific examples.

The overall flow of the memory test method is as follows:

1. and segmenting the memory test units, and measuring and calculating the test time of each kernel to each memory test unit.

2. And acquiring a memory binding core list of the optimal test time according to the test time.

3. One thread is bound for each kernel, and each thread executes the same test algorithm.

4. And distributing a test memory for the thread bound by the kernel according to the memory kernel bound kernel list.

5. And starting the kernel to test the memory.

For the split memory test unit, measuring and calculating the test time of each core to each memory measurement unit can be realized through the following processes:

a) According to the DRAM memory grain number M and the kernel number K, the number N = M multiplied by K of the memory test units of the memory segmentation;

b) Acquiring the total capacity V of the system-testable memory, and dividing the memory into N memory test units, wherein the capacity E = V/N of each memory test unit;

c) The memory test units are numbered as

test units

0,1,2, \8230andN-1 in sequence;

d) Marking the inner cores as

inner cores

0,1,2, \ 8230;, K-1 in sequence;

e) The

memory test units

0,1,2, \ 8230;, K-1, are tested using

cores

0,1,2, \ 8230;, N-1, respectively, to obtain each memory test unit, and a test time matrix table for each core is used, as shown in Table 1.

TABLE 1 test time matrix Table (unit: ms)

The memory bound core list at the optimal test time can be obtained according to the test time in table 1.

Under the condition that the running test time of each core is guaranteed to be basically the same (namely, the difference value between the test time of any two memory test unit groups is within a preset time range), a memory test unit group and core binding list is obtained according to the test time matrix table, as shown in table 2.

Table 2 memory test unit group and kernel binding list

Test unit ID	0	1	2	3	…	N-4	N-3	N-2	N-1
										Kernel ID	0	1	K-2	1	…	0	K-1	2	K-3

According to the preset kernel thread correspondence, one thread is bound for each kernel, as shown in table 3.

TABLE 3 Kernel thread binding relationship Table

Thread ID	0	1	2	3	…	K-4	K-3	K-2	K-1
										Kernel ID	0	1	2	3	…	K-4	K-3	K-2	K-1

And binding the memory test unit and the thread to realize the binding of the memory to the kernel, as shown in table 4.

TABLE 4 memory Kernel binding List

Test cell ID	0	1	2	3	…	N-4	N-3	N-2	N-1
										Thread ID	0	1	K-2	1	…	0	K-1	2	K-3
Kernel ID	0	1	K-2	1	…	0	K-1	2	K-3

And after the binding of the memory, the thread and the kernel is finished, starting the kernel and starting the test.

Based on the same inventive concept, the embodiment of the present disclosure further provides a memory test apparatus, as described in the following embodiments. Because the principle of solving the problem of the embodiment of the apparatus is similar to that of the embodiment of the method, reference may be made to the implementation of the embodiment of the apparatus, and repeated descriptions are omitted.

Fig. 11 is a schematic structural diagram of a memory test apparatus according to an embodiment of the present disclosure. As shown in fig. 11, in an embodiment, a memory testing apparatus provided in an embodiment of the present disclosure includes an obtaining module 1101, a time consuming module 1102, and a matching module 1103.

The acquiring module 1101 is configured to acquire a plurality of non-intersecting memory test units;

a time consuming module 1102, configured to test each memory test unit by using multiple cores, to obtain test time of each core for each memory test unit;

the matching module 1103 is configured to match the memory test unit groups for the cores according to the test time of each core on each memory test unit, so as to test the memory based on the matching relationship between the cores and the memory test unit groups, where a difference between the test times of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups do not have an intersection.

In one embodiment, the apparatus further includes a binding module, not shown in the drawings, configured to determine a target thread corresponding to one kernel according to a preset kernel thread binding relationship; and binding the target thread with one kernel, binding the target thread with a memory test unit group corresponding to the kernel until the kernel is bound with the memory test unit group, and starting the test.

In one embodiment, the binding module is specifically configured to obtain a test parameter of a memory test unit group corresponding to one core; and inputting the test parameters to a target thread, and binding the memory test unit group with the target thread.

In one embodiment, the apparatus further includes a building module, not shown in the drawings, configured to build a kernel-thread binding relationship between a kernel and a thread according to a preset binding rule.

In one embodiment, the binding module binds the target thread with the one kernel based on a unified extensible firmware interface.

In an embodiment, the obtaining module 1101 is specifically configured to determine the number of memory test units according to the number of grains of the memory and the number of cores of the CPU; according to the number of the memory test units, the memory is divided into a plurality of non-intersection memory test units, and the capacity of each memory test unit is the same.

In one embodiment, the time consuming module 1102 is specifically configured to store the test time of each core for each memory test unit in the test time matrix table.

In one embodiment, the matching module 1103 is configured to divide the plurality of memory test units into a plurality of memory test unit groups based on the number of cores; calculating the test time of a plurality of memory test unit groups according to the test time of each kernel to each memory test unit; and if the difference value between the test time of any two memory test units is within the preset time range, matching the plurality of memory test unit groups with the plurality of cores, wherein the memory test units in one memory test unit group belong to the same memory grain, and one memory test unit group corresponds to one core.

In one embodiment, the matching module 1103 is further configured to adjust a part of the memory test units in the two memory test unit groups until the difference between the test times of the two memory test unit groups is within the preset time range, if the difference between the test times of the two memory test unit groups is not within the preset time range.

In another embodiment, the matching module 1103 is configured to divide the plurality of memory test units into a plurality of memory test unit groups based on the number of cores; calculating the average test time value of the memory test unit groups and the test time of the plurality of memory test unit groups according to the test time of each core to each memory test unit; and if the difference value between the testing time of each memory testing unit group and the testing time average value of the memory testing unit groups is within the preset time range, matching the memory testing unit groups with the cores, wherein the memory testing units in one memory testing unit group belong to the same memory particle, and one memory testing unit group corresponds to one core.

In an embodiment, the matching module 1103 is further configured to, if there is a difference between the test time of one memory test unit group and the test time average of the memory test unit groups that is not within the preset time range, sort the memory test unit groups according to a preset order, and determine a first memory test unit group corresponding to the maximum test time value and a second memory test unit group corresponding to the minimum test time value; and exchanging at least one memory test unit in the first memory test unit group and the second memory test unit group until the difference value between the test time of the exchanged memory test unit group and the test time average value of the memory test units is within a preset time range.

It should be noted that the test time of the memory test unit group is the sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is the average value of the test times of the memory test units in the memory test unit group.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

The memory test device provided by the embodiment of the disclosure obtains a plurality of intersection-free memory test units; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and the running time of the cores is close to that of the memory test unit groups bound for each core; the memory test units in each memory test unit group do not have intersection, so that a plurality of memory test units are prevented from being tested by one kernel, the test time is shortened, the physical addresses of the memory test unit groups are independent and not influenced mutually, the binding of the memory to the kernel is realized, the test equipment does not need an operating system, thread switching is not needed, and the memory test efficiency is greatly improved.

The test apparatus 1200 according to this embodiment of the present invention is described below with reference to fig. 12. The test apparatus 1200 shown in fig. 12 is only an example, and should not bring any limitation to the function and the scope of use of the embodiment of the present invention.

As shown in fig. 12, the test device 1200 is in the form of a general purpose computing device. The components of the test apparatus 1200 may include, but are not limited to: the at least one processing unit 1210, the at least one memory unit 1220, and a bus 1230 connecting various system components including the memory unit 1220 and the processing unit 1210.

Wherein the memory unit stores program code that is executable by the processing unit 1210 such that the processing unit 1210 performs steps according to various exemplary embodiments of the present invention as described in the above section "exemplary methods" of the present specification. For example, the processing unit 1210 may execute the method of obtaining a plurality of non-intersecting memory test units as shown in fig. 7; testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit; and matching the memory test unit groups for the cores according to the test time of each core to each memory test unit so as to test the memory based on the matching relationship between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

The storage unit 1220 may include a readable medium in the form of a volatile memory unit, such as a random access memory unit (RAM) 12201 and/or a cache memory unit 12202, and may further include a read only memory unit (ROM) 12203.

Storage unit 1220 may also include a program/utility 12204 having a set (at least one) of program modules 12205, such program modules 12205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

The bus 1230 may be any bus representing one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The testing device 1200 may also communicate with one or more external devices 1240 (e.g., keyboard, pointing device, bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with the system 1200, and/or may communicate with any device (e.g., router, modem, etc.) that enables the testing device 1200 to communicate with one or more other computing devices. Such communication may occur over input/output (I/O) interfaces 1250. Further, the system may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via network adapter 1260. As shown in FIG. 12, the network adapter 1260 communicates with the other modules of the test equipment 1200 via the bus 1230. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the test device 1200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, to name a few.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium, which may be a readable signal medium or a readable storage medium. Fig. 13 shows a schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure, and as shown in fig. 13, the computer-readable storage medium 1300 has a program product stored thereon, which is capable of implementing the above-mentioned method of the present disclosure. In some possible embodiments, the various aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a user equipment to carry out the steps according to various exemplary embodiments of the invention described in the above section "exemplary methods" of this specification, when said program product is run on said user equipment.

The program product for implementing the above method according to an embodiment of the present invention may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a user device, such as a personal computer. However, the program product of the present invention is not limited in this respect, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A memory test method, comprising:

acquiring a plurality of non-intersection memory test units;

testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit;

and matching the memory test unit groups for the cores according to the test time of each core to each memory test unit, so as to test the memory based on the matching relation between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

2. The method according to claim 1, wherein the testing the memory based on the matching relationship between the kernel and the memory test unit group comprises:

determining a target thread corresponding to the kernel according to a preset kernel thread binding relationship;

and binding the target thread with the kernel, binding the target thread with the memory test unit group corresponding to the kernel until the kernel is bound with the memory test unit group, and starting the test.

3. The method of claim 2, wherein the binding the target thread to the set of memory test units corresponding to the one core comprises:

acquiring test parameters of a memory test unit group corresponding to the core;

and inputting the test parameters into the target thread to bind the memory test unit group with the target thread.

4. The method according to claim 2, wherein before said determining a target thread corresponding to said one kernel according to a preset kernel thread binding relationship, said method further comprises:

and according to a preset binding rule, constructing a kernel thread binding relationship between kernels and threads.

5. The method of claim 2, wherein said binding said target thread to said one kernel comprises:

binding the target thread with the one kernel based on a unified extensible firmware interface.

6. The method of claim 1, wherein obtaining the plurality of non-intersecting memory test cells comprises:

determining the number of the memory test units according to the number of the memory particles and the number of the CPU cores;

and dividing the memory into a plurality of non-intersection memory test units according to the number of the memory test units, wherein the capacity of each memory test unit is the same.

7. The method of claim 1, wherein the testing each memory test unit by using a plurality of cores to obtain the test time of each core to each memory test unit comprises:

and storing the test time of each kernel to each memory test unit in a test time matrix table.

8. The method according to claim 1, wherein the matching a group of memory test units for each core according to the test time of each core to each memory test unit comprises:

dividing the plurality of memory test units into a plurality of memory test unit groups based on the number of the cores;

calculating the test time of the plurality of memory test unit groups according to the test time of each kernel to each memory test unit;

and if the difference value between the test time of any two memory test units is within a preset time range, matching the plurality of memory test unit groups with the plurality of cores, wherein the memory test units in one memory test unit group belong to the same memory grain, and one memory test unit group corresponds to one core.

9. The method of claim 8, further comprising:

if the difference value between the testing time of the two memory testing unit groups is not in the preset time range, adjusting part of the memory testing units in the two memory testing unit groups until the difference value between the testing time of the two memory testing unit groups is in the preset time range.

10. The method according to claim 1, wherein the matching a memory test unit group for each core according to the test time of each core to each memory test unit comprises:

calculating the average test time value of the memory test unit groups and the test time of the plurality of memory test unit groups according to the test time of each core to each memory test unit;

and if the difference value between the testing time of each memory testing unit group and the testing time average value of the memory testing unit groups is within the preset time range, matching the plurality of memory testing unit groups with the plurality of cores, wherein the memory testing units in one memory testing unit group belong to the same memory grain, and one memory testing unit group corresponds to one core.

11. The method of claim 10, further comprising:

if the difference value between the testing time of one memory testing unit group and the testing time average value of the memory testing unit groups is not within the preset time range, sequencing the memory testing unit groups according to a preset sequence, and determining a first memory testing unit group corresponding to the maximum testing time and a second memory testing unit group corresponding to the minimum testing time;

and exchanging at least one memory test unit in the first memory test unit group and the second memory test unit group until the difference value between the test time of the exchanged memory test unit group and the test time average value of the memory test units is within the preset time range.

12. The method according to claim 1, wherein the test time of the memory test unit group is a sum of the test times of the memory test units in the memory test unit group, or the test time of the memory test unit group is an average of the test times of the memory test units in the memory test unit group.

13. A memory test device, comprising:

the acquisition module is used for acquiring a plurality of memory test units without intersection;

the time consuming module is used for testing each memory test unit by using a plurality of kernels to obtain the test time of each kernel to each memory test unit;

and the matching module is used for matching the memory test unit groups for the cores according to the test time of each core on each memory test unit, and testing the memory based on the matching relation between the cores and the memory test unit groups, wherein the difference value of the test time of the memory test unit groups corresponding to any two cores is within a preset time range, and any two memory test unit groups have no intersection.

14. A test apparatus comprising a processor and a memory, the memory for storing executable instructions for the processor; wherein the processor is configured to perform the memory test method of any one of claims 1-12 via execution of the executable instructions.

15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the memory testing method according to any one of claims 1 to 12.