CN115980554B

CN115980554B - Chip testing method and electronic equipment thereof

Info

Publication number: CN115980554B
Application number: CN202310132853.XA
Authority: CN
Inventors: 何雨阳; 郭长江; 周强; 汪晓晖; 顾问; 郭宁宁; 孙见; 曹葵康; 刘军传; 徐一华
Original assignee: Tztek Technology Co Ltd
Current assignee: Suzhou Tianzhun Xingzhi Technology Co ltd
Priority date: 2023-02-17
Filing date: 2023-02-17
Publication date: 2024-02-09
Anticipated expiration: 2043-02-17
Also published as: CN115980554A

Abstract

The invention provides a chip testing method and electronic equipment thereof, wherein the method comprises the following steps: responding to a test request instruction, searching a target tool of an interface to be tested of a chip to be tested, wherein the test request instruction carries information of the interface to be tested of the chip to be tested; testing the interface to be tested based on the target tool; responding to the test result display request, and displaying the test result; and confirming that the test is successful according to the test result. The interface test is carried out by aiming at the target tool of the interface to be tested of the chip, and the test result is displayed in time, so that the time and labor cost for debugging the chip are reduced, and the application and popularization of the chip are promoted.

Description

Chip testing method and electronic equipment thereof

Technical Field

The invention relates to the field of intelligent driving, in particular to a chip testing method and electronic equipment thereof.

Background

With the development of the intelligent driving industry, people have higher requirements on intelligent driving technology. The intelligent driving function automobile is a large adult of tens of highly complex systems, and the most advanced technology is integrated into electronic hardware, sensors, software and the like to meet the intelligent driving requirements of people.

Currently, in order to meet various intelligent driving demands, hardware cooperation, such as some intelligent driving chips, is required in addition to software support. Most of the current intelligent driving chips are researched by chip manufacturers, and in the process that the chips are combined with other chips, software and various interfaces from the chip manufacturers to the intelligent automobile manufacturers to realize the intelligent driving function, the chip marketing test is realized manually by technicians, so that the efficiency is low and the labor cost is increased. Therefore, in order to accelerate the application of the chip in the intelligent driving field to the ground, a set of feasible automatic chip testing schemes are to be proposed.

Disclosure of Invention

In view of the above, the present invention is directed to a new chip testing method and an electronic device thereof.

In order to solve the technical problems, the invention adopts the following technical scheme:

in a first aspect, a chip testing method according to an embodiment of the present invention includes:

responding to a test request instruction, searching a target tool of an interface to be tested of a chip to be tested, wherein the chip to be tested is a vehicle-mounted chip, and the test request instruction carries information of the interface to be tested of the chip to be tested;

Testing the interface to be tested based on the target tool;

responding to the test result display request, and displaying the test result;

and confirming that the test is successful according to the test result.

Further, the method further comprises:

acquiring interface information of the chip to be tested;

interface function information corresponding to the interface information is determined according to the interface information;

a target toolset of the interface is generated based on the interface function information.

Further, the responding to the test request instruction, searching the target tool of the interface to be tested of the chip to be tested includes:

acquiring test request information according to the test request instruction, wherein the test request information carries the interface information to be tested and interface function information to be tested of the interface to be tested;

searching a target tool set of the interface to be tested according to the interface information to be tested;

searching a target tool subset in the target tool set of the interface to be tested according to the interface function information to be tested of the interface to be tested;

and taking the target tools in the target tool subset as target tools of the interface to be tested of the chip to be tested.

Further, the testing the interface to be tested based on the target tool includes:

Obtaining test sample data of the interface to be tested;

inputting the test sample data as parameters into the target tool subset for operation to obtain an operation result;

and taking the operation result as a test result.

when the interface to be tested is a universal asynchronous receiver/transmitter (UART) interface, acquiring the test request instruction, wherein the interface information to be tested carried by the test request instruction comprises serial number information, baud rate information, check bit information, data bit information, stop bit information and control flow information;

determining interface function information to be tested corresponding to the interface information to be tested based on the interface information to be tested, wherein the interface function information to be tested comprises data sending and receiving according to parameter requirements of the interface information to be tested;

and searching the target tool subset corresponding to the interface function information to be tested according to the interface function information to be tested, wherein the target tool subset comprises a serial interrupt receiving function and a serial sending function.

Further, the method further comprises:

Acquiring port information of the UART interface through a preset path;

judging whether a driver corresponding to the port needs to be downloaded and installed according to the port information;

if yes, downloading and installing the driver.

when the interface to be tested is a CAN/CANFD/LIN interface, acquiring the test request instruction, wherein the interface information to be tested carried by the test request instruction comprises first pin information to be tested and second pin information to be tested;

determining interface function information to be tested corresponding to the interface information to be tested based on the interface information to be tested, wherein the interface function information to be tested comprises data transmission and data reception by a channel established by the first pin information to be tested and the second pin information to be tested;

and searching the target tool subset corresponding to the interface function information to be tested according to the interface function information to be tested, wherein the target tool subset comprises a CAN/CANFD/LIN receiving function and a CAN/CANFD/LIN transmitting function.

Further, the method further comprises:

When the interface to be tested is an Ethernet interface, logging in a target chip;

acquiring communication information of the chip to be tested and the target chip according to the IP address information of the chip to be tested;

and confirming that the test is successful according to the communication information.

Further, the login target chip includes:

setting the address of the target chip as a target network segment address;

setting the network segment of the chip to be tested as the target network segment;

logging in the target chip through a remote connection tool SSH.

In a second aspect, an electronic device according to an embodiment of the present invention includes: a processor; and a memory in which computer program instructions are stored, wherein the computer program instructions, when executed by the processor, cause the processor to perform the method as described above.

According to the chip testing method, the interface is tested by aiming at the target tool of the interface to be tested of the vehicle-mounted chip, and the test result is displayed in time, so that the time and labor cost of chip debugging are reduced, and the chip application and popularization are promoted.

Drawings

FIG. 1 is a schematic diagram of an implementation environment of a chip testing method according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart of a chip testing method according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method for generating a target tool in a chip test method according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method for searching a target tool in a chip test method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a relationship between a chip and a target tool in a chip testing method according to an embodiment of the present invention;

FIG. 6 is a flow chart of a method for testing based on a target tool in a chip testing method according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating another method for searching for a target tool in the chip test method according to the embodiment of the present invention;

FIG. 8 is a flowchart illustrating a method for installing a driver in a chip test method according to an embodiment of the present invention;

FIG. 9 is a flowchart illustrating another method for searching for a target tool in the chip test method according to the embodiment of the present invention;

fig. 10 is a flow chart of a testing method of an ethernet interface in a chip testing method according to an embodiment of the present invention;

FIG. 11 is a flowchart of a target chip login method in a chip test method according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a chip test apparatus according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the detailed description and specific examples, while indicating the embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. The technical scheme of the embodiment of the invention obtains, stores, uses, processes and the like the data, and accords with the relevant regulations of national laws and regulations.

Referring to fig. 1 of the specification, a schematic diagram of an implementation environment of a chip testing method according to an embodiment of the invention is shown. It should be noted that fig. 1 is only an example of an implementation environment in which an embodiment of the present invention may be applied to help those skilled in the art understand the technical content of the present invention, and does not mean that the embodiment of the present invention may not be used in other devices, systems, environments, or scenes. As shown in fig. 1, the implementation environment may at least include a chip test terminal 110, a chip terminal 120, and a domain controller 130, where the chip test terminal 110 and the chip terminal 120 may be directly or indirectly connected through a wired or wireless communication manner, which is not limited in the embodiment of the present invention.

The chip testing terminal 110 may include, but is not limited to, smart phones, tablet computers, notebook computers, desktop computers, vehicle terminals, servers, etc., and may also include software running in the physical devices, such as application programs, etc. The operating system running on the chip test terminal 110 may include, but is not limited to, an android system, an iOS system, a linux system, a windows system, etc.

In the embodiment of the present invention, some communication or transmission interfaces and/or software may be provided in the chip test terminal 110 for communication connection with the chip terminal 120, so as to control the chip terminal 120. The chip side 120 may be one or more chips. Fig. 1 illustratively places the chip side 120 in the domain controller 130. When the domain is controlled to be a domain controller in the intelligent driving domain, the chip testing end 110 can realize automatic control on the chip end 120 arranged in the domain controller, so that assistance is provided for floor application and popularization of the intelligent driving technology.

It should be noted that fig. 1 is only an example. It will be appreciated by those skilled in the art that, although fig. 1 only shows the chip end 120 disposed in the domain controller 130, the embodiment of the present invention is not limited thereto, and the chip end 120 may be embedded in other terminals having similar requirements for chip computing power, interfaces, etc. in the intelligent driving field according to actual needs.

The chip testing method is mainly applied to the aspect of controlling the chip in the intelligent driving field, and can be particularly applied to the chip testing end 110. As shown in fig. 2, an embodiment of the present invention further provides a chip testing method, including:

step 201: responding to a test request instruction, searching a target tool of an interface to be tested of a chip to be tested, wherein the chip to be tested is a vehicle-mounted chip, and the test request instruction carries information of the interface to be tested of the chip to be tested.

In the embodiments of the present description, interface testing is mainly used to detect interaction points between external systems and between internal subsystems. The key point of the test is to check the exchange of data, the transfer and control management process, and the mutual logic dependency between systems.

Before executing step 201, the chip testing terminal 110 needs to obtain the interface information of the chip to be tested, and then connect the chip to be tested according to the interface information of the chip to be tested, where the connection may be wired or wireless connection. For example, if the interface information of the chip to be tested is an RS232 serial port, the chip testing terminal 110 is also in communication connection with the chip to be tested through a corresponding serial port. The serial ports of the RS232 serial port and the chip test end can be physical ports or logical ports.

The target tool in the present specification is a tool for testing whether the interface to be tested can normally communicate or complete the corresponding function, and specifically, the tool may be a preset function, preset software or a preset application. The interface to be tested may be one or more interfaces to be tested of the chip to be tested.

The test request instruction can be triggered by a control in an interface of the chip test end, or can be automatically triggered after the chip to be tested is successfully connected with the chip test end.

The chip testing method mainly aims at a vehicle-standard chip, wherein the vehicle-standard chip is a chip applied to an automobile, and different from consumer products and industrial products, the chip has higher requirements on reliability, such as a working temperature range, working stability, reject ratio and the like. The vehicle-mounted chip is integrated with different interfaces, so that the different interfaces need to be tested.

Step 202: and testing the interface to be tested based on the target tool.

In one embodiment, the target tool performs the test on the interface to be tested, which is to simulate the target tool according to the use mode or the use function of the interface to be tested, so as to confirm whether the interface to be tested of the chip to be tested is connected, communicated and used normally.

Step 203: and responding to the test result display request, and displaying the test result.

The display in the step can be the interface display of the chip testing end directly or the display of the chip testing end through a third-party interface, for example, the display of the chip testing end through serial port debugging assistant software.

The test results comprise an interface initialization success result, an interface sample data transmission success, an interface loop communication test success result and the like

Step 204: and confirming that the test is successful according to the test result.

Correspondingly, the success of the test is confirmed according to the test results such as the successful result of the interface initialization, the successful transmission of the interface sample data, the successful result of the interface loop communication test and the like. For unsuccessful cases, steps 202-202 are repeated until the test is confirmed to be successful, by modifying debug parameters or debugging.

The test result can help the user to intuitively find the connection, communication and use conditions of the chip interface, and if the problem is found, the chip interface can be timely adjusted and debugged so that the chip can be normally used.

In one embodiment, as shown in fig. 3, the method further comprises:

step 301: and acquiring interface information of the chip to be tested.

In practical applications, a chip to be tested may have different kinds of interfaces, so that the interface information may include kinds of information of the interfaces, such as UART interfaces, CAN bus interfaces, SGMII interfaces, and the like.

Step 302: and determining interface function information corresponding to the interface information according to the interface information.

Different kinds of interfaces of the chip to be tested have different functions. Illustratively, the UART interface, UART, is a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter). The functions of UART illustratively include: 1. converting parallel data transmitted from the computer into an output serial data stream; 2. converting serial data from outside the computer into bytes for devices using parallel data inside the computer; 3. adding parity bits to the output serial data stream and performing parity checking on the data stream received from the outside; 4. adding a start-stop mark into the output data stream, deleting the start-stop mark from the received data stream, and processing an interrupt signal sent by a keyboard or a mouse (the keyboard and the mouse are serial devices); 5. processing the synchronous management problem of the computer and the external serial equipment; 6. parallel data is adopted in the computer, the data cannot be directly sent to the Modem, and asynchronous transmission can be performed only after UART arrangement.

Step 303: a target toolset of the interface is generated based on the interface function information.

Wherein the target tool set may include one or more target tools. The interfaces and interface functions may be in a one-to-one or one-to-many relationship. The interface functions and the target tool set may be in a one-to-one mapping relationship or in a one-to-many relationship. In embodiments of the present description, different functions of the interface need to be tested by the corresponding target tool set. Illustratively, the interface has a transmission function, and accordingly, the target tool set may include a reception function test tool and a transmission function test tool.

Through steps 301-303, a target tool set of the interface is generated, so that when the interface to be tested of the chip to be tested needs to be tested, a corresponding target tool can be found in the database through interface information of the interface to be tested. In general, the target tool set is designed in advance according to the test requirement of the interface of the existing chip, or can be updated according to the test result after the test result is output, or can be regenerated when a new interface and interface function exist.

In one embodiment, as shown in fig. 4, in response to the test request instruction in step 201, searching the target tool of the interface to be tested of the chip to be tested includes:

Step 401: and acquiring test request information according to the test request instruction, wherein the test request information carries the interface information to be tested and the interface function information to be tested of the interface to be tested.

In some embodiments, there may be one or more interfaces in the same interface, so that all interfaces of the chip to be tested need to be distinguished, so that the interface information to be tested may include identification information of the interface to be tested, and the interface to be tested may be uniquely determined based on the identification information.

Step 402: and searching a target tool set of the interface to be tested according to the interface information to be tested.

The interface to be tested can be positioned to the target tool set of the interface to be tested, and the interface to be tested and the target tool set of the interface to be tested have a one-to-one mapping relation.

Step 403: and searching a target tool subset in the target tool set of the interface to be tested according to the interface function information to be tested of the interface to be tested.

The target tool set of the interface to be tested comprises target tool subsets with different functions, so that the corresponding target tool subsets can be found according to the functional information of the interface to be tested.

Step 404: and taking the target tools in the target tool subset as target tools of the interface to be tested of the chip to be tested.

Illustratively, as shown in fig. 5, the chip includes a plurality of interfaces, each interface corresponding to a plurality of interface functions, each interface function corresponding to a plurality of target tools, the plurality of target tools of each interface function forming a target tool set, which may have a plurality of tool subsets. Specifically, the chip corresponds to the interface 1, 2, … …, m, the interface 1 corresponds to the interface function 1, 2, … …, n, and the interface function 1, 2, … …, n1 corresponds to the target toolset 1, 2, … …, n. The interface function 1 corresponds to the target tool set of the interface function 1, the target tool set of the interface function 1 comprises a target tool subset a and a target tool subset b, wherein the target tool subset a consists of target tools 1, 2, … … and a1, the target tool subset b consists of target tools 1, 2, … … and b1, and m, n, a1 and b1 are positive integers.

According to steps 401-404, positioning a target tool capable of testing the corresponding function of the interface according to the interface information and the corresponding function information of the chip to be tested, so that automatic testing of any function of any interface of the chip to be tested can be realized.

In one embodiment, as shown in fig. 6, the testing the interface to be tested based on the target tool in step 202 includes:

Step 601: and obtaining test sample data of the interface to be tested.

The test sample data may be data to be transmitted, or may be code or program to be executed. Further, the test sample data may be data suitable for the format of the interface transmission data, or may be executable code or program for testing the interface function in cooperation with the target tool. In practical application, the test sample data can be temporarily selected or generated according to the needs of a user, and can also be integrated into codes or programs for realizing automatic test.

Step 602: and inputting the test sample data as parameters into the target tool subset to run so as to obtain a running result.

This step is actually performed by inputting test sample data as parameters into the target tools in the target tool subset. The results of the operation are related to the test sample data and may characterize the successful transmission or execution of the test sample data by the target tool.

Step 603: and taking the operation result as a test result.

The target tool is a framework tool with universality or basicity for a certain function of the same interface, but may need specific data or code program matching when facing different application scenes or connection modes of specific interfaces. Therefore, in step 601-603, whether the test passes or not is judged based on the result of the cooperation operation of the test sample data and the target tool, so that the accuracy of the test result is further improved. In one embodiment, as shown in fig. 7, in response to the test request instruction in step 201, searching the target tool of the interface to be tested of the chip to be tested includes:

Step 701: when the interface to be tested is a universal asynchronous receiver/transmitter (UART) interface, the test request instruction is acquired, and the interface information to be tested carried by the test request instruction comprises serial number information, baud rate information, check bit information, data bit information, stop bit information and control flow information.

The information such as the serial number information, the baud rate information, the check bit information, the data bit information, the stop bit information, the control flow information and the like are all information for judging whether the UART interface can be normally used in the process of using the UART interface function. If the test is to test other interfaces, the test request instruction can also carry information for judging whether the test request instruction can be normally used in the process of using the functions of the other interfaces.

Step 702: and determining interface function information to be tested corresponding to the interface information to be tested based on the interface information to be tested, wherein the interface function information to be tested comprises data sending and receiving according to parameter requirements of the interface information to be tested.

The most common transmission function of UART interfaces is taken as an example here, and other interface information may be used to determine other functions of the interface.

Step 703: and searching the target tool subset corresponding to the interface function information to be tested according to the interface function information to be tested, wherein the target tool subset comprises a serial interrupt receiving function and a serial sending function.

For example, as shown in fig. 5, the interface 1 is a UART interface, the interface function 1 is a transmission function, and the target tool set has a target tool subset a, where the target tool subset is composed of a serial interrupt receiving function and a serial sending function.

In one embodiment, as shown in fig. 8, the method further comprises:

step 801: and acquiring port information of the UART interface through a preset path.

After the chip is in communication connection with the chip testing end, the chip testing end can find port information of the UART interface through a preset path. Taking a chip test terminal as a windows computer as an example, the preset path may be: control panel-hardware and sound-device manager-device and printer-device manager-ports (COM and LPT) through which port information of UART interfaces can be obtained.

Step 802: judging whether the corresponding driver of the port needs to be downloaded and installed according to the port information.

When the port information cannot be normally acquired or an abnormal mark (in practical application, an abnormal symbol or specific text, pattern, etc.) exists in the port information, it can be judged that the corresponding driver of the port is not installed or is installed by mistake, and the driver needs to be downloaded and installed again.

Step 803: if yes, downloading and installing the driver.

The UART interface can find an adaptive target tool to test by installing a driver.

In one embodiment, as shown in fig. 9, in response to the test request instruction in step 201, searching the target tool of the interface to be tested of the chip to be tested includes:

step 901: when the interface to be tested is a CAN/CANFD/LIN interface, the test request instruction is obtained, and the interface information to be tested carried by the test request instruction comprises first pin information to be tested and second pin information to be tested.

The controller area network bus (CAN, controller Area Network) is a serial communication protocol bus for real-time applications that CAN use twisted pair wires to transmit signals, one of the most widely used fieldbuses worldwide. The CAN protocol is used for communication between various components in an automobile to replace expensive and heavy wiring harnesses. The robustness of this protocol extends its use to other automation and industrial applications. The features of the CAN protocol include serial data communication for integrity, providing real-time support, transmission rates up to 1Mb/s, and 11-bit addressing and error detection capabilities.

The CANFD (CAN with Flexible Data rate) bus is an upgrade of the CAN bus, and the functions and characteristics thereof include: 1. the differential signal is used for transmission, so that excellent anti-noise performance is achieved; all nodes have no master-slave division, and when the bus is idle, any node can send a message to the bus; 2. a non-destructive bit arbitration mechanism, which uses an identifier ID in the information to determine the information transmission priority order, so as to ensure the integrity and timeliness of the transmitted data; the node on the CANFD bus inherited from the CAN bus has no concept of address, so that when the node is added on the bus, the software, hardware and application layers of the existing node on the bus are not affected; 3. the communication speed can be set according to the scale of the network and the function of the system, and in addition, the nodes on two buses with different communication speeds can realize information interaction through the gateway; 4. the fault-tolerant processing capability is provided, all nodes can detect errors, and the nodes detecting the errors immediately notify all other nodes on the bus; 5. if an error is detected, the node which is transmitting the message immediately stops the current transmission and continuously and repeatedly transmits the message until the message is successfully transmitted; 6. remote data request can be realized by sending a 'remote control frame' to request other units to send data.

The LIN bus is a low-cost serial communication network defined for an automobile distributed electronic system, is a supplement to other automobile multipath networks such as a Controller Area Network (CAN), and is suitable for application without excessively high requirements on the bandwidth, performance or fault tolerance function of the network. The LIN bus is based on SCI (UART) data format, employing a single master/multiple slave mode.

According to the function and characteristics of the bus interface, two pins are taken as examples to serve as interface information. The first pin information to be tested and the second pin information to be tested may include high-low level information (used for representing a connection mode of the pins), pin number information, master-slave information, transceiving information, and the like.

Step 902: and determining interface function information to be tested corresponding to the interface information to be tested based on the interface information to be tested, wherein the interface function information to be tested comprises data transmission and data reception by a channel established by the first pin information to be tested and the second pin information to be tested.

The connection mode of the pins can be determined based on the pin information of the bus interface, so that the data communication mode can be determined according to the connection mode, and further the function to be tested is determined. Illustratively, according to the information of the first pin to be tested and the information of the second pin to be tested, the CAN 2L is connected with the CAN 3H, the CAN H is connected with the CAN 3L, and then the communication function test is carried out by the channels established by the CAN2 and the CAN 3.

Step 903: and searching the target tool subset corresponding to the interface function information to be tested according to the interface function information to be tested, wherein the target tool subset comprises a CAN/CANFD/LIN receiving function and a CAN/CANFD/LIN transmitting function.

The communication function is generally transmission and reception, and here, only transmission and reception are taken as an example, and the aspects of the present specification are not limited thereto. In this embodiment, various buses are taken as examples, and different buses have different functions and characteristics, so that corresponding target tools are searched and matched according to the different functions and characteristics for testing.

In one embodiment, as shown in fig. 10, the method further comprises:

step 1001: and logging in a target chip when the interface to be tested is an Ethernet interface.

The target chip is another chip which is in communication connection with the chip testing end, and is preferably an AI chip. AI is an english abbreviation for artificial intelligence (Artificial Intelligence), AI chips are also known as AI accelerators or computing cards, i.e. modules dedicated to handling a large number of computing tasks in artificial intelligence applications. The chip testing method provided by the specification is preferably applied to the intelligent driving field, and in order to adapt and meet the requirements of the intelligent driving field on data processing, multiple interfaces and the like, a target chip is preferably a J5 series chip of a Bayesian framework BPU (Brain Processor Unit brain processor) and can be connected with more than 16 paths of high-definition video input; by relying on powerful heterogeneous computing resources, the method is not only suitable for acceleration of the most advanced image sensing algorithm, but also can support multi-sensor fusion of laser radar, millimeter wave radar and the like; and the prediction planning and the H.265/JPEG real-time encoding and decoding are supported, so that the high-level automatic driving requirement can be met.

When the interface to be tested is an Ethernet interface, the chip to be tested is connected and communicated with other chips through the Ethernet interface, and whether the communication function is normal or not is tested, so that whether the Ethernet interface can be normally used or not can be confirmed.

In the embodiment of the present disclosure, the chip to be tested is applied to the intelligent driving field, and no external network port is provided, so that the test of the ethernet interface needs to be performed by means of other AI chips with external network ports of the intelligent driving domain controller.

Step 1002: and acquiring communication information of the chip to be tested and the target chip according to the IP address information of the chip to be tested.

After logging in the target chip, connection with the chip to be tested can be tried on the target chip based on the IP address information of the chip to be tested.

Step 1003: and confirming that the test is successful according to the communication information.

Whether the interface can communicate normally can be known from whether the result of the attempted connection of the chip to be tested on the target chip is normal or not.

In one embodiment, as shown in fig. 11, the method for logging in the target chip in step 1001 includes:

step 1101: and setting the address of the target chip as a target network segment address.

In one embodiment, the address of the target chip is a pre-locked IP address. Preferably, the IP address is locked before the application product (in this application, the intelligent driving domain controller) to which the chip is integrated is marketed, reducing the user's trouble. Illustratively, the fixed IP address is 192.168.1.10.

Further, the network segment where the IP address is located is determined according to the fixed IP address, and the target network segment address is set to be between 192.168.1.0 and 192.168.1.255 (except 192.168.1.10). In practical application, the IP address information of the target chip is stored in a computer document, the document can be automatically searched through the catalog of the document by a computer program, and the IP address of the target chip is searched from the document.

Step 1102: and setting the network segment of the chip to be tested as the target network segment.

By configuring the chip to be tested and the target chip to be the same network segment, communication between the chips is facilitated. The step may be to directly set the gateway of the chip test terminal as the address in the target network segment, and then allocate the IP address of the chip to be tested as the address in the same network segment as the target chip. In practical application, the setting can be distributed under the target network segment through a random algorithm, or can be set according to a preset IP address distribution rule. The preset IP address allocation rule may be that an a network segment preset in the network segments of the chip test end allocates an address of a class a chip, and a B network segment allocates an address of a class B chip. The specific chip type is not limited, and may be differentiated according to different manufacturers, or may be differentiated according to the function of the chip.

Step 1103: and logging in a target network segment of the target chip through a remote connection tool SSH.

SSH (abbreviation for Secure Shell) is a network protocol used to encrypt communications between two computers and supports various authentication mechanisms. In practice, it is mainly used to secure telnet and telecommunications, and any network service can be encrypted with this protocol. Note that ssh is a protocol and in general we say software implementing such a protocol, such as the well known opensh.

The step is to try to connect the target chip at the chip test end, and as the chip test end and the target chip belong to the same network segment, generally, successful connection can be realized. Illustratively, the connection to the target chip in the domain controller may be achieved by a ping command.

Functional safety is one of the very critical elements in the development process of automobiles, and as the complexity of the system increases, the risk from system failure and random hardware failure increases. According to the safety technical measures recommended by the automobile functional safety standard ISO26262 on the diagnostic coverage rate of the processor unit, the chip testing method of the embodiment of the application preferably aims at Infineon Tricore series chips, such as core Chi E3 and Texas instrument TI397 series chips, and is provided with hardware redundancy technical measures of a dual-core lockstep (dual-core lockstep) processor structure, a self-checking function (BIST) of software and hardware, and a memory error correction checking technology (ECC, error correcting code) to ensure the safety characteristic of the processor. TriCore integrates a RISC processor core, a microcontroller, and a DSP in a single MCU. TriCore-based products are very widely used in automobiles, including internal combustion engine control, all-electric and hybrid vehicles, transmission control units, chassis areas, braking systems, electric steering systems, airbags, networking and advanced driving assistance systems, and have driven the development of automation, motorization and networking. The engineer can choose proper products according to the required memory, peripheral equipment, frequency, temperature and packaging, and all the products have high compatibility, so that high automatic intelligent requirements are provided for chip test.

Further, referring to fig. 12 of the specification, which illustrates a structure of a chip apparatus 1200 according to an embodiment of the present invention, the chip testing apparatus 1200 is disposed in a chip testing terminal, as shown in fig. 12, the chip testing apparatus 1200 may include:

the searching module 1201 is configured to respond to a test request instruction, and search a target tool of an interface to be tested of a chip to be tested, where the chip to be tested is a vehicle-mounted chip, and the test request instruction carries information of the interface to be tested of the chip to be tested;

a testing module 1202 for testing the interface to be tested based on the target tool;

a display module 1203, configured to display a test result in response to the test result display request;

and the confirming module 1204 is used for confirming that the test is successful according to the test result.

In one possible embodiment, the apparatus 1200 further comprises:

the acquisition module is used for acquiring interface information of the chip to be tested;

the determining module is used for determining interface function information corresponding to the interface information according to the interface information;

and the generating module is used for generating a target tool set of the interface based on the interface function information.

In one possible embodiment, the searching module 1201 is configured to obtain test request information according to the test request instruction, where the test request information carries the interface information to be tested and interface function information to be tested of the interface to be tested; the target tool set is used for searching the interface to be tested according to the interface information to be tested; and the target tool subset in the target tool set of the interface to be tested is searched according to the interface function information to be tested of the interface to be tested.

In one possible embodiment, the test module 1202 is configured to obtain test sample data of the interface to be tested; the test sample data are used as parameters to be input into the target tool subset for operation to obtain an operation result; and the operation result is used as a test result.

In a possible embodiment, the searching module 1201 may be configured to obtain the test request instruction when the interface to be tested is a UART interface for universal asynchronous receiving and transmitting, where the interface information to be tested carried by the test request instruction includes serial number information, baud rate information, check bit information, data bit information, stop bit information, and control flow information; the interface function information to be tested is used for determining interface function information to be tested corresponding to the interface information to be tested based on the interface information to be tested, and the interface function information to be tested comprises data sending and receiving according to parameter requirements of the interface information to be tested; and the target tool subset is also used for searching the target tool subset corresponding to the interface function information to be tested according to the interface function information to be tested, and the target tool subset comprises a serial interrupt receiving function and a serial sending function. Further, the searching module 1201 may be configured to obtain port information of the UART interface through a preset path; judging whether a driver corresponding to the port needs to be downloaded and installed according to the port information; and the device is also used for downloading and installing the driver if the driver needs to be downloaded and installed.

In a possible embodiment, the searching module 1201 may be configured to obtain the test request instruction when the interface to be tested is a CAN/CANCF/LIN interface, where the interface information to be tested carried by the test request instruction includes first pin information to be tested and second pin information to be tested; the interface function information to be tested is used for determining interface function information to be tested corresponding to the interface information to be tested based on the interface information to be tested, and the interface function information to be tested comprises data sending and receiving by a channel established by the first pin information to be tested and the second pin information to be tested; and the target tool subset is also used for searching the target tool subset corresponding to the interface function information to be tested according to the interface function information to be tested, and the target tool subset comprises a CAN/CANCF/LIN receiving function and a CAN/CANCF/LIN transmitting function.

In one possible embodiment, the apparatus 1200 further comprises:

the generating module is used for logging in a target chip when the interface to be tested is an Ethernet interface;

the generating module is used for acquiring communication information of the chip to be tested and the target chip according to the IP address information of the chip to be tested;

And the generating module is used for confirming that the test is successful according to the communication information.

In a possible embodiment, the generating module is further configured to set an address of the target chip as a target network segment address; the network segment is used for setting the network segment of the chip to be tested as the target network segment; and also for logging in the target chip via the remote connection tool SSH.

It should be noted that, in the apparatus provided in the foregoing embodiment, when implementing the functions thereof, only the division of the foregoing functional modules is used as an example, in practical application, the foregoing functional allocation may be implemented by different functional modules, that is, the internal structure of the device is divided into different functional modules, so as to implement all or part of the functions described above. In addition, the apparatus provided in the foregoing embodiments and the corresponding method embodiments belong to the same concept, and specific implementation processes of the apparatus and the corresponding method embodiments are detailed in the corresponding method embodiments, which are not repeated herein.

An embodiment of the present invention further provides an electronic device, where the electronic device includes a processor and a memory, where at least one instruction or at least one program is stored in the memory, where the at least one instruction or the at least one program is loaded and executed by the processor to implement a chip testing method as provided in the above method embodiment.

The memory may be used to store software programs and modules that the processor executes to perform various functional applications and data processing by executing the software programs and modules stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, application programs required for functions, and the like; the storage data area may store data created according to the use of the device, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory may also include a memory controller to provide access to the memory by the processor.

Referring to fig. 13 in conjunction with the description, a block diagram of an electronic device 1300 according to one embodiment of the invention is shown. The electronic device 1300 may include one or more processors 1302, system control logic 1308 coupled to at least one of the processors 1302, system memory 1304 coupled to the system control logic 1308, non-volatile memory (NVM) 1306 coupled to the system control logic 1308, and a network interface 1310 coupled to the system control logic 1308.

Processor 1302 may include one or more single-core or multi-core processors. Processor 1302 can include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). In embodiments herein, the processor 1302 may be configured to perform one or more embodiments in accordance with various embodiments as shown in fig. 2-4 and fig. 6-11.

In some embodiments, the system control logic 1308 may include any suitable interface controllers to provide for any suitable interface to at least one of the processors 1302 and/or any suitable devices or components in communication with the system control logic 1308.

In some embodiments, the system control logic 1308 may include one or more memory controllers to provide an interface to the system memory 1304. The system memory 1304 may be used for loading and storing data and/or instructions. The memory 1304 of the device 1300 may include any suitable volatile memory, such as suitable Dynamic Random Access Memory (DRAM), in some embodiments.

NVM/memory 1306 may include one or more tangible, non-transitory computer-readable media for storing data and/or instructions. In some embodiments, NVM/memory 1306 may include any suitable nonvolatile memory such as flash memory and/or any suitable nonvolatile storage device, such as at least one of a HDD (Hard Disk Drive), a CD (Compact Disc) Drive, a DVD (Digital Versatile Disc ) Drive.

NVM/memory 1306 may include a portion of a storage resource installed on an apparatus of device 1300, or it may be accessed by, but not necessarily a portion of, a device. For example, NVM/storage 1306 may be accessed over a network via network interface 1310.

In particular, system memory 1304 and NVM/storage 1306 may each include: a temporary copy and a permanent copy of instructions 1320. The instructions 1320 may include: instructions that when executed by at least one of the processors 1302 cause the apparatus 1300 to implement the chip test methods shown in fig. 2-4 and 6-11. In some embodiments, instructions 1320, hardware, firmware, and/or software components thereof may additionally/alternatively be disposed in the system control logic 1308, the network interface 1310, and/or the processor 1302.

The network interface 1310 may include a transceiver to provide a radio interface for the device 1300 to communicate with any other suitable device (e.g., front end module, antenna, etc.) over one or more networks. In some embodiments, the network interface 1310 may be integrated with other components of the device 1300. For example, the network interface 1310 may be integrated with at least one of the communication module of the processor 1302, the system memory 1304, the nvm/storage 1306, and a firmware device (not shown) having instructions which, when executed by at least one of the processor 1302, implement one or more of the various embodiments shown in fig. 2-4 and 6-11.

The network interface 1310 may further include any suitable hardware and/or firmware to provide a multiple-input multiple-output radio interface. For example, network interface 1310 may be a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem.

In one embodiment, at least one of the processors 1302 may be packaged together with logic for one or more controllers of the system control logic 1308 to form a System In Package (SiP). In one embodiment, at least one of the processors 1302 may be integrated on the same die with logic for one or more controllers of the system control logic 1308 to form a system-on-chip (SoC).

The apparatus 1300 may further include: input/output (I/O) devices 1313. The I/O device 1313 may include a user interface to enable a user to interact with the device 1300; the design of the peripheral component interface enables the peripheral components to also interact with the device 1300. In some embodiments, the device 1300 further includes a sensor for determining at least one of environmental conditions and location information associated with the device 1300.

In some embodiments, the user interface may include, but is not limited to, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., still image cameras and/or video cameras), a flashlight (e.g., light emitting diode flash), and a keyboard.

In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

In some embodiments, the sensors may include, but are not limited to, gyroscopic sensors, accelerometers, proximity sensors, ambient light sensors, and positioning units. The positioning unit may also be part of the network interface 1310 or interact with the network interface 1310 to communicate with components of a positioning network, such as Global Positioning System (GPS) satellites.

It should be understood that the illustrated structure of the embodiments of the present invention does not constitute a particular limitation of the electronic device 1300. In other embodiments of the invention, the electronic device 1300 may include more or less components than those illustrated, or may combine certain components, or split certain components, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

An embodiment of the present invention further provides a computer readable storage medium, where the computer readable storage medium may be configured in an electronic device to store at least one instruction or at least one program related to implementing a chip test method, where the at least one instruction or the at least one program is loaded and executed by the processor to implement the chip test method provided in the above method embodiment.

Alternatively, in an embodiment of the present invention, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

An embodiment of the invention also provides a computer program product comprising computer programs/instructions which, when run on an electronic device, are loaded and executed by a processor to implement the steps of the chip test method provided in the various alternative embodiments described above.

The following are to be described: the foregoing sequence of the embodiments of the present application is only for describing, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the apparatus embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The foregoing description of the preferred embodiments of the present application is not intended to limit the invention to the particular embodiments of the present application, but to limit the scope of the invention to the particular embodiments of the present application.

Claims

1. A method of chip testing, the method comprising:

responding to a test request instruction, searching a target tool of an interface to be tested of a chip to be tested, wherein the chip to be tested is a vehicle-mounted chip, and the test request instruction carries information of the interface to be tested of the chip to be tested, and specifically comprises the following steps:

Acquiring interface information of the chip to be tested;

generating a target tool set of the interface based on the interface function information;

taking the target tools in the target tool subset as target tools of the interface to be tested of the chip to be tested;

testing the interface to be tested based on the target tool to obtain a test result;

responding to a test result display request, and displaying the test result;

and confirming that the test is successful according to the test result.

2. The method of chip testing according to claim 1, wherein the testing the interface under test based on the target tool comprises:

Obtaining test sample data of the interface to be tested;

and taking the operation result as a test result.

3. The method of claim 1, wherein the searching for the target tool of the interface to be tested of the chip to be tested in response to the test request instruction comprises:

4. The method of chip testing of claim 3, wherein the method further comprises:

acquiring port information of the UART interface through a preset path;

if yes, downloading and installing the driver.

5. The method of claim 1, wherein the searching for the objective function tool of the interface to be tested of the chip to be tested in response to the test request instruction comprises:

6. The method of chip testing according to any one of claims 1-2, wherein the method further comprises:

7. The method of chip testing of claim 6, wherein the logging into the target chip comprises:

setting the address of the target chip as a target network segment address;

logging in the target chip through a remote connection tool SSH.

8. An electronic device, comprising: a processor; and a memory having stored therein computer program instructions, wherein the computer program instructions, when executed by the processor, cause the processor to perform the method of any of claims 1-7.