CN115952074B

CN115952074B - Performance verification method and device for system on chip

Info

Publication number: CN115952074B
Application number: CN202310248803.8A
Authority: CN
Inventors: 吴明剑; 何俊
Original assignee: Hanbo Semiconductor Shanghai Co ltd
Current assignee: Hanbo Semiconductor Shanghai Co ltd
Priority date: 2023-03-15
Filing date: 2023-03-15
Publication date: 2023-05-16
Anticipated expiration: 2043-03-15
Also published as: CN115952074A

Abstract

The invention provides a performance verification method and device of a system on a chip. Firstly, configuring and simulating a master device VIP verification parameter and a slave device DDR controller arbitration parameter according to performance verification scene definition; then monitoring the two data streams to obtain actual performance indexes; then, analyzing and judging whether the performance of the VIP of the main equipment meets the definition, if so, ending the execution method, otherwise, acquiring the back pressure information of the DDR controller of the slave equipment on the network on chip, and respectively acquiring the delay of the DDR controller of the slave equipment and the network on chip; and then judging whether the delay of the DDR controller of the slave device meets the preset or not, if so, adjusting the VIP verification parameter of the master device or the network-on-chip architecture and then executing the method, and if not, adjusting the arbitration parameter of the DDR controller of the slave device and then executing the method. The technical scheme of the invention enables the delay result to more truly reflect the busy and idle state of the back pressure system bus, and can rapidly locate the system performance bottleneck.

Description

Performance verification method and device for system on chip

Technical Field

The present invention relates to the field of chip verification technologies, and in particular, to a method and an apparatus for verifying performance of a system on a chip.

Background

With the development of semiconductor technology and technology, the SoC chip scale of the system on chip is larger and larger, and the inspection of the system performance is also becoming more and more important. In the development process of the system on chip, the overall performance of the chip needs to be evaluated to determine whether the configuration parameters of the bus architecture and the double data rate controller meet the system requirements. Accurate computation of latency can help quickly locate performance bottlenecks, particularly when multiple masters are present in a system-on-a-chip that simultaneously accesses multiple slaves.

The mainstream performance Verification method at present uses a Verification IP (VIP) component to measure and analyze the number of advanced commands (outlining), bandwidth (Bandwidth) and Latency (Latency) on the interface between the Verification IP and the system bus. However, when the system bus back-pressure verifies the IP, the delay calculation will not reflect the delay introduced by the back-pressure causing the verification IP to fail to command. In addition, when the system is large, the conventional delay calculation method cannot reflect whether the congestion is caused by the double data rate controller or the system bus architecture.

In view of the foregoing, there is a need for a method and apparatus for verifying system on chip performance, which can also account for delay in back pressure of a system on chip bus, so that the delay result is more realistic in back pressure of the busy state of the system bus, and can quickly locate whether the system performance bottleneck is in a network on chip or a double data rate controller.

Disclosure of Invention

In view of the above, the present invention provides a method and apparatus for verifying performance of a system on a chip, so as to solve the above technical problems in the prior art.

According to an aspect of the present invention, there is provided a performance verification method of a system on chip, wherein the performance verification method includes the steps of:

s1: configuring verification parameters of the master verification IP according to the definition of the performance verification scene;

s2: configuring arbitration parameters of the slave double data rate controller according to the definition of the performance verification scene, and starting simulation;

s3: the monitor monitors the data flows of the master device verification IP and the slave device double data rate controller, and obtains the actual performance indexes of the master device verification IP and the slave device double data rate controller;

s4: analyzing and judging whether the performance of the master equipment verification IP meets the performance verification scene definition according to the actual performance index, if so, ending the verification method, and if not, executing S5 and S6;

s5: acquiring back pressure information of the slave device double data rate controller to the network on chip, and respectively acquiring delay of the slave device double data rate controller and the network on chip;

s6: and judging whether the delay of the slave device double data rate controller meets a preset index, if so, returning to S1 and continuously executing S3 and S4 after adjusting the verification parameter or the network-on-chip architecture, and if not, returning to S2 and continuously executing S3 and S4 after adjusting the arbitration parameter.

According to another aspect of the present invention, there is provided a performance verification apparatus of a system on chip, wherein the performance verification apparatus includes:

the master device configuration module is configured to configure verification parameters of the master device verification IP according to the performance verification scene definition;

the slave device configuration module is configured to configure arbitration parameters of the slave device double data rate controller according to the performance verification scene definition, and start simulation;

the data monitoring module is configured to monitor the data flow of the master device verification IP and the slave device double data rate controller and obtain the actual performance indexes of the master device verification IP and the slave device double data rate controller;

the analysis judging module is configured to analyze and judge whether the performance of the main equipment verification IP meets the performance verification scene definition according to the actual performance index, if so, the performance verification device is finished, and if not, the back pressure acquisition module and the equipment adjustment module are executed;

the back pressure acquisition module is configured to acquire back pressure information of the slave device double data rate controller on the network on chip and respectively acquire delay of the slave device double data rate controller and the network on chip;

the device adjusting module is configured to judge whether the delay of the slave device double data rate controller meets a preset index, if yes, the device adjusting module returns to the master device configuration module and continues to execute the data monitoring module and the analysis judging module after adjusting the verification parameter or the network-on-chip architecture, and if not, the device adjusting module returns to the slave device configuration module and continues to execute the data monitoring module and the analysis judging module after adjusting the arbitration parameter.

According to still another aspect of the present invention, there is provided an electronic apparatus including: one or more processors and a memory, wherein the memory is to store executable instructions; the one or more processors are configured to implement the methods described above via executable instructions.

According to still another aspect of the present invention, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the above-described method.

From the above technical solution, the technical solution provided by the present invention has at least the following advantages:

in the performance verification environment, an advanced microcontroller bus architecture first-in first-out memory (AXI FIFO) is introduced to buffer enough commands to realize that the first-in first-out memory does not back pressure on the master device, so that the back pressure time of the network on chip to the first-in first-out memory also accounts for delay;

the delay introduced by the slave double data rate controller and the network-on-chip is calculated respectively, and the back pressure time of the slave double data rate controller to the network-on-chip is counted in the delay of the slave double data rate controller, so that the system performance bottleneck can be positioned quickly.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.

FIG. 1 shows a flow chart of a method provided by an exemplary embodiment of the present invention;

FIG. 2 illustrates an exemplary cumulative bandwidth scatter plot generated by a method provided by an exemplary embodiment of the present invention;

FIG. 3 illustrates an exemplary delay scattergram generated by a method provided by an exemplary embodiment of the present invention;

FIG. 4 illustrates a timing diagram of the computation of slave device double data rate controller delay and network-on-chip delay obtained by the method provided by an exemplary embodiment of the present invention;

FIG. 5 shows a block diagram of an apparatus provided by an exemplary embodiment of the present invention;

fig. 6 shows a block diagram of an electronic device provided by an exemplary embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative, and is not intended to be any limitation on the invention, its application or use. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the elements may be one or more. As used in this specification, the term "plurality/number" means two or more, and the term "based on" should be interpreted as "based at least in part on". Furthermore, the term "and/or" and "at least one of … …" encompasses any and all possible combinations of the listed items.

In addition, in this specification there are descriptions of "first," "second," "third," etc., which are for descriptive purposes only and are not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features indicated.

Referring to fig. 1, a flowchart of a method provided by an exemplary embodiment of the present invention is shown.

The invention provides a performance verification method of a System-on-a-Chip (SoC). Specifically, the performance verification method provided by the invention comprises the following steps:

s1: configuring Verification parameters of a master Verification IP (VIP) according to the definition of the performance Verification scene;

s2: configuring arbitration parameters of a slave Double Data Rate (DDR) controller according to a performance verification scene definition, and starting simulation;

The performance verification scene definition is derived by the chip architecture personnel according to the IP manual, the actually measured scene index parameters and in combination with the currently verified system on chip, and is used as a reference performance index of the system on chip in the current performance verification scene, wherein the reference performance index comprises, but is not limited to, a lead command number reference value, a bandwidth reference value and a delay reference value. The verification parameters include the number of advance commands, burst length, and quality of service, and the actual performance metrics include the number of advance commands (outlining), bandwidth (Bandwidth), and Latency (Latency).

In a preferred embodiment, the system on a chip includes at least one master authentication IP and slave double data rate controllers.

In a preferred embodiment, a master monitor is used to monitor the data flow of the master authentication IP in S3 and a slave double data rate controller monitor is used to monitor the data flow of the slave double data rate controller.

Specifically, the master monitor can record the timestamp, real-time bandwidth, number of leading commands, and delay information at the time each command of the master authentication IP was returned, and save the record in the form of text.

The real-time bandwidth, the number of advance commands and the delay information are calculated as follows, respectively.

(1) For real-time bandwidth, there are two calculation modes, one is cumulative bandwidth bw_accum, and the other is window bandwidth bw_win. Specifically, the accumulated bandwidth is calculated by: bw_accum=pkt_bw_accum/accum_actual_time, where pkt_bw_accum is the cumulative number of bytes monitored by the master monitor, and accum_actual_time is the time difference between the return time of the current command monitored by the master monitor and the issue time of the first command; the window bandwidth bw_win is calculated by: bw_win=pkt_bw_window/win_actual_time, where pkt_bw_window is the cumulative number of bytes in the set sliding time window, and win_actual_time is the time difference between the return time of the current command monitored by the host monitor and the issue time of the first command in the current window.

(2) For the number of advance commands, the calculation method is as follows: outlining=request_queue_size-resp_queue_size, i.e., the number of unreturned commands in the issued commands.

(3) For delay, the calculation is as follows: latency = rsp_end_time-cmd_start_time, where rsp_end_time is the command return time and cmd_start_time is the command issue time.

The slave double data rate controller monitor can record the timestamp, real-time bandwidth, number of advance commands and delay information of each command return on the Port (Port) of the double data rate controller, record the timestamp of each back pressure and release back pressure, and save the record in the form of text. The slave double data rate controller monitor bandwidth, number of advance commands and delay are calculated in a manner consistent with the master monitor. When the slave double data rate controller backs off the system bus on chip, the slave double data rate controller monitor will record the time stamp of each back-pressure signal pull-up and pull-down.

In a preferred embodiment, the analysis in S4 further includes extracting statistics of actual performance metrics (e.g., number of advance commands, bandwidth, latency) from the performance result text, thereby generating a visual map of all master performance metrics, i.e., bandwidth, latency visual maps of all master advanced microcontroller bus architecture interfaces, including bandwidth, latency statistics such as those shown in the following table, e.g., cumulative bandwidth scatter plot shown in fig. 2, and latency scatter plot such as that shown in fig. 3.

Device name	Cumulative bandwidth GBPS	Minimum window bandwidth GBPS	Maximum window bandwidth GBPS	Average window bandwidth GBPS	Minimum delay ns	Maximum delay ns	Average delay ns
								master-0_write	4.95	0.23	9.34	4.95	224	1175.99	596.03
master-0_read	1.1	0.02	2.3	1.1	102.67	278.67	148.54
								master-1_write	0.2	0.02	1.1	0.2	101	668	409.35
master-1_read	12.46	2.98	22.98	12.46	461.86	1279.66	836.5
								ddr0_port1_read	1.54	0.1	3.22	1.54	73.75	591.25	185.27
ddr0_port1_write	0.25	0	1.21	0.25	8.75	112.5	39.21
								ddr0_port12_read	0.31	0.03	1.45	0.31	102.5	447.5	206.96
ddr0_port2_write	0.95	0.17	2.97	0.95	158.75	241.25	163.06
								ddr0_port3_read	8.23	1.35	16.39	8.23	91.25	618.75	252.4
ddr0_port3_write	4.03	1.76	9.76	4.03	8.75	165	67.07

。

In a preferred embodiment, when the performance of the master device verification IP does not meet the performance verification scenario definition in S4 and the process proceeds to S5, the back pressure information of the slave device double data rate controller on the network on chip is further extracted, and the delays of the slave device double data rate controller and the network on chip are calculated, respectively.

Referring to fig. 4, a timing diagram of the computation of the slave double data rate controller delay and the network on chip delay obtained by the method provided by the exemplary embodiment of the present invention is shown. The calculation of the delay will be described below in connection with fig. 5 taking AXI interface delay calculation as an example.

t0: AXI commands are sent from the master device to verify IP;

t0 to t1: the slave device double data rate controller back-off the network on chip;

t1: relieving the back pressure;

t2: the AXI command arrives at the slave double data rate controller AXI interface;

t3: AXI commands arrive at the slave double data rate controller granule interface:

t4: the returned response reaches the AXI interface of the slave device double data rate controller;

t5: the response arrives at the AXI interface where the master verifies the IP.

From the above time information, the following results can be obtained:

the back-pressure time from the device double data rate controller to the network on chip is: tbp_slave=t1-t 0;

the delay of the slave double data rate controller is: tslave_latency=t4-t 2;

the command delay from the master to validate IP to the slave double data rate controller AXI interface is (deducting backpressure to effect): tcmd_latency=t2-t 1;

the delay from the device double data rate controller to the master device to verify the IP AXI interface Response is: tresp_latency=t5-t 4;

the command delay from the device double data rate controller to the device double data rate controller granule interface is: tmem_cmdlat=t3-t 2;

the delay to get the slave double data rate controller is then: tddr_latency=tbp_slave+tslave_latency, and the delay of the network on chip is: tnoc_latency=tcmd_latency+tresp_latency.

In a preferred embodiment, the system on chip further includes an advanced microcontroller bus architecture authentication IP (Advanced Microcontroller Bus Architecture Verification IP, AMBA VIP) and an advanced microcontroller bus architecture first in first out memory (Advanced Microcontroller Bus Architecture First In First Out, AMBA FIFO). Further, the internal logic of the master IP connected to the system-on-chip bus architecture is cleared (i.e., register-transfer Level (RTL) only retains the input-output interface signals, the master has no internal logic), and the advanced microcontroller bus architecture is used to verify IP to replace and mimic the behavior of the master IP. The advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA) includes, among other things, an advanced high-performance bus (Advanced High performance Bus, AHB), a peripheral bus (Advanced Peripheral Bus, APB), and a high-performance expansion bus (Advanced eXtensible Interface, AXI).

The operation and function of the validation IP for the advanced microcontroller bus architecture and the advanced microcontroller bus architecture fifo are described below, respectively.

Advanced microcontroller bus architecture verification IP is used to generate master device stimuli in various performance verification scenarios, which support sequential address and playback stimulus sequences. The continuous address excitation sequence refers to fixed burst length and advanced command number, and addresses are continuously accumulated; the playback of the excitation sequence refers to storing the AMBA excitation sequence generated in the simulation process into a file according to a required format in an IP verification environment, and playing back the excitation sequence in a system-on-chip performance verification environment so as to keep the excitation type, parameters and time intervals among the excitation completely consistent, thereby simulating the actual master device verification IP behavior.

The advanced microcontroller bus architecture FIFO is disposed between the host device authentication IP and the system-on-chip bus and is the maximum number of advance commands allowed by the advanced microcontroller bus architecture authentication IP. This arrangement allows the back pressure of the design under test (Design under test, DUT) not to be transferred to the advanced microcontroller bus architecture verification IP, so that enough advance commands can be issued and the back pressure time can be accounted for in the delay time. Specifically, after the system on chip to be tested starts to back-pressure the fifo of the high-level microcontroller bus architecture, the command in the fifo of the high-level microcontroller bus architecture cannot be sent to the system on chip bus, which results in the command staying in the fifo of the high-level microcontroller bus architecture. At the same time, since the master monitor is connected between the advanced microcontroller bus architecture authentication IP and the advanced microcontroller bus architecture fifo, the delay caused by the backpressure for commands that cannot be issued by this pen will be accounted for in the total delay. Further, since the depth of the fifo of the advanced microcontroller bus architecture is equal to the maximum running advance command number of the advanced microcontroller bus architecture verification IP, the situation that the advanced microcontroller bus architecture verification IP cannot issue commands due to back pressure does not occur.

The actual performance indicators are printed into the performance result text and analyzed by the performance automation analysis script. Specifically, the performance automation analysis script is used for extracting bandwidth and delay information recorded by the master device monitor and the slave device double data rate controller monitor, and carrying out statistical analysis on the bandwidth and delay results of all master device verification IPs in a specified time window, so as to calculate average bandwidth, minimum bandwidth, maximum bandwidth and delay.

The performance automation analysis script is also used for extracting backpressure information of the slave double data rate controller to the network on chip and calculating delays of the slave double data rate controller and the network on chip respectively. The delay of the slave double data rate controller includes the delay introduced by the slave double data rate controller back pressure, so the delay of the network on chip needs to be deducted from the delay introduced by the slave double data rate controller back pressure.

Referring to fig. 5, a block diagram of an apparatus according to an exemplary embodiment of the present invention is shown.

The invention also provides a performance verification device of the system-on-chip. Specifically, the performance verification device provided by the invention comprises the following modules:

It should be understood that the apparatus shown in fig. 5 may correspond to the method previously described in this specification. Thus, the operations, features and advantages described above with respect to the method are equally applicable to the apparatus provided by the present invention and the modules comprised thereof, and the operations, features and advantages described above with respect to the apparatus and the modules comprised thereof are equally applicable to the method provided by the present invention. For brevity, certain operations, features and advantages will not be described in detail.

Although specific functions are discussed above with reference to specific modules, it should be noted that the functions of each module in the present disclosure may also be implemented by dividing the functions into a plurality of modules, and/or at least some functions of the plurality of modules may be implemented by combining at least some functions of the plurality of modules into a single module. The manner in which a particular module performs an action in the present disclosure includes that the particular module itself performs the action, or that the particular module invokes or otherwise accesses the performed action (or performs the action in conjunction with the particular module). Thus, a particular module that performs an action may include that particular module itself that performs the action and/or another module that the particular module invokes or otherwise accesses that performs the action.

In addition, the method provided by the invention can be used for performance verification of the system-on-chip with the slave double data rate controller, and can also be used for performance verification of the system-on-chip with the random access memory (Random Access Memory, RAM) and the Flash memory (Flash) as the slave.

In addition to the technical scheme, the invention further provides electronic equipment, which comprises one or more processors and a memory for storing executable instructions. Wherein the one or more processors are configured to implement the above-described methods via executable instructions.

The invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the above method.

In the following part of the present description, illustrative examples of the aforementioned electronic device, non-transitory computer readable storage medium, and computer program product will be described in connection with fig. 6.

Fig. 6 shows an example configuration of an electronic device 300 that may be used to implement the methods described herein. The inventive aspects may also be implemented, in whole or in part, by electronic device 300, or similar devices or systems.

The electronic device 300 may be a variety of different types of devices. Examples of electronic device 300 include, but are not limited to: a desktop, server, notebook, or netbook computer, a mobile device (e.g., tablet, cellular, or other wireless telephone (e.g., smart phone), notepad computer, mobile station), a wearable device (e.g., glasses, watch), an entertainment appliance (e.g., an entertainment appliance, a set-top box communicatively coupled to a display device, a gaming machine), a television or other display device, an automotive computer, and so forth.

Electronic device 300 may include at least one processor 302, memory 304, communication interface(s) 309, display device 301, other input/output (I/O) devices 310, and one or more mass storage devices 303, capable of communicating with each other, such as through a system bus 311 or other suitable connection.

Processor 302 may be a single processing unit or multiple processing units, all of which may include a single or multiple computing units or multiple cores. Processor 302 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. The processor 302 may be configured to, among other capabilities, obtain and execute computer-readable instructions stored in the memory 304, mass storage device 303, or other computer-readable medium, such as program code of the operating system 305, program code of the application programs 306, program code of other programs 307, and so forth.

Memory 304 and mass storage device 303 are examples of computer-readable storage media for storing instructions that are executed by processor 302 to implement the various functions as previously described. For example, memory 304 may generally include both volatile memory and nonvolatile memory (e.g., RAM, ROM, etc.). In addition, mass storage device 303 may generally include hard disk drives, solid state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CD, DVD), storage arrays, network attached storage, storage area networks, and the like. Memory 304 and mass storage device 303 may both be referred to collectively as memory or a computer-readable storage medium in the present invention, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that may be executed by processor 302 as a particular machine configured to implement the operations and functions described in the examples of the present invention.

A number of programs may be stored on the mass storage device 303. These programs include an operating system 305, one or more application programs 306, other programs 307, and program data 308, and they may be loaded into memory 304 for execution. Examples of such application programs or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing the following components/functions: the methods provided by the present invention (including any suitable steps of the methods) and/or additional embodiments described herein.

Although illustrated in fig. 6 as being stored in memory 304 of electronic device 300,

modules

305, 306, 307, and 308, or portions thereof, may be implemented using any form of computer readable media accessible by electronic device 300. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.

Communication media includes, for example, computer readable instructions, data structures, program modules, or other data in a communication signal that is transferred from one system to another system. Communication media may include conductive transmission media such as electrical cables and wires, and wireless media such as acoustic, electromagnetic, RF, microwave, and infrared, capable of transmitting energy waves. Computer readable instructions, data structures, program modules, or other data may be embodied as a modulated data signal, such as in a wireless medium (e.g., carrier wave, or similar mechanism that is implemented as part of a spread spectrum technology, for example). The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. The modulation may be analog, digital or hybrid modulation techniques.

By way of example, computer-readable storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. For example, computer-readable storage media include, but are not limited to, volatile memory, such as random access memory (RAM, DRAM, SRAM); and non-volatile memories such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic/ferroelectric memories (MRAM, feRAM); and magnetic and optical storage devices (hard disk, tape, CD, DVD); or other known media or later developed computer-readable information/data that may be stored for use by a computer system.

One or more communication interfaces 309 are used to exchange data with other devices, such as via a network, direct connection, or the like. Such communication interfaces may be one or more of the following: any type of network interface (e.g., a Network Interface Card (NIC)), a wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, a worldwide interoperability for microwave access (Wi-MAX) interface, an ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a Near Field Communication (NFC) interface, etc. The communication interface 309 may facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the internet, etc. The communication interface 309 may also provide communication with external storage devices (not shown) such as in a storage array, network attached storage, storage area network, or the like.

In some examples, a display device 301, such as a monitor, may be included for displaying information and images to a user. Other I/O devices 310 may be devices that receive various inputs from a user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input/output devices, and so on.

The technical solutions described in the present invention may be supported by these various configurations of the electronic device 300, and are not limited to the specific examples of the technical solutions described in the present invention.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. A plurality of units or means recited in the apparatus claims can also be implemented by means of one unit or means in software or hardware.

Claims

1. A method for verifying performance of a system on a chip, wherein the system on a chip includes a master verification IP and a slave double data rate controller, and the master verification IP and the slave double data rate controller are at least one, the method for verifying performance includes the following steps:

s1: configuring verification parameters of the master device verification IP according to the performance verification scene definition;

s2: configuring arbitration parameters of the slave double data rate controller according to the performance verification scene definition, and starting simulation;

s6: judging whether the delay of the slave device double data rate controller meets a preset index, if so, returning to S1 and continuously executing S3 and S4 after adjusting the verification parameter or the network-on-chip architecture, and if not, returning to S2 and continuously executing S3 and S4 after adjusting the arbitration parameter;

the system on chip further comprises an advanced microcontroller bus architecture verification IP for simulating the behavior of a master IP and an advanced microcontroller bus architecture first-in first-out memory arranged between the master verification IP and a bus of the system on chip, wherein the internal logic of the master IP is emptied and the depth of the advanced microcontroller bus architecture first-in first-out memory is the maximum advanced command number allowed by the advanced microcontroller bus architecture verification IP.

2. The performance verification method according to claim 1, wherein the performance verification scenario definition is a reference performance index of the system on chip in a current performance verification scenario, the reference performance index including a lead command number reference value, a bandwidth reference value, and a delay reference value.

3. The performance verification method of claim 1, wherein the monitor comprises a master monitor and a slave double data rate controller monitor.

4. The performance verification method according to claim 1, wherein the verification parameters include a number of advance commands, a burst length, and a quality of service, and the actual performance index includes the number of advance commands, a bandwidth, and a delay.

5. The performance verification method of claim 4, wherein the actual performance metrics are printed into performance result text.

6. The performance verification method according to claim 5, wherein the analyzing in S4 further comprises extracting statistical information of the actual performance index from the performance result text, thereby generating a visual map of the actual performance index.

7. A performance verification apparatus for a system on a chip, wherein the system on a chip includes a master verification IP and a slave double data rate controller, and the master verification IP and the slave double data rate controller are at least one, the performance verification apparatus includes the following modules:

a master device configuration module configured to configure verification parameters of the master device verification IP according to a performance verification scenario definition;

a data monitoring module configured to monitor data flows of the master device authentication IP and the slave device double data rate controller, and obtain actual performance indexes of the master device authentication IP and the slave device double data rate controller;

the analysis judging module is configured to analyze and judge whether the performance of the master equipment verification IP meets the performance verification scene definition according to the actual performance index, if so, the performance verification device is finished, and if not, the back pressure acquisition module and the equipment adjustment module are executed;

the device adjusting module is configured to judge whether the delay of the slave device double data rate controller meets a preset index, if yes, the device adjusting module returns to the master device configuration module and continues to execute the data monitoring module and the analysis judging module after adjusting the verification parameter or the network-on-chip architecture, and if not, the device adjusting module returns to the slave device configuration module and continues to execute the data monitoring module and the analysis judging module after adjusting the arbitration parameter;

8. The performance verification device of claim 7, wherein the performance verification scenario definition is a reference performance index of the system on chip in a current performance verification scenario, the reference performance index including a lead command number reference value, a bandwidth reference value, and a latency reference value.

9. The performance verification apparatus of claim 7 wherein said monitor comprises a master device monitor and a slave device double data rate controller monitor.

10. The performance verification device of claim 7, wherein the verification parameters include a number of advance commands, a burst length, and a quality of service, and the actual performance metrics include a number of advance commands, a bandwidth, and a delay.

11. The performance verification device of claim 10, wherein the actual performance indicator is printed into performance result text.

12. The performance verification device of claim 11, wherein the analysis determination module is configured to further include extracting statistical information of the actual performance indicator from the performance result text, thereby generating a visual map of the actual performance indicator.

13. An electronic device, the electronic device comprising:

one or more processors;

a memory for storing executable instructions;

the one or more processors are configured to implement the method of any one of claims 1 to 6 via the executable instructions.

14. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the method of any of claims 1 to 6.