CN115946251A - Method and equipment for wire-electrode cutting silicon rod and silicon wafer - Google Patents
Method and equipment for wire-electrode cutting silicon rod and silicon wafer Download PDFInfo
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- CN115946251A CN115946251A CN202211601961.9A CN202211601961A CN115946251A CN 115946251 A CN115946251 A CN 115946251A CN 202211601961 A CN202211601961 A CN 202211601961A CN 115946251 A CN115946251 A CN 115946251A
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- 238000005520 cutting process Methods 0.000 title claims abstract description 211
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 86
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 86
- 239000010703 silicon Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 42
- 235000012431 wafers Nutrition 0.000 claims abstract description 54
- 238000005498 polishing Methods 0.000 claims description 42
- 239000002173 cutting fluid Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 description 23
- 230000008569 process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013598 vector Substances 0.000 description 4
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- 239000000969 carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Abstract
The embodiment of the invention discloses a method, equipment and a silicon wafer for wire-electrode cutting of silicon rods, wherein the method comprises the following steps: wire-cutting the first silicon rod using a first wire-cutting process parameter set to obtain a plurality of sample silicon wafers; obtaining the fluctuation angle of the linear cutting line mark on the sample silicon wafer; judging whether the linear cutting line mark has a tendency of offsetting from the efficient cutting surface to the inefficient cutting surface or not based on the fluctuating angle; based on the judgment result, adjusting one or more linear cutting process parameters in the first linear cutting process parameter group according to the size of the fluctuation angle to form a second linear cutting process parameter group; and performing linear cutting on a second silicon rod by adopting the second linear cutting process parameter group.
Description
Technical Field
The embodiment of the invention relates to the technical field of wafer processing, in particular to a method and equipment for wire-electrode cutting of a silicon rod and a silicon wafer.
Background
Silicon wafers are used as carriers in semiconductor circuit fabrication processes, and the quality of the silicon wafers has a decisive influence on the formation of integrated circuits. At present, the main processes in the primary forming process of the silicon wafer comprise: silicon rod cutting, physical and chemical grinding, chemical etching, physical and chemical polishing and the like. Silicon rod cutting is one of core processes in a silicon wafer forming process, and mainly comprises multi-line mortar (SiC) cutting and inner circle cutting. The mainstream technology adopted at present is multi-line cutting, because compared with inner circle cutting, the multi-line cutting has the advantages of high efficiency, good quality, high wafer yield and the like.
The principle of the multi-wire cutting is that cutting wires are sequentially wound in guide grooves formed on the circumferential surface of a spool at intervals so that the cutting wires form a cutting wire segment array, abrasive materials are brought into a processing area of a material to be cut (such as a silicon rod) to be ground by high-speed reciprocating motion of the cutting wires under the guiding action of the guide grooves, and the workpiece to be cut is vertically fed through the lifting of a worktable, so that the workpiece is simultaneously cut into a plurality of sheets (such as wafers) with required sizes and shapes.
Factors that affect the quality of wire cuts are numerous, including: the tension of the cutting wire, the lowering speed of the workpiece to be cut, the composition, viscosity and concentration of the abrasive, and the like. In the cutting process, in order to ensure the linear cutting quality, the linear cutting process parameters need to be adjusted according to specific operating conditions, and currently, in the field, the judgment of the quality of the linear cutting process parameters only takes the detection result of the surface damage depth of a workpiece as a basis, and does not consider the dynamic position change of a cutting line relative to a cut surface in the cutting process, so that the linear cutting process parameters are difficult to be properly controlled, and the linear cutting quality is unstable.
Disclosure of Invention
In view of the above, embodiments of the present invention are intended to provide a method, an apparatus, and a silicon wafer for wire-cutting a silicon rod; the linear cutting process parameters can be optimized according to the tendency that the linear cutting line marks deviate from the efficient cutting surface to the inefficient cutting surface, so that the cutting line marks are kept on the efficient cutting surface, and the linear cutting efficiency is improved while the linear cutting quality is ensured.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, embodiments of the present invention provide a method for wire cutting a silicon rod, the method including:
wire-cutting the first silicon rod using a first wire-cutting process parameter set to obtain a plurality of sample silicon wafers;
obtaining the undulation angle of the linear cutting line mark on the sample silicon wafer;
judging whether the linear cutting line mark has a tendency of offsetting from the efficient cutting surface to the inefficient cutting surface or not based on the fluctuating angle;
based on the judgment result, adjusting one or more linear cutting process parameters in the first linear cutting process parameter group according to the size of the fluctuation angle to form a second linear cutting process parameter group;
and performing linear cutting on a second silicon rod by adopting the second linear cutting process parameter group.
In a second aspect, embodiments of the present invention provide a wire cutting apparatus for performing the method according to the first aspect.
In a third aspect, embodiments of the present invention provide a silicon wafer made using the method according to the first aspect.
The embodiment of the invention provides a linear cutting method, which optimizes linear cutting process parameters based on the offset condition of cutting line marks, and comprises the steps of measuring the undulation angle of the linear cutting line marks on a sample silicon wafer, adjusting the linear cutting process parameters based on the obtained undulation angle, and applying the linear cutting process parameters to subsequent linear cutting operation.
Drawings
Fig. 1 is a schematic view of a conventional wire cutting apparatus.
Fig. 2 is a schematic view of another conventional wire cutting apparatus.
Fig. 3 is a flowchart of a conventional wire cutting method.
Fig. 4 is a microscopic image of the surface of a warp cut sample silicon wafer.
Fig. 5 is a flowchart of a method for wire cutting a silicon rod according to an embodiment of the present invention.
Fig. 6 is a schematic perspective view of the surface of a warp-cut sample silicon wafer.
FIG. 7 is a schematic representation of the crystal plane of a silicon wafer.
Fig. 8 is a schematic perspective view of the surface of a sample silicon wafer treated using the method provided by an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
Referring to fig. 1, which shows a schematic view of a conventional wire cutting apparatus 1, it is to be understood that the structure shown in fig. 1 is only for illustrative purposes and does not indicate that a person skilled in the art may add or subtract components to the composition structure shown in fig. 1 according to a specific implementation state, and the embodiment of the present invention is not limited thereto. As shown in fig. 1, the wire cutting apparatus 1 may include a wire cutting unit 11 and a carrying unit 12; the wire cutting unit 11 may be disposed vertically below the carrying unit 12 as shown in fig. 1 in some examples, and may be disposed vertically above the carrying unit 12 as shown in fig. 2 in some examples. Specifically, the wire cutting unit 11 may include a plurality of bobbins 111 and the cutting wire 112 wound on the bobbins 111 to form an array of cutting wire segments parallel to each other; in fig. 1, the number of the bobbins 111 is exemplified by 2, and the reciprocating direction of the bobbins 111 and the cutting wires 112 toward and away from the bearing unit 12 may be 10m/s to 15m/s as shown by the solid arrows in fig. 1, as an example. The carrying unit 12 is used for carrying and fixing the silicon rod 2 to be processed, and in the example shown in fig. 1 and 2, the carrying unit 12 may include a base 121 and an intermediate piece 122, and the intermediate piece 122 may fix the silicon rod 2 to be processed to the base 121, for example, the silicon rod to be processed may be fixed to the base by being bonded with resin to a lower surface (fig. 1) or an upper surface (fig. 2) of the base through a circumferential surface thereof.
With the wire cutting apparatus 1 shown in fig. 1 and 2, the cutting of the silicon rods 2 to be processed may be achieved by moving the wire cutting unit 11 or the carrier unit 12 such that the cutting wire 112 and the silicon rods 2 to be processed move in a vertical direction toward each other, and after the wire 112 to be cut and the silicon rods 2 to be processed contact each other, by the movement of the cutting wire 112 in the extending direction thereof. In the example shown in fig. 1, the wire cutting unit 11 may be moved in the direction indicated by a black arrow, and the carrier unit 12 may also be moved in the direction of a dotted white arrow, to achieve a relative movement between the cutting wire 112 and the silicon rod 2 to be processed in a vertical direction. In the example shown in fig. 2, the carrier unit 12 may be moved in the direction indicated by a black arrow, and the wire cutting unit 11 may also be moved in the direction of a dotted white arrow, to achieve a relative movement between the cutting wire 112 and the silicon rod 2 to be processed in the vertical direction. It should be noted that, in the embodiment of the present invention, the moving of the wire cutting unit 11 or the carrying unit 12 is realized by additionally installing a lifting device (not shown in the figure), and it can be understood that a person skilled in the art can also realize the moving of the wire cutting unit 11 or the carrying unit 12 in other ways according to actual needs and implementation scenarios, which is not described in detail in the embodiment of the present invention.
In the conventional scheme, a plurality of guide grooves for guiding the cutting wire 112 are provided on the bobbin 111, and the cutting wire 112 is sequentially wound in each guide groove of each bobbin 111 such that the cutting wire 112 is formed in an array consisting of a plurality of cutting wire segments in which the cutting wire segments are parallel to each other in order to cut the silicon rod into a plurality of silicon wafers at a time.
The surface of the silicon wafer obtained by wire cutting is not completely flat, but has surface damage caused by cutting wire marks, at present, an angle polishing method is generally adopted to detect the depth of the surface damage, and then the parameters of the wire cutting process are adjusted according to the detection result to ensure the wire cutting quality, wherein the angle polishing method refers to the following steps: the vertical mechanical damage layer is ground to throw a smooth inclined plane to realize the amplification of the mechanical damage layer so as to match the measurement precision of a microscope; after measurement using a microscope, the actual lesion depth is geometrically converted.
Specifically, referring to fig. 3, the conventional wire cutting method includes:
s101, bonding a silicon wafer sample obtained by wire cutting of a silicon rod on a table top inclined at a known angle;
s102, polishing a part of the surface of the silicon wafer sample into an inclined plane inclined at a known angle by using polishing equipment so as to expose the surface damage layer of the silicon wafer sample on the inclined plane;
s103, observing an interface or a boundary between the polished surface part and the unpolished surface part through a microscope, measuring the length of the damage on the inclined plane with the known angle according to the length of the damage at the boundary, and calculating the depth of the damaged layer according to the length and the sine value of the known angle;
and S104, judging whether the parameters of the linear cutting process are good or bad according to the obtained damage depth.
However, the depth of damage does not reflect the dynamic changes of the actual cut surface. The crystal structure of silicon is a diamond structure in which the density, hardness and wear resistance of the (111) crystal plane are highest, the grinding rate is lowest, but cleavage is easiest between two adjacent crystal planes; (110) The grinding rate of the crystal face is highest (namely, the crystal face is most easily damaged and easily ground); (001) The density of the crystal face is lowest, the hardness is low, and the strength is high, namely, for the cutting efficiency: (110) Crystal plane > (001) crystal plane > (111) crystal plane, therefore in the silicon wafer manufacturing industry, (110) crystal plane with better grinding performance is selected as the silicon wafer surface, namely as the standard cutting plane, and is also considered as the high-efficiency cutting plane, compared with the (001) crystal plane which is considered as the low-efficiency cutting plane. In practice, however, microscopic examination of the cut lines reveals that the actual cut surface will shift relative to the standard cut surface, i.e., the line cut lines will shift from the high efficiency cut surface to the low efficiency cut surface. Referring to fig. 4 showing a microscopic image of the surface of the sample wafer S that has been subjected to the wire cutting, it can be seen from fig. 4 that the cutting line traces have a periodically varying shape, which means that the wire cutting line traces are periodically shifted from the high-efficiency cutting plane to the low-efficiency cutting plane, and thus the difficulty of the cutting is periodically varied. In this case, in order to ensure cutting quality and cutting efficiency, it is necessary to keep the actual cut surface at the high-efficiency cut surface by adjusting the parameters of the wire cutting process, suppressing the deviation thereof toward the low-efficiency cut surface.
Based on the above, the embodiment of the invention provides a linear cutting method, linear cutting equipment and a silicon wafer; the linear cutting process parameters can be optimized according to the tendency that the linear cutting line marks deviate from the efficient cutting surface to the inefficient cutting surface, so that the cutting line marks are kept on the efficient cutting surface, and the linear cutting efficiency is improved while the linear cutting quality is ensured.
Referring to fig. 5, a method for wire cutting a silicon rod according to an embodiment of the present invention is shown, the method including:
s201, cutting a first silicon rod in a linear mode by adopting a first linear cutting process parameter set to obtain a plurality of sample silicon wafers;
s202, obtaining the undulation angle of the linear cutting line mark on the sample silicon wafer;
s203, judging whether the linear cutting line mark has a deviation trend from the efficient cutting surface to the inefficient cutting surface or not based on the undulation angle;
s204, based on the judgment result, adjusting one or more linear cutting process parameters in the first linear cutting process parameter group according to the size of the undulation angle to form a second linear cutting process parameter group;
and S205, cutting a second silicon rod by adopting the second wire-electrode cutting process parameter set.
The embodiment of the invention provides a linear cutting method, which optimizes linear cutting process parameters based on the offset condition of cutting line marks, and comprises the steps of measuring the undulation angle of the linear cutting line marks on a sample silicon wafer, adjusting the linear cutting process parameters based on the obtained undulation angle, and applying the linear cutting process parameters to subsequent linear cutting operation.
An example of the relief angle of the cut line score is shown in fig. 4, where the relief angle of the cut line score is 160 °, which means that the cut line score is offset 20 ° from the high efficiency cutting face to the low efficiency cutting face. In order to better determine the undulation angle of the line cutting line trace, which is the angle γ between the plane in which the adjacent female line trace NL and male line trace PL lie and the standard cutting plane SC, see fig. 6, according to a preferred embodiment of the present invention.
As shown in fig. 6, which shows a schematic perspective view of the surface of a warp-cut sample silicon wafer S, wherein the cutting line mark has a periodically undulating shape, a connecting line formed by the most convex portion of the cutting line mark along the direction perpendicular to the linear cutting direction X may be referred to as a positive line PL, a connecting line formed by the most concave portion of the cutting line mark along the direction perpendicular to the linear cutting direction X may be referred to as a negative line NL, the positive line PL and the negative line NL are alternately arranged, and the surface on which the adjacent positive line PL and the negative line NL are located is the actual cutting surface AC. As can be seen from fig. 6, the actual cut surface AC forms an angle γ with respect to the standard cut surface SC, and the angle γ is the undulation angle of the cut line mark.
In actual production, the cutting line mark is difficult to be always on the efficient cutting surface, but can be offset from the efficient cutting surface to a greater or lesser extent. For cost-effectiveness reasons, the undulation angle of the cutting line mark is allowed to fluctuate within a range, and it is judged that there is a tendency of deviation of the cutting line mark from the high-efficiency cutting surface to the low-efficiency cutting surface only when the undulation angle of the cutting line mark exceeds the range, for which it is preferably judged that there is a tendency of deviation of the cutting line mark from the high-efficiency cutting surface to the low-efficiency cutting surface when the obtained undulation angle is less than 160 °. Referring to FIG. 7, the (001), (111), and (110) crystal planes of a silicon wafer are shown. As shown in fig. 7, the coordinates of A, B, C, D at four points are set as: a (1,0,0); b (0,1,0); c (0,1,1); d (0,0,1), then vectors AB = (-1,1,0), BC = (0,0,1) are in the (110) plane, vectors AB = (-1,1,0), BC = (0, -1,1) are in the (111) plane. Assuming that n1= (x 1, y1, z 1) is the normal vector of the (110) crystal plane, then n1= (1,1,0) can be calculated from n1 being perpendicular to AB and perpendicular to BC; assuming that n2= (x 2, y2, z 2) is the normal vector of the (111) crystal plane, then from n2 being perpendicular to AB and perpendicular to BD, n2= (1,1,1) can be calculated, and then the angle between the (110) crystal plane and the (111) crystal plane is arccos < n1, n2> =54.7 ° ≈ 55 °. In addition, since the angle between the (110) plane and the (001) plane is 90 °, the angle between the (111) plane and the (001) plane is 90 ° =35 °.
Based on the above, it can be understood that when cutting along the (110) crystal plane, the line mark undulation angle is <180 ° -55 ° =125 °, and the actual cut surface will be transformed into the (111) crystal plane, which has the lowest grinding efficiency. Generally, the line mark undulation angle from 180 ° to 125 ° to 90 ° corresponds to the cutting efficiency from high to low to general process.
On the other hand, when the line mark angle is slightly shifted, the crystal plane is changed to a high-index crystal plane, and it is considered that the grinding efficiency does not greatly change. Therefore, it can be said that the grinding rate of the (110) crystal plane is when the line mark relief angle is between 180 ° and 153 °, and the grinding rate of the (111) crystal plane is when the line mark relief angle is between 153 ° and 125 °. Therefore, 153 ° may be used as a theoretical threshold. In combination with practical production experience, the threshold value can be set to be 160 degrees finally.
As can be seen from fig. 4 and 6, the greater the relief angle, the less the cutting line mark is displaced from the high-efficiency cutting surface to the low-efficiency cutting surface, so that when the relief angle is greater than a threshold value, it can be considered as a normal fluctuation of the cutting line that is allowed, and when the relief angle is less than the threshold value, it is necessary to optimize the line cutting parameters to ensure the line cutting quality and efficiency.
According to the method provided by the embodiment of the invention, once the trend that the linear cutting line mark deviates from the efficient cutting surface to the inefficient cutting surface is judged, the linear cutting process parameters can be adjusted to suppress the trend, and preferably, the linear cutting process parameter group at least comprises the following steps: tension of the cutting wire, feed speed of the silicon rod relative to the cutting wire, concentration of the cutting fluid.
In the actual cutting process, the three parameters of the tension of the cutting line, the feeding speed of the silicon rod relative to the cutting line and the concentration of the cutting liquid have strong coupling effect, so that a complex rule is presented between the linear cutting speed and the process condition. According to the method provided by the embodiment of the invention, the undulation angle of the linear cutting line mark can be adjusted correspondingly by adjusting one or more of the three parameters, so that the deviation tendency of the linear cutting line mark from the efficient cutting surface to the inefficient cutting surface is inhibited. For example, when the undulation angle of the line mark of the wire cutting is in the range of 150 ° to 160 °, the tension of the cutting line is adjusted in the range of 2.6N to 3.8N, the feeding speed of the silicon rod to the cutting line is adjusted in the range of 15mm/h to 16mm/h, and the mortar concentration is adjusted in the range of 2.55kg/L to 2.7 kg/L.
In order to accurately measure the relief angle of the cut line mark, preferably, the obtaining the relief angle of the cut line mark on the sample silicon wafer includes:
polishing a part of the surface of the sample silicon wafer to an inclined mirror surface with a set angle;
measuring the undulation angle of the wire cut line trace at a boundary between an unpolished portion and a polished portion of the surface of the sample silicon wafer using a microscope.
Referring to fig. 8, a part of the surface of a sample silicon wafer S is polished to a bevel mirror PC at an angle θ with respect to a standard cut surface SC, whereby a cut line mark can be exposed at a boundary BL of the bevel mirror PC and an unpolished portion, and then the relief angle of the cut line mark can be measured at the boundary BL using a microscope.
In order to improve the testing efficiency, the polishing of the surface of the sample silicon wafer may be performed in two stages, and preferably, the step of polishing a portion of the surface of the sample silicon wafer to a set angle includes: and respectively performing first-stage polishing and second-stage polishing by using a first polishing pad and a second polishing pad, wherein the polishing amount of the first polishing pad to the silicon wafer is larger than that of the second polishing pad to the silicon wafer, so that the line marks on the surface of the sample silicon wafer can be removed by rough polishing in the first stage, and then the surface can be made into a mirror surface by fine polishing in the second stage.
Preferably, the duration of the first stage of polishing is less than the duration of the second stage of polishing.
Further preferably, when the first polishing pad is used for polishing, the rotation speed of the first polishing pad is between 20r/min and 40 r/min; when the second polishing pad is used for polishing, the rotating speed of the second polishing pad is between 50r/min and 70 r/min.
Embodiments of the present invention also provide a wire cutting apparatus, which is configured to perform the above-described method.
Embodiments of the present invention also provide a silicon wafer, which is manufactured by using the above-described method.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method for wire cutting a silicon rod, the method comprising:
wire-cutting the first silicon rod using a first wire-cutting process parameter set to obtain a plurality of sample silicon wafers;
obtaining the fluctuation angle of the linear cutting line mark on the sample silicon wafer;
judging whether the linear cutting line mark has a tendency of offsetting from the efficient cutting surface to the inefficient cutting surface or not based on the fluctuating angle;
based on the judgment result, adjusting one or more linear cutting process parameters in the first linear cutting process parameter group according to the size of the fluctuation angle to form a second linear cutting process parameter group;
and linearly cutting a second silicon rod by adopting the second linear cutting process parameter group.
2. The method according to claim 1, wherein the undulation angle of the linear cutting line mark is an included angle between a plane in which the adjacent female line mark and male line mark are located and a standard cutting plane.
3. The method according to claim 1, wherein when the obtained undulation angle is less than 160 °, it is determined that there is a tendency of deviation of the wire-cut line trace from the high-efficiency cutting surface to the low-efficiency cutting surface.
4. The method according to any one of claims 1 to 3, wherein the set of wire cutting process parameters comprises at least: tension of the cutting wire, feed speed of the silicon rod relative to the cutting wire, concentration of the cutting fluid.
5. The method according to any one of claims 1 to 3, wherein the obtaining of the relief angle of the wire cut line mark on the sample silicon wafer comprises:
polishing a part of the surface of the sample silicon wafer to an inclined mirror surface with a set angle;
measuring the undulation angle of the wire cut line trace at a boundary between an unpolished portion and a polished portion of the surface of the sample silicon wafer using a microscope.
6. The method of claim 5, wherein polishing a portion of the surface of the sample silicon wafer to a set angle of a tilted mirror comprises: and respectively executing the first-stage polishing and the second-stage polishing by using a first polishing pad and a second polishing pad, wherein the polishing quantity index of the first polishing pad to the silicon wafer is greater than that of the second polishing pad to the silicon wafer.
7. The method of claim 6, wherein the duration of the first stage of polishing is less than the duration of the second stage of polishing.
8. The method of claim 6, wherein the first polishing pad is rotated at a speed of between 20r/min and 40r/min during polishing using the first polishing pad;
when the second polishing pad is used for polishing, the rotating speed of the second polishing pad is between 50r/min and 70 r/min.
9. A wire cutting apparatus for carrying out the method according to any one of claims 1 to 8.
10. A silicon wafer, characterized in that it is produced by using the method according to any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211601961.9A CN115946251A (en) | 2022-12-13 | 2022-12-13 | Method and equipment for wire-electrode cutting silicon rod and silicon wafer |
| TW112105974A TWI849756B (en) | 2022-12-13 | 2023-02-18 | Method, device and silicon wafer for wire cutting of silicon rod |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211601961.9A CN115946251A (en) | 2022-12-13 | 2022-12-13 | Method and equipment for wire-electrode cutting silicon rod and silicon wafer |
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| CN115946251A true CN115946251A (en) | 2023-04-11 |
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| CN202211601961.9A Pending CN115946251A (en) | 2022-12-13 | 2022-12-13 | Method and equipment for wire-electrode cutting silicon rod and silicon wafer |
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| CH692331A5 (en) * | 1996-06-04 | 2002-05-15 | Tokyo Seimitsu Co Ltd | Wire saw and cutting method using the same. |
| JP5605946B2 (en) * | 2010-02-23 | 2014-10-15 | 株式会社安永 | Wire saw apparatus and wafer manufacturing method using the same |
| JP6132621B2 (en) * | 2013-03-29 | 2017-05-24 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Method for slicing semiconductor single crystal ingot |
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