CN115881525A - Ultrathin wafer, flexible chip preparation method and flexible chip - Google Patents
Ultrathin wafer, flexible chip preparation method and flexible chip Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The disclosure relates to a preparation method of an ultrathin wafer and a flexible chip and the flexible chip, wherein the method comprises the following steps: carrying out mechanical grinding on the back surface of the wafer, wherein the front surface of the wafer is provided with a protective film; placing the wafer into a chemical etching solution to perform chemical etching on the back surface of the wafer under the condition that the wafer thickness of the wafer is reduced to a target grinding thickness; under the condition that the chemical corrosion duration reaches the preset duration, scribing the wafer to obtain a plurality of chips, and transferring each chip to a temporary substrate; performing reactive ion etching on the chip to reduce the chip thickness of the chip to a target thickness; and transferring the chip to a flexible substrate to obtain the flexible chip. The embodiment of the disclosure reduces the thickness of the chip to the maximum extent, does not weaken the normal performance of the device, can effectively eliminate the damage caused by the mechanical grinding in the material in the prior art, weakens the residual stress of the ultrathin chip, and reduces the warpage of the chip.
Description
Technical Field
The disclosure relates to the technical field of semiconductor processes, in particular to a preparation method of an ultrathin wafer and a flexible chip and the flexible chip.
Background
The flexible electronic device has wide application in the aspects of human health medical treatment, flexible display, large-scale component structure health monitoring and the like. The ultrathin chip (the thickness is less than 50 μm) has good flexibility due to low bending rigidity, and is the core of data processing and signal transmission in the flexible electronic device. The ultra-thinning treatment of the chip is also beneficial to improving the heat dissipation performance of the chip and reducing the on-resistance and on-voltage drop of the power chip, thereby improving the overall performance of the chip. In addition, the ultrathin chip is an important way for realizing advanced packaging forms such as heterogeneous integration, three-dimensional integrated circuits and the like, and the continuous development of the moore's law is promoted. At present, mechanical grinding and chemical mechanical polishing are mostly adopted to thin on an integrated circuit manufacturing production line. However, due to the intrinsic hard and brittle characteristics of the inorganic semiconductor material, the precise mechanical grinding is easy to cause material damage to the chip in the processing process, so that the residual stress of the chip is too large, and the chip is warped and deformed, even broken and fails.
Disclosure of Invention
According to an aspect of the present disclosure, a method for manufacturing an ultra-thin wafer and a flexible chip is provided, the method including:
carrying out mechanical grinding on the back surface of the wafer, wherein the front surface of the wafer is provided with a protective film;
placing the wafer into a chemical etching solution to perform chemical etching on the back surface of the wafer under the condition that the thickness of the wafer is reduced to a target grinding thickness;
under the condition that the chemical corrosion duration reaches a preset duration, scribing the wafer to obtain a plurality of chips, and transferring each chip to a temporary substrate;
performing reactive ion etching on the chip to reduce the chip thickness of the chip to a target thickness;
and transferring the chip to a flexible substrate to obtain the flexible chip.
In one possible embodiment, the mechanical grinding of the wafer back side of the wafer includes:
placing the wafer on a workbench of a grinding machine, and setting the rotating speed of the workbench to be 200-300 rpm, the rotating speed of a grinding wheel of the grinding machine to be 3000-5000 rpm and the feeding speed of the grinding machine to be 1-4 mu m/s so as to carry out coarse grinding on the back surface of the wafer, wherein the mesh number of the grinding wheel of the grinding machine in the coarse grinding is 300-1200;
setting the rotating speed of a workbench to be 200-400 rpm, the rotating speed of a grinding wheel of a grinding machine to be 1000-4000 rpm and the feeding speed of the grinding machine to be 0.2-1 mu m/s under the condition that the wafer thickness of the wafer is reduced to the rough grinding target thickness, carrying out fine grinding on the back surface of the wafer to reduce the wafer thickness of the wafer to the target grinding thickness, wherein the mesh number of the grinding wheel of the grinding machine in the fine grinding is more than or equal to 6000,
the rough grinding target thickness is greater than the target grinding thickness.
In one possible embodiment, the target abrasive thickness is 30 μm to 50 μm.
In a possible embodiment, the chemical etching solution comprises 70.0% by mass of nitric acid, 99.8% by mass of acetic acid, 40.0% by mass of hydrofluoric acid and water, and the preset time period is 2-10 minutes.
In one possible embodiment, the dicing the wafer to obtain a plurality of chips, and transferring each chip onto a temporary substrate includes:
adhering a support film on the back of the wafer, wherein the adhering temperature is 80-100 ℃, and the temperature holding time is 1-3 minutes;
irradiating the front surface of the wafer with ultraviolet rays for 10-40 s, and removing the protective film on the front surface of the wafer;
scribing the wafer, and stripping each chip from the support film;
and transferring each chip to a corresponding temporary substrate, wherein the substrate material of the temporary substrate is a thin film/bulk material with reversible interface adhesion.
In one possible embodiment, the performing reactive ion etching on the chip to reduce the chip thickness of the chip to a target thickness includes:
placing the chip into a reaction chamber of reactive ion etching equipment;
and introducing reaction gas into the reaction chamber, and applying high pressure to the reaction chamber to generate plasma in the reaction chamber so as to etch the back surface of the wafer, wherein the flow rate of the reaction gas is 20-200 mL/min, the generated radio frequency power is 20-120W, and the working pressure is 8-15 pa.
In one possible embodiment, transferring the chip to a flexible substrate results in a flexible chip comprising:
spin-coating a layer of polyimide glue on a flexible substrate;
transferring the chip after the reactive ion etching is finished to the flexible substrate by using a PDMS stamp;
and removing the PDMS stamp to obtain the flexible chip.
In one possible embodiment, the thickness of the chip is 4 μm to 6 μm.
In one possible embodiment, before the mechanical grinding is performed on the wafer back side of the wafer, the method further includes:
and arranging the protective film on the front surface of the wafer to protect the circuit on the front surface of the wafer.
According to an aspect of the disclosure, a flexible chip is provided, which is obtained according to the ultrathin wafer and the flexible chip preparation method.
The wafer back side of the wafer is mechanically ground, the wafer is placed into a chemical corrosion solution under the condition that the wafer thickness of the wafer is reduced to a target grinding thickness, the wafer is subjected to chemical corrosion, the wafer thickness is further reduced, the wafer is diced under the condition that the chemical corrosion duration reaches a preset duration to obtain a plurality of chips, the chips are transferred onto a temporary substrate, reactive ion etching is carried out on the chips to reduce the chip thickness of the chips to the target thickness, on the basis of further reduction of the chip thickness, damage caused by preorder mechanical grinding in materials can be eliminated, residual stress of ultrathin chips is weakened, warping deformation of the chips is reduced, the flexible chips are obtained by transferring the chips to a flexible substrate, and the ultrathin chips are manufactured by combining mechanical grinding, chemical corrosion and reactive ion etching.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a flow chart of an ultra-thin wafer and a flexible chip manufacturing method according to an embodiment of the disclosure.
Fig. 2 shows a flow chart of an ultra-thin wafer and a flexible chip manufacturing method according to an embodiment of the disclosure.
Fig. 3a shows a schematic diagram of a mechanical polishing process performed on a wafer according to an embodiment of the disclosure.
Fig. 3b shows a schematic flow chart of mechanical grinding performed by an embodiment of the present disclosure.
Fig. 4 shows a schematic diagram of chemically etching the backside of a wafer according to an embodiment of the disclosure.
Figure 5a shows a schematic diagram of dicing a wafer and transferring chips according to an embodiment of the disclosure.
FIG. 5b shows a schematic diagram of reactive ion etching and transfer printing on a chip according to an embodiment of the disclosure.
FIG. 6 shows a schematic diagram of reactive ion etching of a chip according to an embodiment of the disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings, which is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and, therefore, should not be taken as limiting the present disclosure.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.
In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a variety or any combination of at least two of a variety, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.
Referring to fig. 1, fig. 1 is a flow chart illustrating a method for manufacturing an ultra-thin wafer and a flexible chip according to an embodiment of the disclosure.
As shown in fig. 1, the method includes:
step S11, carrying out mechanical grinding on the back surface of the wafer, wherein the front surface of the wafer is provided with a protective film;
step S12, under the condition that the thickness of the wafer is reduced to the target grinding thickness, putting the wafer into a chemical corrosion solution to carry out chemical corrosion on the back of the wafer;
s13, scribing the wafer to obtain a plurality of chips under the condition that the chemical corrosion duration reaches a preset duration, and transferring each chip to a temporary substrate;
step S14, performing Reactive Ion Etching (RIE) on the chip to reduce the chip thickness of the chip to a target thickness;
and S15, transferring the chip to a flexible substrate to obtain a flexible chip.
The wafer back side of the wafer is mechanically ground, the wafer is placed into a chemical corrosion solution under the condition that the wafer thickness of the wafer is reduced to a target grinding thickness, the wafer is subjected to chemical corrosion, the wafer thickness is further reduced, the wafer is diced under the condition that the chemical corrosion duration reaches a preset duration to obtain a plurality of chips, the chips are transferred onto a temporary substrate, reactive ion etching is carried out on the chips to reduce the chip thickness of the chips to the target thickness, on the basis of further reduction of the chip thickness, damage caused by preorder mechanical grinding in materials can be eliminated, residual stress of ultrathin chips is weakened, warping deformation of the chips is reduced, the flexible chips are obtained by transferring the chips to a flexible substrate, and the ultrathin chips are manufactured by combining mechanical grinding, chemical corrosion and reactive ion etching.
The embodiment of the present disclosure does not limit the specific implementation manner of mechanically grinding the back surface of the wafer in step S11, and does not limit the size of the target grinding thickness, which can be implemented by those skilled in the art according to actual situations and needs.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for manufacturing an ultra-thin wafer and a flexible chip according to an embodiment of the disclosure.
In one possible embodiment, as shown in fig. 2, before the mechanical grinding is performed on the wafer back side of the wafer, the method may further include:
and S10, arranging the protective film on the front surface of the wafer to protect the circuit on the front surface of the wafer.
The type of the protective film is not limited in the embodiments of the present disclosure, and a person skilled in the art may select an adhesive film having a moderate hardness and capable of adhering tightly to the front surface of the wafer according to actual conditions and needs, for example, the adhesive film may be a UV film or a non-UV film, and for example, the thickness of the protective film may be 600 to 700 μm, and preferably may be 700 μm.
According to the embodiment of the disclosure, the protective adhesive film is arranged on the front surface of the wafer, so that the front surface circuit structure can not be damaged due to mechanical extrusion in the subsequent thinning process, and liquid (such as corrosive liquid) can be inhibited from permeating between the adhesive film and the front surface of the wafer, so that the front surface circuit of the wafer is protected from being influenced.
In a possible implementation manner, as shown in fig. 2, the step S11 of performing mechanical grinding on the wafer back side of the wafer may include:
step S111, placing the wafer on a workbench of a grinding machine, and setting the rotating speed of the workbench to be 200-300 rpm, the rotating speed of a grinding wheel of the grinding machine to be 3000-5000 rpm and the feeding speed of the grinding machine to be 1-4 mu m/S so as to carry out coarse grinding on the back surface of the wafer, wherein the mesh number of the grinding wheel of the grinding machine in the coarse grinding is 300-1200;
and step S112, setting the rotating speed of a workbench to be 200-400 rpm, the rotating speed of a grinding wheel of a grinding machine to be 1000-4000 rpm and the feeding speed of the grinding machine to be 0.2-1 μm/S under the condition that the wafer thickness of the wafer is reduced to the rough grinding target thickness, and carrying out fine grinding on the back surface of the wafer to reduce the wafer thickness of the wafer to the target grinding thickness, wherein the mesh number of the grinding wheel of the grinding machine in the fine grinding is greater than or equal to 6000, and the rough grinding target thickness is greater than the target grinding thickness.
In one possible embodiment, the target abrasive thickness may be 30 μm to 50 μm.
Referring to fig. 3a, fig. 3a is a schematic diagram illustrating mechanical polishing of a wafer according to an embodiment of the disclosure.
Referring to fig. 3b, fig. 3b is a schematic diagram illustrating a process of performing mechanical polishing according to an embodiment of the disclosure.
In one example, as shown in fig. 3a and 3b, a wafer with a front side pasted with a protective film may be placed on a worktable of a grinding machine, a back side of the wafer faces upward, and for example, assuming that an initial thickness of the wafer is 700 μm, a general grinding process adopts coarse grinding and then fine grinding, and first enters a coarse grinding stage, a 600# grinding wheel (with mesh number of 600) may be used, a revolving speed of the worktable is set to 200rpm, a revolving speed of the grinding wheel is set to 3000rpm, a feeding speed is set to 1 μm/s, the grinding wheel keeps feeding downwards while rotating around a high speed shaft, diamond abrasive grains are attached to the grinding wheel, a certain interaction force exists between the diamond abrasive grains and the back side of the wafer, including a normal force and a tangential force, during a physical friction process of the diamond abrasive grains on the back side of the wafer, the thickness of the wafer may be reduced from 700 μm to 100 μm in the coarse grinding stage, a large area of wafer thickness reduction may be achieved by using a low mesh grinding wheel, but a violent interaction between the abrasive grains and the wafer may cause material damage, including amorphization, dislocation, microcrack, etc. of a silicon single crystal. Then, entering a fine grinding stage, adopting a 8000# grinding wheel, setting the rotating speed of a workbench at 200rpm, setting the rotating speed of the grinding wheel at 4000rpm, setting the feed rate at 0.2 μm/s, and thinning the thickness of the wafer from 100 μm to 30 μm in the fine grinding stage to finish the mechanical grinding and thinning process.
In a possible embodiment, the chemical etching solution comprises 70.0% by mass of nitric acid, 99.8% by mass of acetic acid, 40.0% by mass of hydrofluoric acid and water, and the preset time period is 2-10 minutes.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a chemical etching process performed on the back side of a wafer according to an embodiment of the disclosure.
In one example, as shown in fig. 4, in the case that the wafer thickness of the wafer is reduced to the target polishing thickness, the wafer is placed in a reaction tank containing a chemical etching solution to chemically etch the back surface of the wafer, so that the damaged layer caused by mechanical grinding can be removed, and the wafer thickness can be reduced from 30 μm to about 15 μm with relatively high efficiency, although if the thickness is desired to be reduced continuously, the chemical etching cannot be continued, because the wafer is placed in the reaction tank during the etching process, through tests, the 15 μm wafer is already very flexible, and the wafer may be broken due to excessive deformation during the fishing process in the etching solution, and therefore, the wafer can be reduced to 15 μm by the chemical etching process in the disclosed embodiments.
Referring to fig. 5a, fig. 5a is a schematic diagram illustrating a wafer dicing and chip transferring process according to an embodiment of the disclosure.
In a possible implementation manner, as shown in fig. 2 and fig. 5a, the step S13 of scribing the wafer to obtain a plurality of chips, and transferring each chip onto the temporary substrate may include:
step S131, adhering a support film on the back of the wafer, wherein the adhering temperature is 80-100 ℃, and the temperature holding time is 1-3 minutes;
for example, as shown in fig. 5a, the wafer after the chemical etching is finished may be transferred to an iron ring with a supporting adhesive film (which may be a blue film), and the back of the wafer is adhered to the supporting adhesive film, which may provide a certain mechanical support for the ultra-thin wafer and facilitate the ultra-thin wafer to be transported on a production line. Illustratively, the wafer can be vacuum-adsorbed on the worktable and kept at 80 ℃ for 1min, so that the blue film is tightly adhered to the back surface of the wafer.
In a possible implementation manner, as shown in fig. 2 and fig. 5a, the step S13 of scribing the wafer to obtain a plurality of chips, and transferring each chip onto the temporary substrate may include:
step S132, irradiating the front surface of the wafer with ultraviolet rays for 10-40S, and removing the protective film on the front surface of the wafer;
for example, as shown in fig. 5a, the front surface of the wafer may be irradiated with ultraviolet rays for 10 seconds to reduce the adhesive strength of the adhesive film adhered to the front surface of the wafer, and the protective adhesive film may be peeled off after the irradiation.
In a possible implementation manner, as shown in fig. 2 and fig. 5a, the step S13 of scribing the wafer to obtain a plurality of chips, and transferring each chip onto the temporary substrate may include:
step S133, scribing the wafer, and stripping each chip from the support film;
for example, as shown in fig. 5a, the wafer may be diced according to the positions of the wafer dicing streets, at this time, the wafer is decomposed into small chips and falls on the blue film, and the single chip may be peeled off from the blue film through the cooperation of the ejector pin and the suction cup.
In a possible implementation manner, as shown in fig. 2 and fig. 5a, the step S13 of scribing the wafer to obtain a plurality of chips, and transferring each chip onto the temporary substrate may include:
in step S134, each chip is transferred to a corresponding temporary substrate, and the substrate material of the temporary substrate is a film/bulk material with reversible interfacial adhesion.
For example, as shown in fig. 5a, the chip peeled off in the previous step may be picked up by means of a PDMS stamp, the front surface of the chip is contacted with the PDMS stamp, and the single chip is transferred into the chamber of the reactive ion etching apparatus.
For example, the temporary substrate can provide a functional layer for supporting, fixing and protecting the front surface of the chip in subsequent processes of the single chip, and facilitate transportation to other production line equipment. The temporary substrate material may be a thin film/bulk material such as hydrosol, thermal release tape or PDMS that can provide reversible interfacial adhesion.
Referring to fig. 5b and fig. 6 together, fig. 5b shows a schematic diagram of performing reactive ion etching and transfer printing on a chip according to an embodiment of the disclosure, and fig. 6 shows a schematic diagram of performing reactive ion etching on a chip according to an embodiment of the disclosure.
In a possible embodiment, as shown in fig. 2, 5b, and 6, the step S14 of performing reactive ion etching on the chip to reduce the chip thickness of the chip to a target thickness may include:
step S141, placing the chip into a reaction chamber of a reactive ion etching device;
for example, as shown in fig. 6, after the chip is transferred to a temporary substrate (e.g., a PDMS substrate), the chip may be further transferred to a workbench in a reaction chamber of a reactive ion etching apparatus, and the transfer process may be performed by transferring using a stamp or by using a combination of an ejector and a chuck, which is not limited in the embodiment of the disclosure.
In a possible embodiment, as shown in fig. 2, 5b, and 6, the step S14 of performing reactive ion etching on the chip to reduce the chip thickness of the chip to a target thickness may include:
and step S142, introducing reaction gas into the reaction chamber, and applying high pressure to the reaction chamber to generate plasma in the reaction chamber to etch the back of the wafer, wherein the flow rate of the reaction gas is 20-200 mL/min, the generated radio frequency power is 20-120W, and the working pressure is 8-15 pa.
Illustratively, as shown in FIGS. 5b and 6, reactive ion etching utilizes primarily fluorine-based gases (e.g., SF) 6 ) And oxygen, argon and the like, and the whole reaction chamber is filled according to certain working pressure. A high-frequency electric field is applied to etching gas in the reaction chamber to generate glow discharge, so that the gas in the reaction chamber generates plasma which mainly comprises active free radicals with chemical activity formed by splitting and more electrons and ions formed by ionization. SF 6 In the glow discharge process, active free radicals F are generated and reach the back of the chip to carry out chemical reaction with surface atoms, and generated volatile substances are discharged along with waste gas, so that the purpose of corroding the surface layer of the sample is achieved. And the charged ions carry out physical bombardment on the film to further promote etching. Finishing machineThe etching process has good anisotropy, and the chemical reaction formula is as follows:
SF 6 +e→SF 5 + + F (radical) +2e (1)
Si+4F→SF 4 (volatile gas) (2)
Because the silicon-based material on the back of the chip is subjected to little interaction in the reactive ion etching process, the material damage caused by mechanical grinding can be effectively removed, the residual stress on the back of the chip is weakened, and the thickness of the chip is further reduced on the basis of the mechanical grinding.
Illustratively, SF may be set 6 The flow rate is 20mL/min, the radio frequency power is 20W, and the working air pressure is 8Pa, so that the thickness of the single chip can be reduced from 15 mu m to 5 mu m. In the anisotropic etching process, the damage introduced by the grinding can be further removed, and the residual stress level of the back surface of the chip can be reduced.
In one possible embodiment, as shown in fig. 2 and 5b, the step S15 transfers the chip to a flexible substrate to obtain a flexible chip, which includes:
step S151, spin-coating a layer of polyimide glue on a flexible substrate;
step S152, transferring the chip after the reactive ion etching is finished to the flexible substrate by using a PDMS stamp;
and S153, removing the PDMS stamp to obtain the flexible chip.
Illustratively, the flexible substrate may be, for example, PI (polyimide), PDMS, etc., and a flexible PI (polyimide) substrate may be prepared and a layer of polyimide paste may be spin-coated on the substrate. After RIE thinning, the single chip is still on the temporary substrate, and the single chip is transferred to the target flexible substrate by utilizing the reversible interface adhesion force of the temporary substrate. And transferring the single chip thinned by the RIE to a flexible PI (polyimide) substrate by using a PDMS stamp. At this time, the front surface of the single chip is in contact with the PDMS stamp, and the back surface of the single chip is in contact with the flexible PI (polyimide) substrate. After the glue is cured, the chip can be well bonded with the flexible PI substrate. And peeling the PDMS stamp and the temporary substrate to obtain the ultrathin flexible chip integrated on the flexible substrate.
In one possible embodiment, the thickness of the chip is 4 μm to 6 μm.
The damage of the preorder mechanical grinding introduced in the material can be effectively eliminated in the subsequent reactive ion etching process of the ultrathin flexible chip, the residual stress of the ultrathin chip is weakened, and the warping deformation of the chip is reduced. And the thickness of the chip can be reduced to the maximum extent without influencing the active area of the chip, and the normal performance of the device is not weakened.
Based on the technical route, the limiting thickness of the ultrathin flexible chip is far lower than the thickness limit of mechanical grinding, the wafer is further thinned by using a chemical corrosion method, certain mechanical damage is removed, residual stress introduced to the back of the ultrathin chip in the processing process can be well removed in an RIE mode, and material damage introduced in the technological process is removed.
According to an aspect of the present disclosure, a flexible chip is provided, which is obtained according to the ultrathin wafer and the flexible chip preparation method.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A preparation method of an ultrathin wafer and a flexible chip is characterized by comprising the following steps:
carrying out mechanical grinding on the back surface of the wafer, wherein the front surface of the wafer is provided with a protective film;
placing the wafer into a chemical etching solution to perform chemical etching on the back surface of the wafer under the condition that the wafer thickness of the wafer is reduced to a target grinding thickness;
under the condition that the chemical corrosion duration reaches a preset duration, scribing the wafer to obtain a plurality of chips, and transferring each chip to a temporary substrate;
performing reactive ion etching on the chip to reduce the chip thickness of the chip to a target thickness;
and transferring the chip to a flexible substrate to obtain the flexible chip.
2. The method of claim 1, wherein the mechanically grinding the wafer back side of the wafer comprises:
placing the wafer on a workbench of a grinding machine, and setting the rotating speed of the workbench to be 200-300 rpm, the rotating speed of a grinding wheel of the grinding machine to be 3000-5000 rpm and the feeding speed of the grinding machine to be 1-4 mu m/s so as to carry out coarse grinding on the back surface of the wafer, wherein the mesh number of the grinding wheel of the grinding machine in the coarse grinding is 300-1200;
setting the rotation speed of a workbench to be 200-400 rpm, the rotation speed of a grinding wheel of a grinding machine to be 1000-4000 rpm and the feeding speed of the grinding machine to be 0.2-1 mu m/s under the condition that the wafer thickness of the wafer is reduced to the rough grinding target thickness so as to carry out fine grinding on the back surface of the wafer and reduce the wafer thickness of the wafer to the target grinding thickness, wherein the mesh number of the grinding wheel of the grinding machine in the fine grinding is more than or equal to 6000,
the rough grinding target thickness is greater than the target grinding thickness.
3. The method according to claim 1 or 2, wherein the target abrasive thickness is 30 μm to 50 μm.
4. The method according to claim 1, wherein the chemical etching solution comprises 70.0 mass percent of nitric acid, 99.8 mass percent of acetic acid, 40.0 mass percent of hydrofluoric acid and water, and the preset time period is 2-10 minutes.
5. The method of claim 1, wherein dicing the wafer to obtain a plurality of chips and transferring each chip to a temporary substrate comprises:
adhering a support film on the back of the wafer, wherein the adhering temperature is 80-100 ℃, and the temperature holding time is 1-3 minutes;
irradiating the front surface of the wafer with ultraviolet rays for 10-40 s, and removing the protective film on the front surface of the wafer;
scribing the wafer, and stripping each chip from the support film;
and transferring each chip to a corresponding temporary substrate, wherein the substrate material of the temporary substrate is a thin film/bulk material with reversible interfacial adhesion.
6. The method of claim 1, wherein reactive ion etching the chip to reduce the chip thickness of the chip to a target thickness comprises:
placing the chip into a reaction chamber of a reactive ion etching device;
and introducing reaction gas into the reaction chamber, and applying high pressure to the reaction chamber to generate plasma in the reaction chamber so as to etch the back surface of the wafer, wherein the flow rate of the reaction gas is 20-200 mL/min, the generated radio frequency power is 20-120W, and the working pressure is 8-15 pa.
7. The method of claim 1, wherein transferring the chip to a flexible substrate results in a flexible chip comprising:
spin-coating a layer of polyimide glue on a flexible substrate;
transferring the chip after the reactive ion etching is finished to the flexible substrate by using a PDMS stamp;
and removing the PDMS stamp to obtain the flexible chip.
8. The method of claim 1, wherein the thickness of the chip is 4 μm to 6 μm.
9. The method of claim 1, wherein prior to mechanically grinding the wafer backside of the wafer, the method further comprises:
and arranging the protective film on the front surface of the wafer to protect the circuit on the front surface of the wafer.
10. A flexible chip, wherein the flexible chip is obtained by the ultrathin wafer and the flexible chip preparation method according to any one of claims 1 to 9.
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| JPH08241977A (en) * | 1995-03-03 | 1996-09-17 | Hamamatsu Photonics Kk | Manufacture of semiconductor device |
| US6046073A (en) * | 1997-11-26 | 2000-04-04 | Siemens Aktiengesellschaft | Process for producing very thin semiconductor chips |
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