CN115881024A - Display substrate and display device - Google Patents
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- CN115881024A CN115881024A CN202211366031.XA CN202211366031A CN115881024A CN 115881024 A CN115881024 A CN 115881024A CN 202211366031 A CN202211366031 A CN 202211366031A CN 115881024 A CN115881024 A CN 115881024A
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- 239000003990 capacitor Substances 0.000 claims abstract description 151
- 239000002184 metal Substances 0.000 claims description 66
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Abstract
The embodiment of the invention provides a display substrate and a display device, wherein a compensation capacitor is arranged, one polar plate of the compensation capacitor is electrically connected with an initial trigger signal line, and the other polar plate of the compensation capacitor is electrically connected with a low-voltage signal line. Therefore, the embodiment of the invention can improve the ESD resistance of the initial trigger signal line by increasing the capacitance of the initial trigger signal line, and prevent the initial trigger signal line from short-circuit failure.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate and a display device.
Background
With the development of display screens, narrow-frame and high-resolution display screens are more and more favored by users, and a common gate drive circuit is complicated in connection and occupies a larger area on the display screen. In the Array substrate row driving (GOA) technology, a grid driving circuit is manufactured on an Array substrate, so that a separate grid driving integrated circuit part is omitted, row scanning of grids is realized, the material cost and the manufacturing cost of a display device are reduced, and the frame design of a panel is reduced.
Disclosure of Invention
The embodiment of the invention provides a display substrate and a display device, and the specific scheme is as follows:
the embodiment of the invention provides a display substrate, which comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a display area and a GOA circuit area arranged on the periphery of the display area; the GOA circuit region includes: the GOA circuit board comprises a plurality of mutually cascaded GOA units, a starting trigger signal line and a low-voltage signal line, wherein the GOA units are arranged on a substrate, the starting trigger signal line is electrically connected with at least one GOA unit, and the low-voltage signal line is electrically connected with the GOA units; the initial trigger signal line and the low-voltage signal line both extend along the arrangement direction of the plurality of mutually cascaded GOA units, and the initial trigger signal line is positioned on one side, far away from the display area, of the plurality of mutually cascaded GOA units;
one pole plate of the compensation capacitor is electrically connected with the initial trigger signal line, and the other pole plate of the compensation capacitor is electrically connected with the low-voltage signal line.
Optionally, in the display substrate provided in the embodiment of the present invention, the compensation capacitor includes a first compensation capacitor, a first plate of the first compensation capacitor is a part of the start trigger signal line, an orthogonal projection of a second plate of the first compensation capacitor on the substrate overlaps an orthogonal projection of the part of the start trigger signal line on the substrate, and the second plate of the first compensation capacitor is electrically connected to the low-voltage signal line.
Optionally, in the display substrate provided in the embodiment of the present invention, the display substrate includes a gate metal layer, a gate insulating layer, a source-drain metal layer, a passivation layer, and a transparent conductive layer, which are stacked on the substrate, where the initial trigger signal line and the low-voltage signal line are both located in the gate metal layer, the second plate of the first compensation capacitor is located in the source-drain metal layer, and the transparent conductive layer includes a first connection portion;
the second plate of the first compensation capacitor is electrically connected with one end of the first connecting portion through a first via hole penetrating through the passivation layer, and the other end of the first connecting portion is electrically connected with the low-voltage signal line through a second via hole penetrating through the passivation layer and the gate insulating layer.
Optionally, in the display substrate provided in the embodiment of the present invention, the compensation capacitor includes a second compensation capacitor, a first plate of the second compensation capacitor is a part of the low-voltage signal line, an orthogonal projection of a second plate of the second compensation capacitor on the substrate overlaps an orthogonal projection of the part of the low-voltage signal line on the substrate, and a second plate of the second compensation capacitor is electrically connected to the start trigger signal line.
Optionally, in the display substrate provided in the embodiment of the present invention, the display substrate includes a gate metal layer, a gate insulating layer, a source-drain metal layer, a passivation layer, and a transparent conductive layer, which are stacked on the substrate, where the initial trigger signal line and the low-voltage signal line are both located in the gate metal layer, the second plate of the second compensation capacitor is located in the source-drain metal layer, and the transparent conductive layer includes a second connection portion;
the second pole plate of the second compensation capacitor is electrically connected with one end of the second connecting part through a third through hole penetrating through the passivation layer, and the other end of the second connecting part is electrically connected with the initial trigger signal line through a fourth through hole penetrating through the passivation layer and the gate insulating layer.
Optionally, in the display substrate provided in the embodiment of the present invention, a test pad group located on a side of a first row of GOA units away from a last row of GOA units in the multiple mutually cascaded GOA units is further included, where the compensation capacitor includes a third compensation capacitor, and the third compensation capacitor is located between the test pad group and the first row of GOA units;
the first polar plate of the third compensation capacitor is a part of the low-voltage signal line, the orthographic projection of the second polar plate of the third compensation capacitor on the substrate base plate and the orthographic projection of the low-voltage signal line on the substrate base plate have an overlapping region, and the second polar plate of the third compensation capacitor is electrically connected with the initial trigger signal line.
Optionally, in the display substrate provided in an embodiment of the present invention, a portion of the low-voltage signal line is a portion of the low-voltage signal line extending to a side of the start trigger signal line.
Optionally, in the display substrate provided in the embodiment of the present invention, the display substrate includes a gate metal layer, a gate insulating layer, a source-drain metal layer, a passivation layer, and a transparent conductive layer, which are stacked on the substrate, where the initial trigger signal line and the low-voltage signal line are both located in the gate metal layer, the second plate of the third compensation capacitor is located in the source-drain metal layer, and the transparent conductive layer includes a third connection portion;
and the second plate of the third compensation capacitor is electrically connected with one end of the third connecting part through a fifth via hole penetrating through the passivation layer, and the other end of the third connecting part is electrically connected with the initial trigger signal line through a sixth via hole penetrating through the passivation layer and the gate insulating layer.
Optionally, in the display substrate provided in the embodiment of the present invention, one end of the start trigger signal line is electrically connected to a first GOA cell in the multiple mutually cascaded GOA cells through a first trace, and the other end of the start trigger signal line is electrically connected to a last GOA cell in the multiple mutually cascaded GOA cells through a second trace;
the compensation capacitor comprises a fourth compensation capacitor and a fifth compensation capacitor;
the first trace comprises a first part having an overlapping region with the low-voltage signal line, and along the extending direction of the low-voltage signal line, the width of the first part is greater than the width of the rest part in the first trace, the first plate of the fourth compensation capacitor is the first part, and the second plate of the fourth compensation capacitor is the part, overlapping with the first part, in the low-voltage signal line;
the second trace comprises a second portion having an overlapping region with the low-voltage signal line, and the width of the second portion is greater than the width of the rest portion in the second trace along the extending direction of the low-voltage signal line, the first plate of the fifth compensation capacitor is the second portion, and the second plate of the fifth compensation capacitor is the portion, overlapping with the second portion, in the low-voltage signal line.
Optionally, in the display substrate provided in an embodiment of the present invention, the low-voltage signal line is located between the start trigger signal line and the plurality of mutually cascaded GOA units.
Optionally, in the display substrate provided in an embodiment of the present invention, the low voltage signal line is located between the plurality of mutually cascaded GOA units and the display area.
Correspondingly, the embodiment of the invention also provides a display device, which comprises a display panel, wherein the display panel is the display substrate provided by the embodiment of the invention.
Drawings
Fig. 1 is a schematic plan view of a display substrate according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a one-side gate driver (GOA) circuit of FIG. 1;
fig. 3 is a schematic diagram illustrating an embodiment of a GOA circuit area on one side of fig. 1;
FIG. 4 is a schematic cross-sectional view taken along direction DD' in FIG. 3;
fig. 5 is a schematic diagram illustrating another embodiment of a GOA circuit region on one side of fig. 1;
FIG. 6 is a schematic cross-sectional view taken along direction EE' of FIG. 5;
fig. 7 is a schematic diagram illustrating another embodiment of a GOA circuit region on one side of fig. 1;
FIG. 8 is a schematic cross-sectional view taken along direction FF' of FIG. 7;
FIG. 9 is a schematic diagram of another embodiment of a GOA circuit region on one side of FIG. 1;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The use of "including" or "comprising" and the like in the present invention is intended to mean that the elements or items listed before the word "comprise" or "comprising" and the like, include the elements or items listed after the word and their equivalents, but do not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
Fig. 1 is a schematic plan view of a display substrate having a gate driver circuit (GOA), which includes a display area AA and a peripheral area located at the periphery of the display area AA, where the peripheral area includes a driver chip (IC), the gate driver circuit (GOA), routing lines, etc., fig. 2 is a schematic cascade diagram of the gate driver circuit (GOA) at one side in fig. 1, which includes a plurality of cascade-connected GOA units (for example, 6 GOA units), and a plurality of signal lines connected to the GOA units, such as a start trigger signal line STV, clock signal lines (CLK, CLKB), a low voltage signal line VGL, etc. The start trigger signal line STV is generally electrically connected to only the first row of GOA cells and the last row of GOA cells, and the clock signal lines (CLK, CLKB), the low voltage signal lines VGL, etc. are electrically connected to more GOA cells, so that the overlap positions of the start trigger signal line STV and other signal lines are fewer, the overlap positions of the clock signal lines (CLK, CLKB), the low voltage signal lines VGL, etc. and other signal lines are more, and the overlap positions of the signal lines form parasitic capacitors. As the size of the display product increases, the signal lines are lengthened, and electrostatic discharge (ESD) is easily generated in the product manufacturing process and the process test. The inventor of the present application analyzes and verifies that the primary reason why the ESD failure is easily caused in the GOA is the initial trigger signal line STV, and the primary reason why the ESD failure is easily caused in the initial trigger signal line STV is that the parasitic capacitance is obviously smaller than the signal lines such as CLK, CLKB, VGL, etc., because when the signal line is subjected to ESD, the electrostatic charge charges the parasitic capacitance of the signal line preferentially, and when the parasitic capacitance of the signal line is larger, the voltage difference between the two plates of the parasitic capacitance is smaller, the dielectric of the parasitic capacitance is less prone to be broken down, and thus the ESD resistance is higher. Therefore, the initial trigger signal line STV has a weak ESD resistance due to its small parasitic capacitance, and is very prone to fail problems such as burning and short-circuiting. Therefore, how to improve the ESD resistance of the start trigger signal line STV to avoid its failure has a great influence on the yield and quality of the display substrate manufacturing process.
In view of this, in order to improve the ESD resistance of the start trigger signal line STV, an embodiment of the invention provides a display substrate, as shown in fig. 1, including a substrate 1, the substrate 1 having a display area AA and a GOA circuit area BB disposed at the periphery of the display area; as shown in fig. 3, fig. 5, fig. 7 and fig. 9, fig. 3, fig. 5, fig. 7 and fig. 9 are respectively schematic specific structural diagrams of one side of the GOA circuit area BB in fig. 1, where the GOA circuit area BB includes: a plurality of mutually cascaded GOA cells 2 (taking 6 GOA cells 2 as an example, constituting a gate driving circuit) disposed on a substrate 1, a start trigger signal line STV electrically connected to at least one GOA cell 2, and a low voltage signal line VGL electrically connected to the GOA cells; the start triggering signal line STV and the low voltage signal line VGL both extend along the arrangement direction of the plurality of mutually cascaded GOA units 2, and the start triggering signal line STV is located at the side of the GOA circuit area BB farthest from the display area AA;
and the low-voltage trigger circuit further comprises a compensation capacitor C, one polar plate of the compensation capacitor C is electrically connected with the initial trigger signal line STV, and the other polar plate of the compensation capacitor C is electrically connected with the low-voltage signal line VGL.
In the display substrate provided by the embodiment of the invention, because the initial trigger signal line is located on the side farthest from the display area in the GOA circuit area BB, and the initial trigger signal line is generally electrically connected only with the first row of GOA units and the last row of GOA units, the overlapping area of the initial trigger signal line and other signal lines is small, so that the parasitic capacitance of the initial trigger signal line is small, therefore, by setting the compensation capacitor, one electrode plate of the compensation capacitor is electrically connected with the initial trigger signal line, and the other electrode plate of the compensation capacitor is electrically connected with the low-voltage signal line, that is, by increasing the capacitance of the initial trigger signal line, when the initial trigger signal line is subjected to ESD, the electrostatic charge preferentially charges the capacitance of the initial trigger signal line, and under the condition that the electrostatic charge amount is unchanged, when the capacitance is larger, the voltage difference between the two electrodes of the capacitance is smaller, the capacitance medium is less prone to be broken down, and thus the ESD resistance is higher. Therefore, the embodiment of the invention can improve the ESD resistance of the initial trigger signal line by increasing the capacitance of the initial trigger signal line, and prevent the initial trigger signal line from short-circuit failure.
In practical implementation, in the above display substrate provided in the embodiment of the present invention, as shown in fig. 3, the compensation capacitor C includes a first compensation capacitor C1, the first plate 31 of the first compensation capacitor C1 is a part of the start triggering signal line STV, an orthographic projection of the second plate 32 of the first compensation capacitor C1 on the substrate 1 overlaps with an orthographic projection of a part of the start triggering signal line STV on the substrate 1, and the second plate 32 of the first compensation capacitor C1 is electrically connected to the low voltage signal line VGL. Therefore, the routing wires (namely the second plate 32) overlapped with the initial trigger signal line STV orthographic projection can be arranged on other metal film layers of the display substrate, which are different from the metal film layer where the initial trigger signal line STV is positioned, and the overlapped area forms the first compensation capacitor C1, so that the capacitance of the initial trigger signal line STV is increased, and the ESD resistance of the initial trigger signal line STV is improved.
In specific implementation, as shown in fig. 3 and 4, in the display substrate provided in the embodiment of the present invention, fig. 4 is a schematic cross-sectional view along the DD' direction in fig. 3, and includes a gate metal layer G, a gate insulating layer GI, a source/drain metal layer SD, a passivation layer PVX, and a transparent conductive layer 5, which are stacked on a substrate 1, where an initial trigger signal line STV and a low-voltage signal line VGL are both located on the gate metal layer G, a second plate 32 of a first compensation capacitor C1 is located on the source/drain metal layer SD, and the transparent conductive layer 5 includes a first connection portion 51;
the second plate 32 of the first compensation capacitor C1 is electrically connected to one end of the first connection portion 51 through a first via hole V1 penetrating the passivation layer PVX, and the other end of the first connection portion 51 is electrically connected to the low voltage signal line VGL through a second via hole V2 penetrating the passivation layer PVX and the gate insulating layer GI. Thus, a metal wire (the second plate 32 of the first compensation capacitor C1) located on the source-drain metal layer SD is disposed above the start trigger signal line STV and is overlapped with the start trigger signal line STV in parallel, the second plate 32 of the first compensation capacitor C1 is electrically connected to the low-voltage signal line VGL through the transparent conductive layer 5 (the first connection portion 51) located above the source-drain metal layer SD, the first compensation capacitor C1 can be formed at the overlapped portion of the start trigger signal line STV and the metal wire (the second plate 32 of the first compensation capacitor C1) located on the source-drain metal layer SD, the two plates of the first compensation capacitor C1 are the start trigger signal line STV and the metal wire located on the source-drain metal layer SD, the capacitance medium is the gate insulation layer GI, and the size of the first compensation capacitor C1 can be adjusted by adjusting the length and width of the second plate 32 of the first compensation capacitor C1.
Alternatively, as shown in fig. 3, the length of the second plate 32 may be approximately the length of the start triggering signal line STV along the GOA cell arrangement direction, but is not limited specifically, for example, the length of the second plate 32 may also be smaller than the length of the start triggering signal line STV along the GOA cell arrangement direction.
In practical implementation, in the above display substrate provided in the embodiment of the present invention, as shown in fig. 5, the compensation capacitor C includes a second compensation capacitor C2, the first plate 41 of the second compensation capacitor C2 is a part of the low-voltage signal line VGL, an orthogonal projection of the second plate 42 of the second compensation capacitor C2 on the substrate base 1 overlaps an orthogonal projection of a part of the low-voltage signal line VGL on the substrate base 1, and the second plate 42 of the second compensation capacitor C2 is electrically connected to the start trigger signal line STV. In this way, the other metal film layer different from the metal film layer where the low voltage signal line VGL is located on the display substrate may be provided with a trace (i.e., the first plate 41) overlapping with the orthographic projection of the low voltage signal line VGL, and the overlapping region forms the second compensation capacitor C2, so that the second plate 42 of the second compensation capacitor C2 may be electrically connected to the start trigger signal line STV, and the second compensation capacitor C2 is equivalent to the capacitor of the start trigger signal line STV, thereby increasing the capacitor of the start trigger signal line STV and improving the ESD protection capability of the start trigger signal line STV.
In specific implementation, as shown in fig. 5 and fig. 6, in the display substrate provided in the embodiment of the present invention, fig. 6 is a schematic cross-sectional view along EE' direction in fig. 5, and includes a gate metal layer G, a gate insulating layer GI, a source/drain metal layer SD, a passivation layer PVX, and a transparent conductive layer 5, which are stacked on a substrate 1, where an initial trigger signal line STV and a low-voltage signal line VGL are both located on the gate metal layer G, a second plate 7 of a second compensation capacitor C2 is located on the source/drain metal layer SD, and the transparent conductive layer 5 includes a second connection portion 52;
the second plate 42 of the second compensation capacitor C2 is electrically connected to one end of the second connection portion 52 through a third via hole V3 penetrating the passivation layer PVX, and the other end of the second connection portion 52 is electrically connected to the start trigger signal line STV through a fourth via hole V4 penetrating the passivation layer PVX and the gate insulating layer GI. Therefore, a metal wire (the second plate 42 of the second compensation capacitor C2) located on the source-drain metal layer SD is arranged above the low-voltage signal line VGL and is overlapped with the low-voltage signal line VGL in parallel, the second plate 42 of the second compensation capacitor C2 is electrically connected with the initial trigger signal line STV through the transparent conductive layer 5 (the second connecting portion 52) located above the source-drain metal layer SD, the second compensation capacitor C2 can be formed at the overlapped position of the low-voltage signal line VGL and the metal wire (the second plate 42 of the second compensation capacitor C2) located on the source-drain metal layer SD, the two plates of the second compensation capacitor C2 are the low-voltage signal line VGL and the metal wire located on the source-drain metal layer SD, the capacitance medium is the gate insulation layer GI, and the size of the second compensation capacitor C2 can be adjusted by adjusting the length and the width of the second plate 42 of the second compensation capacitor C2.
It should be noted that, in the embodiment of the present invention, the capacitance of the start triggering signal line STV is increased by further adding a second compensation capacitor C2 on the basis of the embodiment of fig. 3, that is, the compensation capacitor C of the start triggering signal line STV in fig. 5 includes a first compensation capacitor C1 and a second compensation capacitor C2, so that a larger capacitance can be added to the start triggering signal line STV, that is, fig. 5 is a scheme of adding two compensation capacitors between the start triggering signal line STV and the low voltage signal line VGL.
Of course, it is also possible to add only the second compensation capacitor C2 shown in fig. 5 to the circuit shown in fig. 2.
In a specific implementation, as shown in fig. 7, the display substrate provided in the embodiment of the present invention further includes a test Pad group 6 (ET Pad) located on a side of a first row of GOA units of the plurality of mutually cascaded GOA units 2, which is far from a last row of GOA units, where the compensation capacitor C includes a third compensation capacitor C3, and the third compensation capacitor C3 is located between the test Pad group 6 and the first row of GOA units 2;
the first plate 71 of the third compensation capacitor C3 is a portion 8 of the low voltage signal line VGL, an orthogonal projection of the second plate 72 of the third compensation capacitor C3 on the substrate base plate 1 and an orthogonal projection of the low voltage signal line VGL on the substrate base plate 1 have an overlapping region, and the second plate 72 of the third compensation capacitor C3 is electrically connected to the start trigger signal line STV. Thus, the third compensation capacitor C3 is disposed between the ET Pad and the first row GOA unit 2, the start trigger signal line STV and the low voltage signal line VGL can be extended into the space, a metal line (i.e., the second plate 72 of the third compensation capacitor C3) overlapped with the extended portion of the low voltage signal line VGL is disposed on a metal layer different from the metal layer where the low voltage signal line VGL is disposed, and the overlapped region forms the third compensation capacitor C3, so that the capacitance of the start trigger signal line STV is increased, and the ESD resistance of the start trigger signal line STV is improved.
In specific implementation, in the display substrate provided in the embodiment of the present invention, as shown in fig. 7, a portion 8 of the low voltage signal line VGL is a portion of the low voltage signal line VGL extending toward the start trigger signal line STV. Specifically, when the low voltage signal line VGL is fabricated, a portion 8 extending from the low voltage signal line VGL may be disposed in a space between the test pad group 6 and the GOA cells 2 in the first row, and the portion 8 serves as the first plate 71 of the third compensation capacitor C3.
In specific implementation, as shown in fig. 7 and 8, in the display substrate provided in the embodiment of the present invention, fig. 8 is a schematic cross-sectional view along FF' direction in fig. 7, and includes a gate metal layer G, a gate insulating layer GI, a source-drain metal layer SD, a passivation layer PVX, and a transparent conductive layer 5, which are stacked on a substrate 1, where an initial trigger signal line STV and a low-voltage signal line VGL are both located on the gate metal layer G, a second plate 72 of a third compensation capacitor C3 is located on the source-drain metal layer SD, and the transparent conductive layer 5 includes a third connection portion 53;
the second plate 72 of the third compensation capacitor C3 is electrically connected to one end of the third connection portion 53 through a fifth via hole V5 penetrating the passivation layer PVX, and the other end of the third connection portion 53 is electrically connected to the start trigger signal line STV through a sixth via hole V6 penetrating the passivation layer PVX and the gate insulating layer GI. Thus, a third compensation capacitor C3 is arranged in the space between the test pad group 6 and the first row GOA unit 2, the second plate 72 of the third compensation capacitor C3 is electrically connected to the start trigger signal line STV through the transparent conductive layer 5 (third connection part 53) located above the source-drain metal layer SD, the third compensation capacitor C3 can be formed at the overlapping position of a part 8 of the low-voltage signal line VGL extending into the space and the metal line located in the source-drain metal layer SD (the second plate 72 of the third compensation capacitor C3), the two plates of the third compensation capacitor C3 are the low-voltage signal line VGL and the metal line located in the source-drain metal layer SD, the capacitance medium is the gate insulating layer GI, and the length and the width of the first plate 71 and the second plate 72 of the third compensation capacitor C3 can be adjusted according to the size of the space between the test pad group 6 and the first row GOA unit 2, i.e. the size of the third compensation capacitor C3 can be adjusted.
In a specific implementation, as shown in fig. 9, in the display substrate provided in the embodiment of the present invention, one end of the start trigger signal line STV is electrically connected to the first GOA unit 2 in the multiple GOA units 2 that are cascaded with each other through the first trace 10, and the other end of the start trigger signal line STV is electrically connected to the last GOA unit 2 in the multiple GOA units 2 that are cascaded with each other through the second trace 20;
the compensation capacitor C comprises a fourth compensation capacitor C4 and a fifth compensation capacitor C5;
the first trace 10 includes a first portion 11 having an overlapping region with the low voltage signal line VGL, and along the extending direction of the low voltage signal line VGL, the width of the first portion 11 is greater than the width of the rest portion in the first trace 10, the first plate 81 of the fourth compensation capacitor C4 is the first portion 11, and the second plate 82 of the fourth compensation capacitor C4 is the portion of the low voltage signal line VGL overlapping with the first portion 11;
the second trace 20 includes a second portion 21 having an overlapping region with the low voltage signal line VGL, and along the extending direction of the low voltage signal line VGL, the width of the second portion 21 is greater than the width of the rest portion in the second trace 20, the first plate 91 of the fifth compensation capacitor C5 is the second portion 21, and the second plate 82 of the fifth compensation capacitor C5 is the portion of the low voltage signal line VGL overlapping with the second portion 21. In this way, by increasing the line widths of the first trace 10 and the second trace 20 for electrically connecting the start trigger signal line STV with the GOA cell 2 at the overlapping portion with the low voltage signal line VGL to appropriately increase the capacitance of the overlapping region, the capacitance of the start trigger signal line STV can be increased, thereby achieving an increase in the ESD resistance of the start trigger signal line STV.
It should be noted that, in the embodiment of the present invention, fig. 3 only adds the first compensation capacitor C1, fig. 5 only adds the second compensation capacitor C2 on the basis of fig. 3, fig. 7 only sets the third compensation capacitor C3 in the space between the ET Pad and the first row of GOA units 2, and fig. 9 only adds the fourth compensation capacitor C4 and the fifth compensation capacitor C5 by increasing the line width of the overlapped portion, and of course, the first compensation capacitor C1, the second compensation capacitor C2, the third compensation capacitor C3, the fourth compensation capacitor C4, and the fifth compensation capacitor C5 in the embodiment of the present invention may be mutually overlapped and combined to increase the capacitance of the start trigger signal line STV to the maximum extent, so that the ESD protection capability of the start trigger signal line STV is optimal.
In practical implementation, in the display substrate provided in the embodiment of the present invention, as shown in fig. 1, 3 and 9, the low voltage signal line VGL may be located between the start trigger signal line STV and the plurality of mutually cascaded GOA cells 2.
In practical implementation, in the display substrate provided in the embodiment of the present invention, as shown in fig. 1, 5 and 7, the low voltage signal line VGL may be located between the plurality of GOA units 2 and the display area AA, which are cascaded with each other.
In practical implementation, as shown in fig. 3-9, a clock signal line (e.g., CLK, CLKB) electrically connected to the GOA unit 2 is further included, the CLK and CLKB have the same period and opposite timing, and the function of CLK and CLKB is the same as that of the prior art, and will not be described in detail here.
In specific implementation, as shown in fig. 3, fig. 5, fig. 7 and fig. 9, CLK and CLKB may be located between the start trigger signal line STV and the GOA unit 2, although fig. 3, fig. 5, fig. 7 and fig. 9 only schematically illustrate several wiring manners of STV, CLK, CLKB and VGL, which is not limited to this, and the position of VGL is set according to actual needs.
In summary, the display substrate provided in the embodiments of the present invention can improve the capacitance of the start trigger signal line STV, so as to improve the ESD resistance of the start trigger signal line STV, thereby preventing the failure problems of burning, short circuit, and the like of the start trigger signal line STV due to electrostatic discharge, and improving the yield of the display substrate.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises a display panel, wherein the display panel comprises the display substrate provided by the embodiment of the invention. The principle of the display device for solving the problems is similar to that of the display substrate, so the implementation of the display device can refer to the implementation of the display substrate, and repeated descriptions are omitted here.
In a specific implementation, the display device provided in the embodiment of the present invention may be an organic light emitting display device or a liquid crystal display device, and is not limited herein.
In a specific implementation, the display device provided in the embodiment of the present invention may be a full-screen display device, or may also be a flexible display device, and the like, which is not limited herein.
In specific implementation, the display device provided in the embodiment of the present invention may be a full-screen mobile phone as shown in fig. 10. Of course, the display device provided in the embodiment of the present invention may also be any product or component having a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
In the display substrate and the display device provided by the embodiments of the present invention, since the initial trigger signal line is located on the side farthest from the display area in the GOA circuit area BB, and the initial trigger signal line is generally electrically connected to only the first GOA unit and the last GOA unit, so that the overlapping area of the initial trigger signal line and other signal lines is small, and the parasitic capacitance of the initial trigger signal line is small, the compensation capacitor is provided, one electrode plate of the compensation capacitor is electrically connected to the initial trigger signal line, and the other electrode plate of the compensation capacitor is electrically connected to the low-voltage signal line. Therefore, the embodiment of the invention can improve the ESD resistance of the initial trigger signal line by increasing the capacitance of the initial trigger signal line, and prevent the initial trigger signal line from short-circuit failure.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (12)
1. The display substrate is characterized by comprising a substrate, wherein the substrate is provided with a display area and a GOA circuit area arranged at the periphery of the display area; the GOA circuit region includes: the GOA unit comprises a plurality of mutually cascaded GOA units, a starting trigger signal wire and a low-voltage signal wire, wherein the GOA units are arranged on the substrate, the starting trigger signal wire is electrically connected with at least one GOA unit, and the low-voltage signal wire is electrically connected with the GOA units; the initial trigger signal line and the low-voltage signal line both extend along the arrangement direction of the plurality of mutually cascaded GOA units, and the initial trigger signal line is positioned on one side, far away from the display area, of the plurality of mutually cascaded GOA units;
one pole plate of the compensation capacitor is electrically connected with the initial trigger signal line, and the other pole plate of the compensation capacitor is electrically connected with the low-voltage signal line.
2. The display substrate of claim 1, wherein the compensation capacitor comprises a first compensation capacitor, a first plate of the first compensation capacitor is a portion of the initial trigger signal line, an orthographic projection of a second plate of the first compensation capacitor on the substrate overlaps with an orthographic projection of the portion of the initial trigger signal line on the substrate, and the second plate of the first compensation capacitor is electrically connected to the low voltage signal line.
3. The display substrate according to claim 2, comprising a gate metal layer, a gate insulating layer, a source-drain metal layer, a passivation layer and a transparent conductive layer stacked on the substrate, wherein the initial trigger signal line and the low voltage signal line are both located on the gate metal layer, the second plate of the first compensation capacitor is located on the source-drain metal layer, and the transparent conductive layer comprises a first connection portion;
the second plate of the first compensation capacitor is electrically connected with one end of the first connecting portion through a first via hole penetrating through the passivation layer, and the other end of the first connecting portion is electrically connected with the low-voltage signal line through a second via hole penetrating through the passivation layer and the gate insulating layer.
4. The display substrate according to any one of claims 1 to 3, wherein the compensation capacitor includes a second compensation capacitor, a first plate of the second compensation capacitor is a portion of the low voltage signal line, an orthogonal projection of a second plate of the second compensation capacitor on the substrate overlaps an orthogonal projection of the portion of the low voltage signal line on the substrate, and a second plate of the second compensation capacitor is electrically connected to the start trigger signal line.
5. The display substrate according to claim 4, comprising a gate metal layer, a gate insulating layer, a source-drain metal layer, a passivation layer and a transparent conductive layer, wherein the gate metal layer, the gate insulating layer, the source-drain metal layer, the passivation layer and the transparent conductive layer are stacked on the substrate, the initial trigger signal line and the low-voltage signal line are both located on the gate metal layer, the second plate of the second compensation capacitor is located on the source-drain metal layer, and the transparent conductive layer comprises a second connecting portion;
and the second pole plate of the second compensation capacitor is electrically connected with one end of the second connecting part through a third via hole penetrating through the passivation layer, and the other end of the second connecting part is electrically connected with the initial trigger signal line through a fourth via hole penetrating through the passivation layer and the gate insulating layer.
6. The display substrate according to any one of claims 1-3 and 5, further comprising a testing pad set located on a side of a first row of GOA units away from a last row of GOA units in the plurality of mutually cascaded GOA units, wherein the compensation capacitor comprises a third compensation capacitor, and the third compensation capacitor is located between the testing pad set and the first row of GOA units;
the first plate of the third compensation capacitor is a part of the low-voltage signal line, an orthographic projection of the second plate of the third compensation capacitor on the substrate has an overlapping region with an orthographic projection of the low-voltage signal line on the substrate, and the second plate of the third compensation capacitor is electrically connected with the initial trigger signal line.
7. The display substrate according to claim 6, wherein a portion of the low voltage signal line is a portion of the low voltage signal line extending to a side of the start trigger signal line.
8. The display substrate according to claim 7, comprising a gate metal layer, a gate insulating layer, a source-drain metal layer, a passivation layer and a transparent conductive layer, wherein the gate metal layer, the gate insulating layer, the source-drain metal layer, the passivation layer and the transparent conductive layer are stacked on the substrate, the initial trigger signal line and the low voltage signal line are both located on the gate metal layer, the second plate of the third compensation capacitor is located on the source-drain metal layer, and the transparent conductive layer comprises a third connecting portion;
the second plate of the third compensation capacitor is electrically connected with one end of the third connecting part through a fifth via hole penetrating through the passivation layer, and the other end of the third connecting part is electrically connected with the initial trigger signal line through a sixth via hole penetrating through the passivation layer and the gate insulating layer.
9. The display substrate according to any one of claims 1 to 3, 5, 7 and 8, wherein one end of the start trigger signal line is electrically connected to a first GOA cell in the plurality of mutually cascaded GOA cells through a first trace, and the other end of the start trigger signal line is electrically connected to a last GOA cell in the plurality of mutually cascaded GOA cells through a second trace;
the compensation capacitor comprises a fourth compensation capacitor and a fifth compensation capacitor;
the first trace comprises a first part having an overlapping region with the low-voltage signal line, and along the extending direction of the low-voltage signal line, the width of the first part is greater than the width of the rest part in the first trace, the first plate of the fourth compensation capacitor is the first part, and the second plate of the fourth compensation capacitor is the part of the low-voltage signal line, which overlaps with the first part;
the second trace comprises a second part having an overlapping region with the low-voltage signal line, and the width of the second part is greater than the width of the rest part in the second trace along the extending direction of the low-voltage signal line, the first plate of the fifth compensation capacitor is the second part, and the second plate of the fifth compensation capacitor is the overlapping part of the low-voltage signal line and the second part.
10. The display substrate according to claim 9, wherein the low voltage signal line is located between the start trigger signal line and the plurality of GOA cells cascaded to each other.
11. The display substrate according to claim 9, wherein the low voltage signal line is located between the plurality of GOA cells cascaded to each other and the display area.
12. A display device comprising a display panel comprising the display substrate according to any one of claims 1 to 11.
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| CN202211366031.XA CN115881024A (en) | 2022-10-31 | 2022-10-31 | Display substrate and display device |
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| CN202211366031.XA CN115881024A (en) | 2022-10-31 | 2022-10-31 | Display substrate and display device |
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