CN115878532A - Data transmission system and data transmission method - Google Patents
Data transmission system and data transmission method Download PDFInfo
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- CN115878532A CN115878532A CN202211656062.9A CN202211656062A CN115878532A CN 115878532 A CN115878532 A CN 115878532A CN 202211656062 A CN202211656062 A CN 202211656062A CN 115878532 A CN115878532 A CN 115878532A
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Abstract
The invention provides a data transmission system, which comprises a storage unit, a plurality of algorithm units and a transmission unit, wherein the storage unit is used for storing data to be operated and operation result data; the transmission unit is connected with the storage unit and the algorithm units and is used for reading the data to be operated from the storage unit and writing the operation result data into the storage unit in a polling arbitration mode; the algorithm units are used for reading the data to be operated from the transmission unit, operating the data to be operated to obtain the operation result data, writing the operation result data into the transmission unit, and enabling the algorithm units to share one storage unit through the transmission unit. The invention also discloses a data transmission method.
Description
Technical Field
The present invention relates to the field of semiconductor chip technologies, and in particular, to a data transmission system and a data transmission method.
Background
There are multiple algorithms in an Image Signal Processor (ISP) chip, each algorithm needs an independent storage unit to store data, and the multiple independent storage units occupy a large area and are very costly.
Therefore, there is a need to provide a novel data transmission system and a data transmission method to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a data transmission system and a data transmission method, which can reduce the occupied area of a storage unit and further reduce the cost.
In order to achieve the above object, the data transmission system of the present invention comprises a storage unit, a plurality of algorithm units and a transmission unit;
the storage unit is used for storing data to be operated and operation result data; the transmission unit is connected with the storage unit and the algorithm units and is used for reading the data to be operated from the storage unit and writing the operation result data into the storage unit in a polling arbitration mode; the arithmetic unit is used for reading the data to be operated from the transmission unit, operating the data to be operated to obtain the operation result data, and writing the operation result data into the transmission unit.
The data transmission system has the advantages that: the storage unit is used for storing data to be operated and operation result data; the transmission unit is connected with the storage unit and the algorithm units and is used for reading the data to be operated from the storage unit and writing the operation result data into the storage unit in a polling arbitration mode; the algorithm units are used for reading the data to be operated from the transmission unit, operating the data to be operated to obtain the operation result data, writing the operation result data into the transmission unit, and enabling the algorithm units to share one storage unit through the transmission unit.
Optionally, the transmission unit includes a bus module and a cache module, the cache module and the storage unit are both connected to the bus module, and the cache module is connected to the plurality of algorithm units.
Optionally, the cache module includes a plurality of first caches and a plurality of second caches, the algorithm units are connected with the first caches in a one-to-one correspondence, one algorithm unit is connected with the plurality of second caches, and both the first caches and the second caches are connected with the bus module.
Optionally, only one of the first buffer and the second buffer is permitted to perform data transmission with the bus module at the same time in the polling arbitration process, and the same first buffer and the same second buffer are not continuously permitted to perform data transmission with the bus module within a preset time. The beneficial effects are that: on the premise of avoiding data overflow, the depth of the first buffer and the second buffer is reduced, and the cost is reduced.
Optionally, the first buffer is configured to buffer the operation result data, initiate a bus request to the bus module when the operation result data is not empty, and write the operation result data into the bus module after the permission of the bus module is obtained.
Optionally, the second buffer is configured to cache the data to be operated, initiate a bus request to the bus module when the second buffer is not full, and read the data to be operated from the bus module after the permission of the bus module is obtained.
Optionally, the first buffer and the second buffer are both asynchronous first-in first-out memories or asynchronous random access memories.
Optionally, a bit width of a connection side of the first buffer and the arithmetic unit is smaller than a bit width of a connection side of the first buffer and the bus module.
Optionally, a bit width of a connection side of the second buffer and the arithmetic unit is smaller than a bit width of a connection side of the second buffer and the bus module.
The invention also provides a data transmission method of the data transmission system, which comprises the following steps:
providing a data transmission system, wherein the data transmission system comprises a storage unit, a plurality of algorithm units and a transmission unit, the transmission unit is connected with the storage unit and the algorithm units, and the storage unit is used for storing data to be operated and operation result data;
the transmission unit reads the data to be operated from the storage unit and writes the operation result data into the storage unit in a polling arbitration mode;
the arithmetic unit reads the data to be operated from the transmission unit, operates the data to be operated to obtain the operation result data, and writes the operation result data into the transmission unit.
The data transmission method has the beneficial effects that: the data transmission system comprises a storage unit, a plurality of algorithm units and a transmission unit, wherein the transmission unit is connected with the storage unit and the algorithm units, the storage unit is used for storing data to be operated and operation result data, the transmission unit reads the data to be operated from the storage unit and writes the operation result data into the storage unit in a polling arbitration mode, the algorithm units read the data to be operated from the transmission unit and operate the data to be operated to obtain the operation result data, and the operation result data are written into the transmission unit to enable the algorithm units to share one storage unit through the transmission unit.
Drawings
FIG. 1 is a block diagram of a data transmission system according to some embodiments of the present invention;
FIG. 2 is a diagram illustrating a model of polling arbitration in some embodiments of the present invention;
FIG. 3 is a waveform diagram of request grant for an asynchronous FIFO memory according to some embodiments of the present invention;
fig. 4 is a flow chart of a data transmission method in some embodiments of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In view of the problems in the prior art, an embodiment of the present invention provides a data transmission system, where the data transmission system includes a storage unit, a plurality of algorithm units, and a transmission unit, the transmission unit is connected to the storage unit and the plurality of algorithm units, and the storage unit is used to store data to be operated and operation result data; the transmission unit is used for reading the data to be operated from the storage unit and writing the operation result data into the storage unit in a polling arbitration mode; the arithmetic unit is used for reading the data to be operated from the transmission unit, operating the data to be operated to obtain the operation result data, and writing the operation result data into the transmission unit.
In some embodiments, the transmission unit includes a bus module and a cache module, the cache module and the storage unit are both connected to the bus module, the cache module is connected to the algorithm units, the cache module includes a plurality of first caches and a plurality of second caches, the algorithm units are connected to the first caches in a one-to-one correspondence, one algorithm unit is connected to the second caches, and the first caches and the second caches are both connected to the bus module. Specifically, the first buffer and the second buffer are both asynchronous first-in first-out memories (FIFOs) or asynchronous random access memories (srams).
In some embodiments, the bus module includes an arbiter and at least one of an APB bus, an AHB bus, and an AXI bus.
Fig. 1 is a schematic diagram of a data transmission system according to some embodiments of the present invention. Referring to fig. 1, the data transmission system 100 includes a storage unit 101, three algorithm units, and a transmission unit 102.
Referring to fig. 1, three of the algorithm units are a first algorithm unit 1031, a second algorithm unit 1032 and a third algorithm unit 1033, respectively, where the first algorithm unit 1031 includes 1 write line and 2 read lines, the second algorithm unit 1032 includes 1 write line and 4 read lines, and the third algorithm unit 1033 includes 1 write line and 6 read lines.
Referring to fig. 1, the transmission unit 102 includes a bus module 1021 and a buffer module 1022, where the bus module includes an arbiter and an APB bus, the buffer module 1022 includes 3 first buffers 10221 and 12 second buffers 10222,3, input ends of the first buffers 10221 are respectively connected to a write line, output ends of the 3 first buffers 10221 are all connected to the bus module 1021, output ends of the 12 second buffers 10222 are respectively connected to a read line, input ends of the 12 second buffers 10222 are all connected to the bus module 1021, and the bus module 1021 is connected to the storage unit 101.
In some embodiments, a bit width of a connection side of the first buffer and the arithmetic unit is smaller than a bit width of a connection side of the first buffer and the bus module, and a bit width of a connection side of the second buffer and the arithmetic unit is smaller than a bit width of a connection side of the second buffer and the bus module.
Referring to fig. 1, the first buffer and the second buffer are all asynchronous fifo memories, a bit width of a side of the first buffer 10221 connected to the arithmetic unit is 12 bits, a bit width of a side of the first buffer 10221 connected to the bus module 1021 is 288 bits, a bit width of a side of the second buffer 10222 connected to the arithmetic unit is 12 bits, and a bit width of a side of the second buffer 10222 connected to the bus module 1021 is 288 bits.
In some embodiments, the first buffer is configured to cache the operation result data, initiate a bus request to the bus module when the operation result data is not empty, and write the operation result data into the bus module after permission of the bus module is obtained, and the second buffer is configured to cache the data to be operated, initiate a bus request to the bus module when the operation result data is not full, and read the data to be operated from the bus module after permission of the bus module is obtained. In the polling arbitration process, only one first buffer or one second buffer is permitted to transmit data with the bus module at the same time, and the same first buffer and the same second buffer are not permitted to transmit data with the bus module continuously within a preset time. The preset time is two clock cycles.
FIG. 2 is a diagram illustrating a polling arbitration model according to some embodiments of the present invention. Referring to FIG. 2, a buffer a is included 1 Buffer a 2 A buffer a 3 Buffer a 4 Buffer a 5 A buffer a 6 Buffer a 7 Buffer a 8 And a reference point a.
Referring to FIG. 2, during the round-robin arbitration, the reference point A is located in the buffer a 4 The first buffer to initiate a bus request is selected according to the round-robin arbitration direction, for example, if the round-robin arbitration direction is counterclockwise, the first buffer a 3 Buffer a, not originating bus request 2 Initiating a bus request, buffer a 2 Permission of the bus module is obtained if the buffer a 2 Writing the operation result data into the bus module if the buffer is a first buffer 2 Is the second buffer, thenAnd the bus module reads the data to be operated.
Referring to FIG. 2, in the next polling, the reference point A is changed to the buffer on the side where the bus module permission polling direction was obtained in the last polling arbitration, and taking the polling arbitration direction as the counterclockwise direction as an example, the reference point A is changed to the buffer a 1 。
FIG. 3 is a waveform diagram illustrating request grant for an asynchronous FIFO memory according to some embodiments of the present invention. Referring to fig. 3, clk denotes a clock signal, req denotes a bus request signal, sram _ cs denotes a chip select signal, and sram _ q _ out denotes read data.
Referring to fig. 3, at time t1, req changes from low to high, the asynchronous fifo initiates a bus request, at time t2, sram _ cs changes from high to low, the asynchronous fifo obtains a bus module grant, and at time t3, req changes from high to low, reads data from the bus module and stores the data. After the asynchronous FIFO memory initiates a bus request, data is written in through two clock cycles, and the asynchronous FIFO memory is fully written in the next several clock cycles.
Fig. 4 is a flow chart of a data transmission method in some embodiments of the invention. Referring to fig. 2, the data transmission method is applied to the data transmission system, and the data transmission method includes the following steps:
s0: providing a data transmission system, wherein the data transmission system comprises a storage unit, a plurality of algorithm units and a transmission unit, the transmission unit is connected with the storage unit and the algorithm units, and the storage unit is used for storing data to be operated and operation result data;
s1: the transmission unit reads the data to be operated from the storage unit and writes the operation result data into the storage unit in a polling mode;
s2: the arithmetic unit reads the data to be operated from the transmission unit, operates the data to be operated to obtain the operation result data, and writes the operation result data into the transmission unit.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to the embodiments. However, it is to be understood that such modifications and variations fall within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A data transmission system is characterized by comprising a storage unit, a plurality of algorithm units and a transmission unit;
the storage unit is used for storing data to be operated and operation result data; the transmission unit is connected with the storage unit and the algorithm units and is used for reading the data to be operated from the storage unit and writing the operation result data into the storage unit in a polling arbitration mode; the arithmetic unit is used for reading the data to be operated from the transmission unit, operating the data to be operated to obtain the operation result data, and writing the operation result data into the transmission unit.
2. The data transmission system according to claim 1, wherein the transmission unit includes a bus module and a cache module, the cache module and the storage unit are both connected to the bus module, and the cache module is connected to the plurality of algorithm units.
3. The data transmission system according to claim 2, wherein the buffer module comprises a plurality of first buffers and a plurality of second buffers, the arithmetic units are connected with the first buffers in a one-to-one correspondence, one arithmetic unit is connected with the plurality of second buffers, and the first buffers and the second buffers are both connected with the bus module.
4. The data transmission system of claim 3, wherein only one of the first buffer and the second buffer is permitted to transmit data to the bus module at a time during the polling arbitration, and the first buffer and the second buffer are not permitted to transmit data to the bus module continuously for a predetermined time.
5. The data transmission system according to claim 3, wherein the first buffer is configured to buffer the operation result data, initiate a bus request to the bus module when the operation result data is not empty, and write the operation result data into the bus module after obtaining the permission of the bus module.
6. The data transmission system according to claim 3, wherein the second buffer is configured to buffer the data to be operated, and initiate a bus request to the bus module when the second buffer is not full, and read the data to be operated from the bus module after obtaining the permission of the bus module.
7. The data transmission system of claim 3, wherein the first buffer and the second buffer are both asynchronous first-in first-out memories or asynchronous random access memories.
8. The data transmission system according to claim 3, wherein the bit width of the side of the first buffer connected to the arithmetic unit is smaller than the bit width of the side of the first buffer connected to the bus module.
9. A data transmission system according to claim 3, wherein the bit width of the side of said second buffer to which said arithmetic unit is connected is less than the bit width of the side of said second buffer to which said bus module is connected.
10. A data transmission method of a data transmission system according to any one of claims 1 to 9, comprising:
providing a data transmission system, wherein the data transmission system comprises a storage unit, a plurality of algorithm units and a transmission unit, the transmission unit is connected with the storage unit and the algorithm units, and the storage unit is used for storing data to be operated and operation result data;
the transmission unit reads the data to be operated from the storage unit and writes the operation result data into the storage unit in a polling arbitration mode;
the arithmetic unit reads the data to be operated from the transmission unit, operates the data to be operated to obtain the operation result data, and writes the operation result data into the transmission unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211656062.9A CN115878532A (en) | 2022-12-22 | 2022-12-22 | Data transmission system and data transmission method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211656062.9A CN115878532A (en) | 2022-12-22 | 2022-12-22 | Data transmission system and data transmission method |
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| CN115878532A true CN115878532A (en) | 2023-03-31 |
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| CN202211656062.9A Pending CN115878532A (en) | 2022-12-22 | 2022-12-22 | Data transmission system and data transmission method |
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