CN115866885A

CN115866885A - Circuit board and electronic equipment

Info

Publication number: CN115866885A
Application number: CN202211424751.7A
Authority: CN
Inventors: 姬忠礼; 曹权根
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2023-03-28
Also published as: WO2024103925A1

Abstract

The application provides a circuit board and electronic equipment. The circuit board comprises a first plate, a second plate and a third plate, wherein the first plate comprises a first surface and a second surface which are arranged oppositely, and the first surface is provided with a mounting groove; the second plate is embedded in the mounting groove and comprises a third surface and a fourth surface which are arranged in a back-to-back mode, the third surface is flush with the first surface, and the fourth surface is arranged at the bottom of the mounting groove; the third plate is arranged in a stacked manner with the first plate, the third plate is in contact with the second plate, the third plate comprises at least one first circuit layer, and the first circuit layer is electrically connected with the first plate; the first circuit layer is electrically connected with the second plate; wherein the transmission rate of the second board pair signal is greater than or equal to the transmission rate of the first board pair signal. The technical scheme of the application can support the transmission of signals and reduce the cost of the circuit board on the basis of adapting to the high calculation requirement of the electronic equipment.

Description

Circuit board and electronic equipment

Technical Field

The application relates to the technical field of circuit boards, in particular to a circuit board and electronic equipment.

Background

With the rise of big data, cloud computing and AI (Artificial intelligence), computing requirements of electronic devices such as servers and super computers are increasing. In order to meet the high computing requirements of electronic devices, a circuit board disposed in the electronic device may support low-speed and high-speed signal transmission by using a single board, but the use of the single board often increases the cost of the circuit board.

Disclosure of Invention

Embodiments of the present application provide a circuit board and an electronic device, which can support signal transmission and reduce the cost of the circuit board on the basis of adapting to the high computing requirements of the electronic device.

In a first aspect of the present application, a circuit board is provided, which includes: a first plate, a second plate, and a third plate;

the first plate comprises a first surface and a second surface which are arranged oppositely, and the first surface is provided with a mounting groove;

the second plate is embedded in the mounting groove and comprises a third surface and a fourth surface which are arranged oppositely, the third surface is flush with the first surface, and the fourth surface is arranged at the bottom of the mounting groove;

the third plate is arranged in a stacked manner with the first plate, the third plate is in contact with the second plate, the third plate comprises at least one first circuit layer, and the first circuit layer is electrically connected with the first plate; the first circuit layer is electrically connected with the second plate;

wherein the transmission rate of the second board pair signal is greater than or equal to the transmission rate of the first board pair signal.

It is understood that in electronic equipment, a circuit board functions to provide a connection path for transmission of signals between electronic devices. As the computing requirements of electronic devices continue to increase, the configurations of electronic devices (e.g., processors, memories, etc.) within electronic devices also continue to upgrade. In the evolution of electronic device performance, the structural arrangement of the circuit board needs to meet the working requirements of being able to support the transmission of signals such as low-speed signals and high-speed signals and to meet a large number (e.g., thousands) of I/O (Input/Output) interconnections. At present, high-speed grade plates are often adopted to support the transmission of signals such as low-speed signals and high-speed signals, and a large number of I/O interconnections are realized by increasing the circuit layer number and the wiring density of a circuit board, but the arrangement can cause the cost of the circuit board to increase. The high-speed signal may be a signal whose rising edge (or falling edge) time is less than 50ps (picosecond). Alternatively, the high speed signal may be a signal greater than 50 Mhz. Alternatively, the high speed signal may be a signal at a rate of 2.5Gbps/s (gigabits per second) or more.

Therefore, the circuit board can be made into a composite board by embedding the second plate in the first plate, the transmission rate of the second plate to signals is greater than that of the first plate to signals, the transmission speed of the second plate to signals can be increased compared with that of the first plate, and the second plate is more suitable for transmitting high-speed signals compared with the first plate. On the one hand, because the second board can be embedded in the structure of the first board, the second board can be arranged on the transmission path of the high-speed signal in the first board according to the actual transmission requirements of the signals such as the low-speed signal and the high-speed signal in the circuit board, and the arrangement position of the second board is flexible. On the other hand, because the second board inlays the structure setting of locating the first board for the second board only needs to replace the partial structure of first board just can reach high-speed signal transmission's purpose, effectively reduce all spaces of first board and all replace the required high manufacturing cost and the high technology degree of difficulty of panel that can transmit high-speed signal, reduce the processing degree of difficulty of circuit board, make the circuit board can satisfy electronic equipment mainboard size and performance demand, be favorable to making the circuit board apply to jumbo size treater interconnection and signal fan-out, the reliability is good.

And the third plate is arranged outside the first plate and the second plate, so that the second plate is wrapped by the first plate and the third plate together to form the structure of the embedded plate. And because the third plate and the first plate can jointly form the appearance surface of the circuit board, the surface of the third plate, which is far away from the first plate and the second plate, can be used as a welding surface of the circuit board to be connected with a plurality of electronic devices and signal output ends. With this arrangement, since the third board is electrically connected to the second board, high-speed signal interconnection can be realized between the electronic devices provided on the surface of the third board and/or between the electronic devices and the signal output terminals through the second board. Namely, the circuit board can realize the transmission of high-speed signals on the basis of meeting board-level process capabilities such as precision control, tolerance control and the like, and is favorable for reducing the production cost of the circuit board.

And after the second plate is installed in the installation groove, the vertical distance between the third surface of the second plate and the second surface of the first plate is equal to the vertical distance between the first surface of the first plate and the second surface of the first plate. Under this setting, the composite sheet that first board and second board constitute can have better plane degree, guarantees that each part of circuit board does not appear the position deviation, reduces the possibility that the circuit board takes place to warp and crooked to minimum.

In one possible embodiment, the second board is used to transmit high speed signals.

In one possible embodiment, the wiring density of the second board is greater than or equal to the wiring density of the first board.

Under the arrangement, the second board is a board with high-density circuit arrangement compared with the first board, so that the layer number of the second board can be reduced on the basis of realizing high-speed signal transmission, and the cost of the circuit board is further reduced.

In a possible embodiment, the second board comprises at least one second wiring layer, and the first board comprises at least two third wiring layers;

the minimum line width of the second line layer is smaller than or equal to the minimum line width of the third line layer; and/or the presence of a gas in the gas,

the minimum pitch of the second circuit layer is smaller than or equal to the minimum pitch of the third circuit layer.

Under the arrangement, the second board is more suitable for transmitting high-speed signals relative to the first board, and the circuit board can transmit the high-speed signals on the basis of low cost.

the dielectric loss of the second circuit layer is less than or equal to that of the third circuit layer; and/or the presence of a gas in the atmosphere,

the dielectric constant of the second circuit layer is less than or equal to that of the third circuit layer.

By enabling the second circuit layer of the second board and the third circuit layer of the first board to meet one or more of the above conditions, the second board can be more suitable for transmitting high-speed signals relative to the first board, and therefore the circuit board is beneficial to realizing high-speed signal transmission on the basis of low cost.

In a possible embodiment, the second board comprises at least one second wiring layer and the first board comprises at least two third wiring layers;

the roughness of the copper foil of the second circuit layer is smaller than or equal to that of the copper foil of the third circuit layer.

By enabling the second circuit layer of the second board and the third circuit layer of the first board to meet the above condition, the second board can be more suitable for transmitting high-speed signals relative to the first board, and therefore the circuit board can transmit the high-speed signals on the basis of low cost.

In a possible embodiment, the second plate is arranged separated from the first plate in a direction parallel to the first surface.

That is, in the circumferential direction around the second board, the wiring layer of the second board and the wiring layer of the first board are disconnected from each other and are not in conduction with each other. With this arrangement, the insulating arrangement of the second plate and the first plate can be achieved in the circumferential direction of the second plate. It will be appreciated that the second plate is arranged apart from the first plate in a direction parallel to the first surface of the first plate. The embedded arrangement of the first board and the embedded second board may be made substantially signal-free in a direction parallel to the first surface of the first board. Thereby reducing the cost of making interlayer signal interconnections between the first and second plates in a direction parallel to the first surface. The structure of the second board embedded into the first board is favorable for reducing the production cost of the circuit board.

In a possible embodiment, the second board is a PCB board, a carrier-like board or a carrier board.

In a possible embodiment, the first board comprises at least two third circuit layers, the third circuit layers being electrically connected to the first circuit layers.

It can be understood that the first circuit layer located at the outermost layer in the third board layer structure can be used as a soldering surface of the circuit board to connect with the aforementioned plurality of electronic devices, and since the first circuit layer is electrically connected with the third circuit layer, the circuit layers of the circuit board can be conducted with each other, so that the plurality of electronic devices can be interconnected through the circuit board.

In a possible embodiment, the orthographic projection of the third plate on the first plate at least partially overlaps the orthographic projection of the second plate on the first plate. With this arrangement, the electronic device disposed on the third board can be interconnected with the second board through the via structure (i.e., the transmission structure). Or the second plate may be directly interconnected with the electronic device.

In a second aspect of the present application, there is also provided an electronic device, including the circuit board as described above, a first processor; the third plate comprises a first connecting surface and a second connecting surface which are arranged oppositely, and the first connecting surface is contacted with the first plate and the second plate;

the first processor is arranged on the second connecting surface; and is electrically connected to the third plate.

In one possible implementation, the electronic device further includes a second processor;

the second processor is arranged on the second connecting surface; and is electrically connected to the third plate;

the first board is used for transmitting a first signal between the first processor and the second processor

The second board is used for transmitting a second signal between the first processor and the second processor;

wherein a rate of the first signal is less than a rate of the second signal.

In one possible embodiment, the circuit board has a first transmission structure and a second transmission structure which are arranged at intervals;

the first transmission structure is arranged along the thickness direction of the circuit board and electrically connected with the first processor and the second board;

the second transmission structure is arranged along the thickness direction of the circuit board, and the second transmission structure is electrically connected with the second processor and the second board.

It can be appreciated that since the first transmission structure enables electrical connection between the first processor and the second board and the second transmission structure enables electrical connection between the second processor and the second board, the first processor and the second processor can be electrically connected through the second board and the second board can transmit high-speed signals between the first processor and the second processor. Under this setting, be used for high-speed signal connection through embedded second board, on the basis of realizing the interconnection of two treater, reduce the wiring degree of difficulty of circuit board, reduce the required face area of circuit board wiring. On the basis of low cost, the problems of difficult high-density wiring and blocked high-speed signal transmission caused by adopting common plates in the prior art are solved, and the reliability is good.

In one possible implementation, the electronic device further includes a functional device disposed between the first processor and the second processor; the functional device is electrically connected with the second plate; the functional device comprises a memory, a switching chip and/or a signal enhancement chip.

In a possible implementation manner, the circuit board further has a third transmission structure, the third transmission structure is arranged at a distance from both the first transmission structure and the second transmission structure, and the third transmission structure is arranged along the thickness direction of the circuit board;

the functional device is arranged on the second connecting surface of the third plate; the third transmission structure electrically connects the functional device and the second board.

It will be appreciated that the functional device disposed between the first processor and the second processor enables signal interconnection of the first processor and the second processor, since the third transmission structure enables electrical connection between the functional device and the second board, which is capable of transmitting high speed signals between the first processor and the second processor. The signal loss during the transmission of the signal transmission link is usually less than a preset threshold (e.g., 30 db), and if the signal loss exceeds the preset threshold, the transmission quality of the signal is difficult to be ensured. Therefore, by arranging the functional device in the transmission path of the first processor and the second processor, the functional device can be used as a medium for signal interconnection of the first processor and the second processor, so that the signal transmission energy is increased, the signal attenuation is reduced, the loss in the signal transmission process is reduced, and the signal transmission quality is improved.

In a possible embodiment, the third plate has a hollowed-out area, the third plate comprising a hollowed-out area, the hollowed-out area exposing a portion of the second plate; the functional device is arranged on the third surface of the second plate and is electrically connected with the second plate.

With this arrangement, the functional device can be fixed and electrically connected to the second board, and the functional device can be directly soldered to the second board.

In one possible embodiment, the electronic device further comprises a signal output;

the signal output end is arranged on the second connecting surface and is electrically connected with the second plate;

the second board is used for transmitting high-speed signals between the first processor and the signal output end;

wherein, the high-speed signal is a signal with the rising edge or falling edge time of the signal less than 50 picoseconds.

It can be appreciated that since the first transmission structure enables electrical connection between the first processor and the second board and the second transmission structure enables electrical connection between the signal output terminal and the second board, the first processor can implement fan-out of processor signals through the second board and the second board can transmit high-speed signals between the first processor and the signal output terminal. Under this setting, be used for high-speed signal connection through embedded second board, can make the signal fan-out of the whole realization treater of circuit board, the reliability is good.

Drawings

Fig. 1 is an angular schematic structure diagram of an electronic device according to an embodiment of the present disclosure;

FIG. 2 isbase:Sub>A schematic sectional view taken along section line A-A of FIG. 1;

FIG. 3 is a cross-sectional view of a first plate of the circuit board shown in FIG. 2;

FIG. 4 is another cross-sectional schematic view of the first plate of the circuit board shown in FIG. 2;

FIG. 5 is a schematic cross-sectional view of a first plate of the circuit board shown in FIG. 2;

fig. 6 is an exploded schematic view of a part of the structure of the circuit board shown in fig. 2;

FIG. 7 is a cross-sectional view of a second plate of the circuit board shown in FIG. 2;

FIG. 8 is another cross-sectional view of the second plate of the circuit board shown in FIG. 2;

FIG. 9 is a further cross-sectional view of the second plate of the circuit board shown in FIG. 2;

FIG. 10 is a schematic cross-sectional view of a third plate of the circuit board shown in FIG. 2;

fig. 11 is another schematic cross-sectional view of a third plate of the circuit board shown in fig. 2;

fig. 12 is a schematic cross-sectional view of a third plate of the circuit board shown in fig. 2;

FIG. 13 is another schematic cross-sectional view taken along section line A-A of FIG. 1;

FIG. 14 is a cross-sectional schematic view of the circuit board of FIG. 1 in connection with an electronic device;

FIG. 15 is another cross-sectional schematic view of the circuit board of FIG. 1 coupled to an electronic device;

FIG. 16 is a schematic cross-sectional view of the circuit board of FIG. 1 in connection with an electronic device;

FIG. 17 is a schematic cross-sectional view of the circuit board of FIG. 1 in connection with an electronic device;

FIG. 18 is a cross-sectional schematic view of the circuit board of FIG. 1 connected to electronics and signal output terminals;

fig. 19 is a schematic flow chart of a method for manufacturing a circuit board according to an embodiment of the present disclosure;

fig. 20 is a state diagram illustrating a manufacturing process of the manufacturing method of the circuit board shown in fig. 19.

Detailed Description

For convenience of understanding, terms referred to in the embodiments of the present application are first explained.

And/or: only one kind of association relationship describing the associated object, indicates that there may be three kinds of relationships, for example, a and/or B, may indicate: a exists alone, A and B exist simultaneously, and B exists alone.

A plurality of: two or more than two.

Connecting: it should be understood that, for example, A and B are connected, either directly or indirectly through an intermediate.

The following description of the embodiments of the present application will be made with reference to the accompanying drawings.

The embodiment of the application provides a circuit board and electronic equipment.

The electronic device may be, but is not limited to, a server, a router, a switch, a supercomputer, an AI (Artificial intelligence) device, and the like. For convenience of understanding, the following description will use an electronic device as an example of a server, but it should be understood that the invention is not limited thereto.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an angle of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 may include a housing 210, a circuit board 100, and electronics 220.

The number of the electronic devices 220 may be multiple, the electronic devices 220 are located inside the housing 210, and the electronic devices 220 are disposed on the circuit board 100 to implement functions of data exchange or processing of the electronic device 200. Illustratively, the electronic device 220 may be, but is not limited to being, a processor, a hard drive, or a memory. Specifically, the processor may be, for example, a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), a TPU (temporal Processing Unit), or the like. The Memory may be a Dual-Inline Memory module (DIMM), such as one or more of a first generation Double Data Rate Synchronous Random Access Memory (DDR SDRAM), a second generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR 2 SDRAM), a third generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR 3 SDRAM), a fourth generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR 4 SDRAM) and a fifth generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR 5 SDRAM).

It should be noted that the number of processors may be configured as one or more as needed, and the number of memories may also be configured as one or more as needed, and the embodiments of the present application do not strictly limit the number, types, and the like of the processors and the memories.

Referring to fig. 2, fig. 2 isbase:Sub>A cross-sectional view taken alongbase:Sub>A cutting linebase:Sub>A-base:Sub>A shown in fig. 1. The circuit board 100 may include a first board 10, a second board 20, and a third board 30. The second plate 20 is embedded in the first plate 10, the third plate 30 is stacked on the first plate 10, and the third plate 30 is in contact with and electrically connected to the second plate 20. Wherein, the transmission rate of the second board 20 to the signal is greater than or equal to the transmission rate of the first board 10 to the signal.

It is understood that in the electronic apparatus 200, the circuit board 100 functions to provide a connection path for transmission of signals between the electronic devices 220. As the computing requirements of the electronic device 200 increase, the configuration of the electronic devices 220 (e.g., processors, memory, etc.) within the electronic device 200 also increases. In the evolution of the performance of the electronic device 220, the structural configuration of the circuit board 100 needs to meet the operational requirements of being able to support the transmission of signals such as low-speed signals and high-speed signals and to meet the requirements of a large number (e.g., thousands) of I/O (Input/Output) interconnects. At present, a high number of I/O interconnections are realized by increasing the number of wiring layers and wiring density of the circuit board 100 by using a high-speed grade board to support the transmission of signals such as low-speed signals, high-speed signals, etc., but the aforementioned arrangement may result in an increase in the cost of the circuit board 100. The high-speed signal may be a signal whose rising edge (or falling edge) time is less than 50ps (picosecond). Alternatively, the high speed signal may be a signal greater than 50 Mhz. Alternatively, the high speed signal may be a signal having a rate above 2.5Gbps/s (gigabits per second).

Thus, the circuit board 100 can be a composite board by embedding the second board 20 in the first board 10, and the transmission rate of the second board 20 for signals is greater than that of the first board 10, so that the transmission rate of the second board 20 for signals can be increased compared with the first board 10, and the second board 20 is more suitable for transmitting high-speed signals compared with the first board 10. On one hand, since the second board 20 can be embedded in the first board 10, the second board 20 can be laid out on the transmission path of the high-speed signal in the first board 10 according to the actual transmission requirement of the signals such as the low-speed signal and the high-speed signal in the circuit board 100, and the arrangement position of the second board 20 is flexible. On the other hand, because the second board 20 is embedded in the structure of the first board 10, the second board 20 can achieve the purpose of high-speed signal transmission only by replacing part of the structure of the first board 10, thereby effectively reducing the high manufacturing cost and the high process difficulty required by replacing all spaces of the first board 10 with plates capable of transmitting high-speed signals, reducing the processing difficulty of the circuit board 100, enabling the circuit board 100 to meet the requirements of the size and the performance of the main board of the electronic device 200, being beneficial to the circuit board 100 to be applied to interconnection of large-size processors and signal fan-out, and having good reliability.

By providing the third plate 30 on the outer side of the first plate 10 and the second plate 20, the second plate 20 can be covered by the first plate 10 and the third plate 30, and thus can be provided as a buried plate. Since the third board 30 and the first board 10 can jointly form the external surface of the circuit board 100, the surface of the third board 30 away from the first board 10 and the second board 20 can be used as a soldering surface of the circuit board 100 to connect with the plurality of electronic devices 220 and the signal output terminals. With this arrangement, since the third board 30 is electrically connected to the second board 20, it is possible to realize high-speed signal interconnection between the electronic devices 220 and/or between the electronic devices 220 and signal output terminals provided on the surface of the third board 30 through the second board 20. That is, the circuit board 100 can realize the transmission of high-speed signals on the basis of satisfying board-level process capabilities such as precision control and tolerance control, and is beneficial to reducing the production cost of the circuit board 100.

With continued reference to fig. 2, the first plate 10 may include a first surface 101 and a second surface 102 disposed opposite to each other, where the first surface 101 is a surface of the first plate 10 contacting the third plate 30, and the second surface 102 is a surface of the first plate 10 facing away from the third plate 30. The first surface 101 is concavely provided with a mounting groove 103, and the mounting groove 103 is used for mounting the second plate 20. Illustratively, the first board 10 may be a low frequency circuit board having an operating frequency of 1Ghz (gigahertz) -5 Ghz.

It should be noted that the mounting groove 103 may be disposed at a first predetermined position of the first board 10 according to the transmission requirement of the high-speed signal. For example, the first predetermined position may be between two electronic devices 220 on the circuit board 100 that need to perform high-speed signal transmission, and the first predetermined position may also be between one electronic device 220 on the circuit board 100 that needs to perform high-speed signal transmission and one signal output terminal. The size of the mounting groove 103 may be selected to fit the size of the second plate 20, and the embodiment of the present application is not limited thereto.

Referring to fig. 3, fig. 4 and fig. 5 in combination, fig. 3 is a schematic cross-sectional view of the first board 10 of the circuit board 100 shown in fig. 2, fig. 4 is a schematic cross-sectional view of the first board 10 of the circuit board 100 shown in fig. 2, and fig. 5 is a schematic cross-sectional view of the first board 10 of the circuit board 100 shown in fig. 2.

In an embodiment of the present application, the first board 10 may include at least one first dielectric layer 11 and at least two third circuit layers 12. Illustratively, the material of the first dielectric layer 11 may include a thermoplastic resin, such as Polytetrafluoroethylene (PTFE), soluble Polytetrafluoroethylene (PFA), fluorinated Ethylene Propylene (FEP), and the like, and a mixture thereof, and may also include a thermosetting resin. The third circuit layer 12 may be made of copper, such as HVLP ultra-low profile copper foil, or VLP low profile copper foil.

In one possible embodiment, as shown in fig. 3, the first board 10 may include one first dielectric layer 11 and two third circuit layers 12, the two third circuit layers 12 being respectively disposed on opposite sides of the one first dielectric layer 11, so that the first board 10 is a two-layer circuit board having two third circuit layers 12.

In another possible embodiment, as shown in fig. 4, the first board 10 may include three first dielectric layers 11 and four third circuit layers 12, wherein the three first dielectric layers 11 and the four third circuit layers 12 are alternately stacked in series in the order of one third circuit layer 12 and one first dielectric layer 11, so that the first board 10 is a four-layer circuit board having four third circuit layers 12. That is, two adjacent third wiring layers 12 are spaced apart by one first dielectric layer 11.

In still another possible embodiment, as shown in fig. 5, the first board 10 may include five first dielectric layers 11 and six third circuit layers 12, and the five first dielectric layers 11 and the six third circuit layers 12 are continuously and alternately stacked in the order of one third circuit layer 12 and one first dielectric layer 11, so that the first board 10 is a six-layer circuit board having six third circuit layers 12. That is, two adjacent third wiring layers 12 are spaced apart by one first dielectric layer 11.

Based on the above description, it should be understood that the first board 10 can be prepared as a board structure having a plurality of circuit layers (e.g., the number of circuit layers is greater than ten), and the number of the circuit layers of the first board 10 can be selected according to the practical application requirement of the circuit board 100, which is not limited in this application. In addition, the third circuit layers 12 have a conductive function, and the first dielectric layer 11 is disposed between two adjacent third circuit layers 12, so that the two adjacent third circuit layers 12 can be effectively separated from each other, and the two adjacent third circuit layers 12 can independently exert their respective functions without mutual interference, and thus, the reliability is good.

It should be noted that each third circuit layer 12 can be etched into a corresponding circuit pattern as required to have a corresponding function. For example, the third wiring layer 12 may function as a slit coupling layer. Alternatively, the third circuit layer 12 may be used as a ground layer to achieve isolation or ground protection. Alternatively, the third circuit layer 12 may be used as a power layer to enable power supply to the electronic device 220. Alternatively, the third line layer 12 may function as a control layer to control signals such as a clock signal (CLK), a Chip Select (CSB), and the like. Alternatively, the third wiring layer 12 may be used as a stripline layer to realize a function of feeding the antenna radiation element. Alternatively, the third wiring layer 12 may be used as an antenna relay layer. In other words, in the first board 10, the respective roles and the specific arrangement positions of the multiple third circuit layers 12 may be selected and arranged according to the application scenarios, and the embodiments of the present application are not limited strictly.

Referring to fig. 6, fig. 6 is an exploded view of a portion of the circuit board 100 shown in fig. 2. In embodiments of the present application, the second board 20 may be used to transfer high speed signals. The second plate 20 may be made of a common plate material, such as a 1T158 plate material or a S1000 plate material. The second Board may be a PCB (Printed Circuit Board). Alternatively, the second plate 20 may be a high speed plate, such as an M6 plate. The second board may be a Substrate like board (SLP), a Substrate (Sub). It is understood that a normal plate may be suitable for a low frequency scene less than 1Ghz, and a high speed plate may be suitable for a high frequency scene such as 5Ghz, 10Ghz, etc., and may have a lower Dielectric Constant (Dk) and a lower Dielectric loss (Df) in the high frequency scene. Under this arrangement, the circuit board 100 may not be limited to a single board, but may flexibly select various composite boards according to the actual application scenario of the circuit board 100, so as to effectively reduce the transmission loss of the circuit board 100, improve the transmission quality of the high-speed signal, and make the circuit board 100 have good reliability.

It should be noted that the number of the second boards 20 may be configured as one or more as needed, and the location of the second boards 20 may also be any location in the circuit board 100 where high-speed signal transmission is needed, such as between two electronic devices 220 that need to implement high-speed signal interconnection. The number and the actual arrangement position of the second plates 20 may be flexibly selected according to the application scene requirements of the electronic device 200, which is not strictly limited in the embodiment of the present application.

In the embodiment of the present application, the second plate 20 is mounted in the mounting groove 103 of the first plate 10. The second plate 20 may include third and

fourth surfaces

201 and 202 that are oppositely disposed. The third surface 201 of the second plate 20 may be flush with the first surface 101 of the first plate 10 and the fourth surface 202 of the second plate 20 may be flush with the bottom wall of the mounting groove 103. That is, after the second plate 20 is mounted to the mounting groove 103, a vertical distance between the third surface 201 of the second plate 20 and the second surface 102 of the first plate 10 is equal to a vertical distance between the first surface 101 of the first plate 10 and the second surface 102 of the first plate 10. With this arrangement, the composite board formed by the first board 10 and the second board 20 can have a better flatness, so that no position deviation of the components of the circuit board 100 occurs, and the possibility of deformation and bending of the circuit board 100 is reduced to a minimum. Of course, in some other embodiments, after the second board 20 is mounted to the mounting slot 103, the vertical distance between the third surface 201 of the second board 20 and the second surface 102 of the first board 10 may be greater or smaller than the vertical distance between the first surface 101 of the first board 10 and the second surface 102 of the first board 10.

In an embodiment of the present application, the second board 20 may include at least one second dielectric layer 21 and at least one second wiring layer 22. In one possible embodiment, the second circuit layer 22 may be electrically connected to the first circuit layer 32, such as via a transmission structure 40 described below to achieve interlayer signal interconnection, thereby achieving electrical connection between the second board 20 and the first board 10.

Illustratively, the material of the second dielectric layer 21 may include a thermoplastic resin, such as Polytetrafluoroethylene (PTFE), soluble Polytetrafluoroethylene (PFA), fluorinated Ethylene Propylene (FEP), and the like, and a mixture thereof, and may also include a thermosetting resin. The second circuit layer 22 may be made of copper, such as ultra-low profile copper foil (HVLP).

Illustratively, the dielectric loss of the second wiring layer 22 may be less than or equal to 0.15. The dielectric constant of the second wiring layer 22 may be less than or equal to 4.0. For example, when second board 20 is a 56G (Gbps, switching bandwidth) board, the dielectric constant of second line layer 22 may be 3.3, and the dielectric loss of second line layer 22 may be in the range of 0.002 to 0.004 (inclusive of 0.002 and 0.004). When the second board 20 is a 112G board, the dielectric constant of the second circuit layer 22 may be 3.2, and the dielectric loss of the second circuit layer 22 may be 0.002.

Referring to fig. 7, fig. 7 is a schematic cross-sectional view of the second board 20 of the circuit board 100 shown in fig. 2 according to a possible embodiment. The second board 20 may include a second dielectric layer 21 and a second wiring layer 22, and a second wiring layer 22 is provided on one side of the second dielectric layer 21, so that the second board 20 is a single-layer wiring board having a second wiring layer 22.

In another possible implementation manner, referring to fig. 8, fig. 8 is another cross-sectional view of the second board 20 of the circuit board 100 shown in fig. 2. The second board 20 may include a second dielectric layer 21 and two second circuit layers 22, and the two second circuit layers 22 are respectively disposed on two opposite sides of the second dielectric layer 21, so that the second board 20 is a double-layer circuit board having the two second circuit layers 22.

In another possible implementation, referring to fig. 9, fig. 9 is a schematic cross-sectional view of the second board 20 of the circuit board 100 shown in fig. 2. The second board 20 may include three second dielectric layers 21 and four second circuit layers 22, where the three second dielectric layers 21 and the four second circuit layers 22 are sequentially and alternately stacked in the order of one second circuit layer 22 and one second dielectric layer 21, so that the second board 20 is a four-layer circuit board having four second circuit layers 22. That is, two adjacent second wiring layers 22 are spaced apart by one second dielectric layer 21.

Based on the above description, it should be understood that the second board 20 may be prepared as a board structure having one or more circuit layers, and the number of the circuit layers of the second board 20 may be selected according to the practical application requirement of the circuit board 100, which is not strictly limited by the embodiments of the present application. In addition, the second circuit layers 22 have a conductive function, and the second dielectric layer 21 is provided between two adjacent second circuit layers 22, so that the two adjacent second circuit layers 22 can be effectively separated from each other, and the two adjacent second circuit layers 22 can independently exert their respective functions without mutual interference, and reliability is high.

In the embodiment of the present application, the wiring density of the second board 20 is greater than or equal to the wiring density of the first board 10. With such a configuration, the second board 20 is a board with high-density circuit layout compared to the first board 10, so that the number of layers of the second board 20 can be reduced on the basis of realizing high-speed signal transmission, thereby reducing the cost of the circuit board 100. And the second circuit layer 22 of the second board 20 and the third circuit layer 12 of the first board 10 may satisfy one or more of the following conditions, so that the second board 20 is more suitable for transmitting high-speed signals relative to the first board 10, thereby facilitating the circuit board 100 to realize high-speed signal transmission on the basis of low cost. The conditions are as follows:

1. the minimum line width of the second line layer 22 is less than or equal to the minimum line width of the third line layer 12.

2. The minimum pitch of the second wiring layer 22 is smaller than or equal to the minimum pitch of the third wiring layer 12.

3. The dielectric loss of the second wiring layer 22 is less than or equal to the dielectric loss of the third wiring layer 12.

4. The dielectric constant of the second wiring layer 22 is less than or equal to the dielectric constant of the third wiring layer 12.

5. The roughness of the copper foil of the second circuit layer 22 is less than or equal to the roughness of the copper foil of the third circuit layer 12.

It will be appreciated that the second board 20 made from different boards will have different line layer line densities and dielectric layer dielectric thicknesses, and the specific application of the second board 20 will be described in three different embodiments as follows.

In one possible embodiment, the minimum line width of the second line layer 22 may be in the range of 50um-100um (inclusive of 50um and 100 um). With this arrangement, the second board 20 can be made of a common PCB board. Illustratively, the minimum thickness of the second dielectric layer 21 may be 50um.

In another possible embodiment, the minimum line width of the second line layer 22 may be in the range of 15um-40um (inclusive of 15um and 40 um). With this arrangement, the second board 20 can be prepared as a similar carrier board. Illustratively, the minimum thickness of the second dielectric layer 21 may be 30um.

In yet another possible embodiment, the minimum line width of the second line layer 22 is in the range of 2um-10um (inclusive of 2um and 10 um). With this arrangement, the second board 20 can be prepared as a carrier board. Illustratively, the minimum thickness of the second dielectric layer 21 may be 15um.

Based on the above description, it should be understood that the plate material of the second board 20 has various application modes, and the plate material of the second board 20 can be flexibly selected according to different application scenarios, so that a high-speed application scenario of the circuit board 100 is realized on the basis of lower cost, and reliability is good.

Due to the skin effect of current transmission caused by the high-frequency characteristic of the high-speed signal, the current is concentrated on the second circuit layer 22 on the surface layer of the second board 20, so that the current transmission is based on the second circuit layer 22 on the surface layer of the second board 20, and the lower the surface roughness of the copper foil used in the second circuit layer 22, the smaller the transmission loss of the high-speed signal is, so that it is very important to select different copper foil roughness according to different application scenarios. The surface roughness refers to the small pitch and the unevenness of minute peaks and valleys on the processed surface. The distance (wave distance) between two wave crests or two wave troughs is very small, belonging to microscopic geometrical shape errors.

In one possible embodiment, the second board 20 can be prepared by using a high-speed board (e.g., a carrier board, a carrier-like board), and the surface roughness of the second circuit layer 22 is less than or equal to 5um. Therefore, the second circuit layer 22 with the surface roughness satisfying the range can have lower copper foil roughness, can effectively improve the conductor loss under the high-frequency band, and the loss is improved more obviously at the high-frequency band, which is beneficial to reducing the overall transmission line loss of the circuit board 100.

In another possible embodiment, the second board 20 may be made of a low-speed board (e.g., PCB), and the surface roughness of the second circuit layer 22 may be greater than 5um.

In the embodiment of the application, since the second board 20 is a structure embedded in the first board 10, the second board 20 is a small board with a smaller board surface area compared with the first board 10, and the second board 20 can also be used for transmitting high-speed signals, so that the second board 20 can be locally compounded on the first board 10, and part of the low-speed board can be replaced by the high-speed board on the basis that the low-speed board is still generally adopted, thereby breaking through the transmission performance limitation caused by the circuit board 100 adopting a single board in the prior art, so that the circuit board 100 as a whole can realize the function of the circuit board 100 for transmitting high-speed signals on the basis of having lower cost. Illustratively, the length of the second panel 20 may be in the range of 30mm-200mm (inclusive of 30mm and 200 mm), and the width of the second panel 20 may be in the range of 30mm-100mm (inclusive of 30mm and 100 mm).

In a possible embodiment, the second plate 20 is arranged separated from the first plate 10 in a direction parallel to the first surface 101 of the first plate 10.

That is, in the circumferential direction around the second board 20, the second line layer 22 of the second board 20 and the third line layer 12 of the first board 10 are disconnected from each other and are not in conduction with each other. With this arrangement, the insulating arrangement of the second plate 20 from the first plate 10 can be achieved in the circumferential direction of the second plate 20. It will be appreciated that the second plate 20 is provided separately from the first plate 10 in a direction parallel to the first surface 101 of the first plate 10. It is possible to have a substantially signal-free connection between the embedded first board 10 and the embedded second board 20 in a direction parallel to the first surface 101 of the first board 10. Therefore, the cost caused by interlayer signal interconnection in the direction parallel to the first surface 101 between the first board 10 and the second board 20 is reduced, and the production cost of the circuit board 100 is reduced on the basis of realizing the structural arrangement that the second board 20 is embedded into the first board 10.

Referring to fig. 2 again, the third plate 30 is disposed on the first surface 101 of the first plate 10, and the third plate 30 covers the second plate 20 and contacts the third surface 201 of the second plate 20. Specifically, the third board 30 may include a first connection face 301 and a second connection face 302 which are disposed opposite to each other, the first connection face 301 is in contact with the first board 10 and the second board 20, the second connection face 302 is away from the first board 10 and the second board 20, and the second connection face 302 is used for the electronic device 220 to be disposed thereon.

The third board 30 may include at least one third dielectric layer 31 and at least one first line layer 32, and the first line layer 32 is electrically connected to both the second line layer 22 and the third line layer 12 to electrically connect the third board 30 and the second board 20 and the third board 30 and the first board 10. Illustratively, the material of the third dielectric layer 31 may include a thermoplastic resin, such as Polytetrafluoroethylene (PTFE), soluble Polytetrafluoroethylene (PFA), fluorinated Ethylene Propylene (FEP), and the like, and a mixture thereof, and may also include a thermosetting resin. The material of the first circuit layer 32 may be copper, such as ultra-low profile copper foil (HVLP).

Referring to fig. 10, fig. 10 is a schematic cross-sectional view of the third plate 30 of the circuit board 100 shown in fig. 2. The third board 30 may include a third dielectric layer 31 and a first circuit layer 32, the third dielectric layer 31 may be disposed on the first surface 101 of the first board 10, and the first circuit layer 32 may be disposed on a side of the third dielectric layer 31 away from the first board 10, so that the third board 30 has a single-layer circuit structure with the first circuit layer 32.

In another possible implementation manner, referring to fig. 11, fig. 11 is another schematic cross-sectional view of the third plate 30 of the circuit board 100 shown in fig. 2. The third board 30 may include one third dielectric layer 31 and two first line layers 32, and the two first line layers 32 are respectively disposed at opposite sides of the one third dielectric layer 31, so that the third board 30 has a dual-layer line structure having the two first line layers 32.

Referring to fig. 12, fig. 12 is a schematic cross-sectional view of a third board 30 of the circuit board 100 shown in fig. 2. The third plate 30 may include three third dielectric layers 31 and four first wiring layers 32, and the three third dielectric layers 31 and the four first wiring layers 32 are sequentially and alternately stacked in the order of one first wiring layer 32 and one third dielectric layer 31, so that the third plate 30 has a four-layer wiring structure having four first wiring layers 32. That is, two adjacent first wiring layers 32 are spaced apart by one third dielectric layer 31.

In the embodiment of the present application, the first circuit layer 32 located at the outermost layer in the layer structure of the third plate 30 may be used as a soldering surface of the circuit board 100 to connect with the plurality of electronic devices 220, and since the first circuit layer 32 is electrically connected with the second circuit layer 22 and the third circuit layer 12, the circuit layers of the circuit board 100 can be conducted with each other, so that the plurality of electronic devices 220 can be interconnected through the circuit board 100.

In one possible embodiment, referring again to fig. 2, the orthographic projection of the third plate 30 on the first plate 10 overlaps the orthographic projection of the second plate 20 on the first plate 10. That is, the third plate 30 completely covers the second plate 20. In this arrangement, the electronic device 220 disposed on the third board 30 needs to be indirectly interconnected with the second board 20 through a via structure (i.e., a transmission structure 40 described later).

In another possible embodiment, referring to fig. 13, fig. 13 is another schematic cross-sectional view taken along the sectional linebase:Sub>A-base:Sub>A shown in fig. 1. The third plate 30 has a hollowed-out area 33, and the hollowed-out area 33 exposes a portion of the second plate 20. That is, the third plate 30 only partially covers the second plate 20. With this configuration, the hollow area 33 formed in the third plate 30 can expose the second circuit layer 22 on the surface layer of the second plate 20, so that at least a portion of the electronic device 220 can be located in the hollow area 33, and the second plate 20 and the electronic device 220 can be directly interconnected.

Referring to fig. 14, fig. 14 is a schematic cross-sectional view illustrating connection between the circuit board 100 and the electronic device 220 shown in fig. 1. In the embodiment of the present application, the circuit board 100 has the transmission structure 40, the transmission structure 40 is disposed along the thickness direction of the circuit board, and the transmission structure 40 electrically connects the third board 30 and the second board 20, or the transmission structure 40 electrically connects the third board 30, the first board 10 and the second board 20. The transmission structure 40 may be a metalized via (i.e., an electrical connection structure formed by electroplating metal (e.g., copper) on the inner wall of the via), or may be a metal pillar.

It should be noted that the specific length of the transmission structure 40 may be selected according to the actual interlayer line connection requirement in the circuit board 100, and the transmission structure 40 may also penetrate through the third board 30 and not penetrate through the second board 20, or the transmission structure 40 may penetrate through the third board 30 and the second board 20 and not penetrate through the first board 10. The embodiments of the present application are not strictly limited thereto. Exemplarily, the transmission structure 40 may extend from the third plate 30 to the second plate 20, the transmission structure 40 electrically connecting the third plate 30 and the second plate 20. Alternatively, the transmission structure 40 may extend to the first board 10 after passing through the third board 30 and the second board 20 in sequence, and the transmission structure 40 electrically connects the third board 30, the first board 10 and the second board 20.

The transmission structure 40 penetrating through the third plate 30 and the second plate 20 will be described as an example, but it should be understood that the invention is not limited thereto.

Referring to fig. 14, the transmission structure 40 extends from the surface of the third plate 30 facing away from the first plate 10 to the surface of the second plate 20 facing away from the third plate 30. I.e. the transmission structure 40 extends from the second connection face 302 of the third plate 30 to the fourth surface 202 of the second plate 20, the transmission structure 40 electrically connects the third plate 30 and the second plate 20. It will be appreciated that the transmission structure 40 is a blind via structure, which may be disposed at a second predetermined location of the circuit board 100, such as between the second board 20 and the electronic device 220 to be electrically connected to the second board 20, as desired. The transmission structure 40 can connect the first line layer 32 and the second line layer 22 of the third board 30 and the second board 20 that need to be interconnected, thereby achieving the interconnection requirements of the transmission structure 40. Illustratively, the transmission structure 40 may be an intra-metallized via that extends through all of the first line layers 32 in the third board 30 and all of the second line layers 22 in the second board 20.

It should be noted that the number of the transmission structures 40 can be configured as one or more according to the preparation requirement of the circuit board 100. While different transport structures 40 may be present in the same line layer, for example, two transport structures 40 may be present in the same line layer, wherein one transport structure 40 may enable interconnection between two adjacent line layers, and another transport structure 40 may enable interconnection between three adjacent line layers. In addition, the transmission structure 40 may be used to implement interconnections between adjacent line layers, and the transmission structure 40 may also be used to implement interconnections between non-adjacent line layers. The number, the arrangement position, the specific interconnection requirement, and the like of the transmission structures 40 may be selected according to the actual application requirement of the circuit board 100, which is not strictly limited in the embodiments of the present application.

In the embodiment of the present application, the circuit board 100 may be used to implement transmission of a high-speed signal between the electronic device 220 and the electronic device 220, and the circuit board 100 may also be used to implement transmission of a high-speed signal between the electronic device 220 and a signal output end, where the transmission scenario of the circuit board 100 is described in detail through three different application scenarios as follows.

In a first possible application scenario, referring to fig. 14, the plurality of electronic devices 220 may include a first processor 230 and a second processor 240. The first board 10 may be used to transmit a first signal between the first processor 230 and the second processor 240, and the second board 20 may be used to transmit a second signal between the first processor 230 and the second processor 240; wherein the rate of the first signal is less than the rate of the second signal. Illustratively, the first signal may be a low speed signal and the second signal may be a high speed signal.

Specifically, the first processor 230 may include a first solder ball 2301, and the first solder ball 2301 is an outlet pin of the first processor 230. The first processor 230 is connected to the second connection face 302 of the third plate 30 through the first solder balls 2301, and in this arrangement, the first processor 230 may be fixed and electrically connected to the third plate 30. The second processor 240 may include a second solder ball 2401, and the second solder ball 2401 is an outlet pin of the second processor 240. The second processor 240 is connected to the second surface 102 of the third plate 30 through the second solder balls 2401, and in this arrangement, the second processor 240 may be fixed and electrically connected to the third plate 30. The second processor 240 is spaced apart from the first processor 230.

It should be noted that the number of the first solder balls 2301 and the second solder balls 2401 may be multiple, and the specific number may be selected according to an actual application scenario, which is not limited in this embodiment of the application.

In this application scenario, the transmission structure 40 may include a first transmission structure 41 and a second transmission structure 42 that are arranged at intervals. The number of the first transmission structures 41 may be multiple, each of the first transmission structures 41 is used for electrically connecting to one of the first solder balls 2301, each of the first transmission structures 41 is disposed along the thickness direction of the circuit board 100, and each of the first transmission structures 41 extends from the third board 30 to the second board 20. Illustratively, each first transmission structure 41 extends from the second connection face 302 of the third plate 30 to the fourth surface 202 of the second plate 20, i.e. each first transmission structure 41 extends through the third plate 30 and the second plate 20. The first transmission structure 41 electrically connects the first processor 230 and the second board 20. The number of the second transmission structures 42 may be multiple, each of the second transmission structures 42 is used for electrically connecting with one of the second solder balls 2401, each of the second transmission structures 42 is disposed along the thickness direction of the circuit board 100, and each of the second transmission structures 42 extends from the third board 30 to the second board 20. Each second transmission structure 42 illustratively extends from the second connection face 302 of the third plate 30 to the fourth surface 202 of the second plate 20, i.e., each second transmission structure 42 extends through the third plate 30 and the second plate 20. The second transmission structure 42 electrically connects the second processor 240 and the second board 20.

It is understood that, since the first transmission structure 41 can realize the electrical connection between the first processor 230 and the second board 20 and the second transmission structure 42 can realize the electrical connection between the second processor 240 and the second board 20, the first processor 230 and the second processor 240 can realize the electrical connection through the second board 20 and the second board 20 can transmit high-speed signals between the first processor 230 and the second processor 240. With this arrangement, the embedded second board 20 is used for high-speed signal connection, so that the wiring difficulty of the circuit board 100 is reduced and the area of the board surface required for wiring the circuit board 100 is reduced on the basis of realizing interconnection of the two processors. And on the basis of low cost, high-density wiring and high-speed signal transmission are realized, and the reliability of high-speed signal transmission is improved.

Based on the above description, it should be understood that the circuit board 100 can function to realize the interconnection of the first processor 230 and the second processor 240 in the present application scenario.

In a second possible application scenario, please refer to fig. 15, 16 and 17 in combination, in which fig. 15 is another schematic cross-sectional view of the connection between the circuit board 100 and the electronic device 220 shown in fig. 1, fig. 16 is another schematic cross-sectional view of the connection between the circuit board 100 and the electronic device 220 shown in fig. 1, and fig. 17 is another schematic cross-sectional view of the connection between the circuit board 100 and the electronic device 220 shown in fig. 1.

In this application scenario, the same content as the first possible application scenario is not repeated, and different from the first possible application scenario, the electronic device 220 may further include a functional device, and the functional device may include the functional chip 250 and/or the memory 260.

In one possible implementation, as shown in fig. 15, the functional device may include a functional chip 250, where the functional chip 250 is disposed apart from both the first processor 230 and the second processor 240, and the functional chip 250 is located between the first processor 230 and the second processor 240. Illustratively, the functional chip 250 may include a Switch chip (e.g., switch chip) and a signal enhancement chip (e.g., retimer chip and Redriver chip for signal enhancement amplification and signal attenuation avoidance).

The functional chip 250 may include a third solder ball 2501, and the third solder ball 2501 is an outlet pin of the functional chip 250. The functional chip 250 is connected to the second connection face 302 of the third plate 30 via third solder balls 2501, and in this arrangement, the functional chip 250 can be fixed and electrically connected to the third plate 30. The transfer structure 40 may further include a third transfer structure 43, the third transfer structure 43 being spaced apart from both the first transfer structure 41 and the second transfer structure 42, the third transfer structure 43 being located between the first transfer structure 41 and the second transfer structure 42. The number of the third transmission structures 43 may be plural, each of the third transmission structures 43 is used for electrically connecting with one of the third solder balls 2501, each of the third transmission structures 43 is disposed along the thickness direction of the circuit board 100, and each of the third transmission structures 43 extends from the third board 30 to the second board 20. Illustratively, each third transmission structure 43 extends from the second connection face 302 of the third plate 30 to the fourth surface 202 of the second plate 20, i.e. each third transmission structure 43 extends through the third plate 30 and the second plate 20. The third transmission structure 43 electrically connects the functional chip 250 and the second board 20.

It is understood that the functional chip 250 disposed between the first processor 230 and the second processor 240 enables signal interconnection of the first processor 230 and the second processor 240, since the third transmission structure 43 enables electrical connection between the functional chip 250 and the second board 20, and the second board 20 enables transmission of high-speed signals between the first processor 230 and the second processor 240. The signal loss during the transmission of the signal transmission link is usually less than a preset threshold (e.g., 30 db), and if the signal loss exceeds the preset threshold, the transmission quality of the signal is difficult to be ensured. Therefore, by arranging the functional chip 250 in the transmission path between the first processor 230 and the second processor 240, the functional chip 250 can be used as a medium for signal interconnection between the first processor 230 and the second processor 240, so that signal transmission energy is increased, signal attenuation is reduced, loss in the signal transmission process is reduced, and signal transmission quality is improved.

It should be noted that at least a portion of the orthographic projection of the first processor 230 on the first board 10 may fall within the orthographic projection range of the second board 20 on the first board 10, so that the first processor 230 and the second board 20 have an overlapping portion in the thickness direction of the circuit board 100. The orthographic projection of the first processor 230 on the first board 10 may not fall within the orthographic projection range of the second board 20 on the first board 10, so that the first processor 230 and the second board 20 do not have an overlapping portion in the thickness direction of the circuit board 100. At least a portion of the orthographic projection of the second processor 240 on the first board 10 may fall within a range of the orthographic projection of the second board 20 on the first board 10, so that the second processor 240 and the second board 20 have an overlapping portion in the thickness direction of the circuit board 100. The orthogonal projection of the second processor 240 on the first board 10 may not fall within the orthogonal projection range of the second board 20 on the first board 10, so that the second processor 240 and the second board 20 do not have an overlapping portion in the thickness direction of the circuit board 100. The embodiments of the present application are not strictly limited thereto.

In another possible embodiment, as shown in fig. 16, the same contents as those in the first embodiment are not repeated, and different from the first embodiment, the circuit board 100 does not have the third transmission structure 43, the third plate 30 has a hollow area 33, the hollow area 33 exposes a portion of the second plate 20, and the functional chip 250 is located in the hollow area 33 and electrically connected to the second plate 20. Specifically, the functional chip 250 is connected to the third surface 201 of the second board 20 through the third solder balls 2501, and in this configuration, the functional chip 250 can be fixed and electrically connected to the second board 20, and the functional chip 250 can be directly soldered to the second board 20.

In yet another possible implementation, as shown in fig. 17, the same contents as those in the first implementation are not repeated, and different from the first implementation, the functional device may include a memory 260, where the memory 260 is disposed at an interval with both the first processor 230 and the second processor 240, and the memory 260 is located between the first processor 230 and the second processor 240.

The transfer structure 40 may further include a third transfer structure 43, the third transfer structure 43 being spaced apart from both the first transfer structure 41 and the second transfer structure 42, the third transfer structure 43 being located between the first transfer structure 41 and the second transfer structure 42. The number of the third transmission structures 43 may be multiple, each third transmission structure 43 is used to electrically connect with one pin of the memory 260, and each third transmission structure 43 extends from the second connection surface 302 of the third board 30 to the fourth surface 202 of the second board 20, that is, each third transmission structure 43 penetrates through the third board 30 and the second board 20. The third transmission structure 43 electrically connects the memory 260 and the second board 20. With this arrangement, the memory 260 can be placed more flexibly, and high-speed signal transmission between the memory 260 and the circuit board 100 can be realized, which is highly reliable.

Based on the above description, it should be understood that in the present application scenario, the second board 20 can play a role in improving signal transmission quality and the like for the interconnection of the first processor 230 and the second processor 240.

In a third possible application scenario, referring to fig. 18, fig. 18 is a schematic cross-sectional view of the circuit board 100 shown in fig. 1, connected to the electronic device 220 and the signal output terminal 270.

In this application scenario, the same content as the first possible application scenario is not repeated, and different from the first possible application scenario, the electronic device 200 further includes a signal output end 270, and the signal output end 270 may be configured as one or more signal output ends as needed. Illustratively, the signal output 270 may be a PCIe (Peripheral Component Interconnect Express) interface. Each of the second transmission structures 42 is configured to be electrically connected to one pin of the signal output end 270, and each of the second transmission structures 42 extends from the second connection surface 302 of the third board 30 to the fourth surface 202 of the second board 20, that is, each of the second transmission structures 42 extends through the third board 30 and the second board 20. The second transmission structure 42 electrically connects the signal output terminal 270 and the second board 20.

It is understood that, since the first transmission structure 41 can realize the electrical connection between the first processor 230 and the second board 20, and the second transmission structure 42 can realize the electrical connection between the signal output terminal 270 and the second board 20, the first processor 230 can realize the fan-out of the processor signal through the second board 20, and the second board 20 can transmit the high-speed signal between the first processor 230 and the signal output terminal 270. With this arrangement, the embedded second board 20 is used for high-speed signal connection, so that the signal fan-out of the processor can be realized on the whole circuit board 100, and the reliability is high.

Based on the above description, it should be appreciated that in the context of the present application, circuit board 100 is capable of functioning to implement fan-out of processor signals.

Referring to fig. 19 and 20 in combination, fig. 19 is a schematic flow chart of a method for manufacturing the circuit board 100 according to an embodiment of the present disclosure, and fig. 20 is a schematic state diagram of a manufacturing process of the method for manufacturing the circuit board 100 shown in fig. 19. Embodiments of the present application further provide a method for manufacturing the circuit board 100, and reference may be made to fig. 1 to 18 and the foregoing description for specific structures of the circuit board 100 involved in the manufacturing method, which are not repeated herein. In addition, the circuit board 100 shown in fig. 1 to 18 is further described hereinafter as an example, and these descriptions can be applied to the circuit board 100 shown in fig. 1 to 18 without conflict.

The method for manufacturing the circuit board 100 may include at least steps S100, S200, S300, S400, S500, and S600, which are described in detail as follows:

s100: a first plate 10 is provided.

S200: a mounting groove 103 is formed on the first plate 10.

S300: the second plate 20 is fitted into the fitting groove 103 of the first plate 10.

S400: a third plate 30 covering the first plate 10 and the second plate 20 is formed on the first plate 10 and the second plate 20.

S500: a through-hole 50 is formed through the third plate 30 and the second plate 20.

S600: the through holes 50 are metallized and plated to form the transmission structures 40 through the third plate 30 and the second plate 20.

The metallization of the through hole 50 includes copper metallization, a black hole or a shadow, and copper may be electroplated in the through hole 50 to achieve the electrical connection function of the transmission structure 40.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A circuit board, comprising: a first plate, a second plate, and a third plate;

wherein the transmission rate of the second board to the signal is greater than or equal to the transmission rate of the first board to the signal.

2. The circuit board of claim 1, wherein the second board has a wiring density greater than or equal to the wiring density of the first board.

3. The circuit board of claim 1 or 2, wherein the second board comprises at least one second wiring layer, and the first board comprises at least two third wiring layers;

the minimum line distance of the second line layer is smaller than or equal to the minimum line distance of the third line layer.

4. The circuit board of any of claims 1-3, wherein the second board comprises at least one second wire layer, and the first board comprises at least two third wire layers;

the dielectric loss of the second circuit layer is less than or equal to that of the third circuit layer; and/or the presence of a gas in the gas,

5. The circuit board of any of claims 1-4, wherein the second board comprises at least one second wire layer, and the first board comprises at least two third wire layers;

6. The circuit board of any of claims 1-5, wherein the first board is a PCB board; the second board is a PCB board, a similar carrier board or a carrier board.

7. A circuit board according to any one of claims 1-6, characterized in that the orthographic projection of the third plate on the first plate at least partly covers the orthographic projection of the second plate on the first plate.

8. The circuit board according to any one of claims 1 to 7, wherein the second board is disposed apart from the first board in the direction of the first surface.

9. An electronic device, characterized in that the electronic device comprises a circuit board according to any of claims 1-8, a first processor; the third plate comprises a first connecting surface and a second connecting surface which are arranged oppositely, and the first connecting surface is contacted with the first plate and the second plate;

10. The electronic device of claim 9, wherein the electronic device further comprises a second processor;

wherein a rate of the first signal is less than a rate of the second signal.

11. The electronic device of claim 10, wherein the circuit board includes first and second transmission structures spaced apart;

12. The electronic device of claim 10, wherein the electronic device further comprises a functional device;

the functional device is arranged between the first processor and the second processor; the functional device is electrically connected with the second plate; the functional device comprises a memory, a switching chip and/or a signal enhancement chip.

13. The electronic device of claim 12, wherein the circuit board further comprises a third transmission structure disposed in a thickness direction of the circuit board;

14. The electronic device according to claim 12, wherein the third plate includes a hollowed-out region that exposes a portion of the second plate; the functional device is arranged on the third surface of the second plate and is electrically connected with the second plate.

15. The electronic device of any of claims 9-14, wherein the electronic device further comprises a signal output;

the signal output end is arranged on the second connecting surface and is electrically connected with the second board;

wherein, the high-speed signal is a signal with the rising edge or falling edge time less than 50 picoseconds.