CN115865755A - Parallel data calibration method for interconnection among networks on multiple chips and electronic equipment - Google Patents
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Abstract
The invention discloses a parallel data calibration method for interconnection among networks on multiple chips and electronic equipment. The method firstly adjusts the delay coefficient of the clock channel, finds a state which can enable most data channels to be correctly sampled, and then respectively adjusts the delay coefficient of each data channel. And if all the data channels cannot be correctly sampled in the clock channel delay state, returning to adjust the clock channel delay coefficient. The invention can achieve the aim that each data channel can be aligned with the clock channel by self-adaptively and dynamically adjusting the delay coefficients of the clock and the data channels, thereby ensuring the correct transmission of the interconnected parallel data among the networks on a plurality of chips.
Description
Technical Field
The invention relates to the field of network on chip, in particular to a parallel data calibration method and electronic equipment for interconnection among multiple networks on chip.
Background
As more and more processor cores are integrated On a single Chip, a Network On Chip (NoC) has become a mainstream communication structure of a System On Chip (SoC) due to its high bandwidth, good flexibility and expandability. In the context of high performance computing and big data applications, system architects are constantly required to integrate more cores, accelerators, and memory within a given power range. As the development of integrated circuit technology enters the aftermolarity, the limitations of electronics and physics make the continuous scaling and upgrading of advanced semiconductor processes more and more difficult. The solution of continuously realizing a large-scale system by a single chip inevitably faces the problems of greatly reduced yield, sharply increased design and mask costs, and the like.
The scheme of changing the traditional single chip design scheme into a multi-chip design scheme and utilizing a high-speed interface for interconnection or utilizing an advanced packaging process for integration becomes a better choice. The interconnection of multiple networks across chips is attracting high attention in the research field and industry as a basic but important communication mode for multi-chip/multi-chip integration. However, because a clock skew (time skew) is introduced to the PCB wiring and the inter-chip interface, there are problems of phase drift and incomplete high-low level duty cycle during the cross-chip transmission of parallel data, which may cause sampling errors of inter-chip transmission data by a downstream chip, and further cause data packet errors and even loss.
Aiming at the problem that transmission errors are caused by time sequence differences of parallel data, the aim that each data channel can be aligned with a clock channel is achieved by adjusting channel delay. The traditional method has the advantages that the delay coefficient is manually adjusted, and the delay coefficient of each channel is repeatedly corrected after the sampling result of each channel is observed through continuous tests until the parallel data sampling is completely correct, so that time and labor are consumed. There have also been studies that propose to adjust the channel delay coefficients using an auto-calibration algorithm, but this algorithm is only for data channels and the calibratable range is very limited. Therefore, it is necessary to design a method for dynamically and adaptively adjusting the delay coefficients of the clock and the data channel at the same time, so as to maximize the calibration capability.
Disclosure of Invention
Aiming at the defects in the prior art, the parallel data calibration method and the electronic equipment for interconnection among networks on a plurality of chips solve the problem that the prior art cannot simultaneously adjust the delay coefficients of a clock channel and a data channel.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
the parallel data calibration method for interconnection among networks on multiple chips is provided, and comprises the following steps:
s1, setting a convergence threshold interval, and setting initial delay coefficient values of a clock channel and each data channel; wherein the initial interval of the convergence threshold interval is [0, m);
s2, judging whether the left endpoint value of the current convergence threshold interval is less than or equal to the total number of the data channels, and if so, entering the step S3; otherwise, judging that the calibration cannot be successful;
s3, judging whether the number of the data channels which are not aligned currently meets the current convergence threshold interval or not, and if so, entering a step S4; otherwise, entering step S5;
s4, adjusting the delay coefficient value of each data channel under the current clock channel delay coefficient value, judging whether all the data channels can be correctly sampled or not, and if so, entering the step S6; otherwise, recovering the initial delay coefficient value of the data channel and entering the step S5;
s5, judging whether all the delay coefficient values of the clock channel in the current convergence threshold interval are traversed or not, if so, increasing m to both end point values of the current convergence threshold interval, recovering the initial delay coefficient value of the clock channel, and returning to the step S2; otherwise, selecting the clock channel delay coefficient value which is not traversed under the current convergence threshold interval, and returning to the step S3;
and S6, respectively acquiring the delay coefficient values corresponding to the current clock channel and the data channel to finish calibration.
Furthermore, the selectable delay coefficient interval of the clock channel is the same as the selectable delay coefficient interval of the data channel; the initial delay coefficient value of the clock channel is the upper limit value of the selectable delay coefficient interval; the initial delay coefficient value of the data channel is the intermediate value of the selectable delay coefficient interval, and the expression is as follows:
wherein a is an initial delay coefficient value of the data channel; a is max The time delay coefficient interval is the upper limit value of the selectable time delay coefficient interval of the data channel; a is min The time delay coefficient is the lower limit value of the selectable time delay coefficient interval of the data channel; [. The]Representing an integer fetch operation.
Further, the specific method for adjusting the delay coefficient value of each data channel under the current clock channel delay coefficient value in step S4 is as follows:
and traversing the delay coefficient value of each data channel in the selectable delay coefficient interval under the current clock channel delay coefficient value.
Further, the specific method for selecting the clock channel delay coefficient value which is not traversed under the current convergence threshold interval in step S5 is as follows:
subtracting 1 from the current clock channel delay coefficient value, and when the clock channel delay coefficient value after subtracting 1 is smaller than the lower limit of the selectable delay coefficient of the clock channel, judging that all the delay coefficient values of the clock channel under the current convergence threshold interval have been traversed; otherwise, judging that the traversal is not completed.
Further, the specific method for acquiring the delay coefficient value corresponding to the current data channel in step S6 is as follows:
for each data channel, acquiring a feasible delay coefficient interval which can be correctly sampled and corresponds to the data channel under the current clock channel delay coefficient value, and selecting a middle value of the feasible delay coefficient interval as a final delay coefficient to obtain a delay coefficient value corresponding to the current data channel; the expression is as follows:
wherein s is the middle value of the feasible delay coefficient interval; s max The upper limit value of the feasible time delay coefficient interval is obtained; s min Is the lower limit value of the feasible delay coefficient interval.
Further, the value of the parameter m is one seventh or one eighth of the total number of data channels to be calibrated.
Further, the step S2 of determining that the calibration fails successfully includes the following operations:
and setting the delay coefficient value of the clock channel as the intermediate value of the selectable delay coefficient interval, and taking the best delay coefficient value of each data channel as the final delay coefficient value of the data channel on the basis.
Provided is an electronic apparatus, including:
a memory storing executable instructions; and
a processor configured to execute the executable instructions in the memory to implement a parallel data calibration method for inter-network-on-chip interconnects.
The invention has the beneficial effects that:
1. the invention can achieve the aim that each data channel can be aligned with the clock channel by self-adaptively and dynamically adjusting the delay coefficients of the clock and the data channels, thereby ensuring the correct transmission of the interconnected parallel data among the networks on a plurality of chips.
2. The smaller the parameter m of the invention is, the more severe the clock channel delay condition meeting the threshold interval is, i.e. the smaller the range of the clock channel delay coefficient which is screened out to meet the condition is, thereby the invention can adapt to different clock channel delay conditions.
3. The initial delay coefficient value of the clock channel is set to be larger than that of the data channel, so that the problem that the clock channel lags behind the data channel for a period of time when the clock rising edge is used for sampling data is solved.
4. The invention adopts the mode that the initial delay coefficient value of the clock channel is gradually reduced from the maximum value, so that the traversal is conveniently judged whether to be completed in the current convergence threshold value interval.
5. The left endpoint value is increased when the convergence threshold interval is adjusted, so that the clock channel delay coefficients which are tried to be matched with all the data channel delay coefficients can be prevented from being searched again, and the total searching time is shortened.
6. Searching for the most suitable delay factor for each data channel under the proposed clock channel delay state takes a long time, and if this operation is performed for each clock channel delay state in order, the search efficiency is very low. Therefore, the method and the device set the convergence threshold interval to screen out the clock channel delay coefficients which are possibly suitable, and then carry out the operation of adjusting the delay coefficients of each data channel, can improve the matching success rate, and thus save the calibration time.
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FIG. 1 is a schematic flow diagram of the process;
FIG. 2 is a flow chart of a process in an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, the parallel data calibration method for interconnection between networks on multiple chips includes the following steps:
s1, setting a convergence threshold interval, and setting initial delay coefficient values of a clock channel and each data channel; wherein the initial interval of the convergence threshold interval is [0, m);
s2, judging whether the left endpoint value of the current convergence threshold interval is less than or equal to the total number of the data channels, and if so, entering the step S3; otherwise, judging that the calibration cannot be successful;
s3, judging whether the number of the data channels which are not aligned currently meets the current convergence threshold interval or not, and if so, entering a step S4; otherwise, entering step S5;
s4, adjusting the delay coefficient value of each data channel under the current clock channel delay coefficient value, judging whether all the data channels can be correctly sampled or not, and if so, entering the step S6; otherwise, restoring the initial delay coefficient value of the data channel, and entering the step S5;
s5, judging whether all the delay coefficient values of the clock channel in the current convergence threshold interval are traversed or not, if so, increasing m to both end point values of the current convergence threshold interval, recovering the initial delay coefficient value of the clock channel, and returning to the step S2; otherwise, selecting the clock channel delay coefficient value which is not traversed under the current convergence threshold interval, and returning to the step S3;
and S6, respectively acquiring the delay coefficient values corresponding to the current clock channel and the data channel to finish calibration.
The selectable delay coefficient interval of the clock channel is the same as that of the data channel; the initial delay coefficient value of the clock channel is the upper limit value of the selectable delay coefficient interval; the initial delay coefficient value of the data channel is the intermediate value of the selectable delay coefficient interval, and the expression is as follows:
wherein a is an initial delay coefficient value of the data channel; a is max The time delay coefficient interval is the upper limit value of the selectable time delay coefficient interval of the data channel; a is a min The lower limit value of the selectable delay coefficient interval of the data channel; [. The]Representing an integer fetch operation.
The specific method for adjusting the delay coefficient value of each data channel under the current clock channel delay coefficient value in step S4 is as follows: and traversing the delay coefficient value of each data channel in the selectable delay coefficient interval under the current clock channel delay coefficient value.
The specific method for selecting the clock channel delay coefficient value which is not traversed under the current convergence threshold interval in the step S5 is as follows: subtracting 1 from the current clock channel delay coefficient value, and when the clock channel delay coefficient value after subtracting 1 is smaller than the lower limit of the selectable delay coefficient of the clock channel, judging that all the delay coefficient values of the clock channel under the current convergence threshold interval have been traversed; otherwise, judging that the traversal is not completed. In addition, the value of the delay coefficient of the clock channel can be randomly selected.
The specific method for acquiring the delay coefficient value corresponding to the current data channel in step S6 is as follows: for each data channel, acquiring a feasible delay coefficient interval which can be correctly sampled and corresponds to the data channel under the current clock channel delay coefficient value, and selecting a middle value of the feasible delay coefficient interval as a final delay coefficient to obtain a delay coefficient value corresponding to the current data channel; the expression is as follows:
wherein s is the middle value of the feasible delay coefficient interval; s max The upper limit value of the feasible time delay coefficient interval is obtained; s min Is the lower limit value of the feasible delay coefficient interval.
In a specific implementation process, the value of the parameter m may be selected according to the total number of data channels to be calibrated, and the smaller m is, the more severe the clock channel delay condition satisfying the threshold interval is, i.e., the smaller the range of the clock channel delay coefficient that satisfies the condition is screened out, the faster the iterative clock channel delay coefficient is, but the slower the iterative threshold interval is. Preferably, the value of the parameter m is one seventh or one eighth of the total number of data channels to be calibrated. If the left end point value k m of the threshold interval is greater than the total number of data channels, it means that an attempt has been made to adjust the delay coefficients of the data channels under all the delay coefficients of the clock channels, but a combination of delay conditions that can cause all the data channels to be correctly sampled cannot be found, so that it is determined that the situation is beyond the calibratable range and the calibration is not successful. After the step S2 determines that the calibration fails, the following operations are included: and setting the delay coefficient value of the clock channel as the intermediate value of the selectable delay coefficient interval, and taking the best delay coefficient value of each data channel as the final delay coefficient value on the basis.
The electronic device includes:
a memory storing executable instructions; and
a processor configured to execute the executable instructions in the memory to implement a parallel data calibration method for inter-network-on-chip interconnects.
In one embodiment of the present invention, assuming that 78 data lanes need to be aligned with the clock lane, all lane delay factor adjustable ranges are [0,31 ]]I.e. an upper limit of 31 and a lower limit of 0. T in the figure apclk And T apdata Representing the delay factors of the clock and data channels, respectively. Y and N respectively indicate satisfaction and non-satisfaction of the judgment condition. If a data channel is not aligned, that is, a signal transmitted by the data channel cannot be correctly sampled by a clock transmitted by a clock channel, a specific flow is described as follows:
as shown in fig. 2, first, by comprehensively considering the convergence difficulty and the convergence speed, the initial convergence threshold interval may be set to [0,10 ], the initial value of the clock channel delay factor is set to 31, and the initial values of all the data channel delay factors are set to 15.
And then judging whether the number of the unaligned data channels meets the convergence threshold value interval or not under the condition of the clock channel delay coefficient. If the difference is not satisfied, the clock channel delay coefficient needs to be reduced by 1, and then judgment is carried out again until the clock channel delay coefficient which can enable the number of the misaligned data channels to satisfy the convergence threshold value interval is found. Then, it is possible to start to find the most suitable delay factors for 78 data channels respectively. If all data channels can search a delay coefficient which can be correctly sampled under the condition of the delay coefficient of the clock channel, the calibration is successful. Otherwise, the next clock channel delay coefficient which can make the number of the misaligned data channels meet the convergence threshold interval needs to be searched again, but before this, the delay coefficients of all the data channels need to be restored to the initial value 15.
When the delay factor of the clock channel is reduced to 0, the convergence threshold interval needs to be readjusted, i.e. the left and right end points of the interval are increased by 10. If the incremented left endpoint value is still not greater than the total number of data lanes (78 in this example), the value of the clock lane delay factor may be restored to 31 and then the clock lane delay factor satisfying the new convergence threshold interval may be searched again. Otherwise, directly setting the delay coefficient of the clock channel to 15, and then searching the best delay coefficient of each data channel on the basis of the delay coefficient. Although the delay coefficient combination that enables all data channels to be correctly sampled cannot be found (i.e., calibration fails), it is guaranteed that the sampling condition is certainly better than the original sampling condition without calibration.
In summary, the present invention can expand the application range of the calibration method and achieve better calibration effect by considering the adjustment of the delay of the clock channel and the delay of the data channel. By dynamically and adaptively changing the convergence threshold interval of the clock channel, the convergence speed of the calibration algorithm can be increased, and the calibration efficiency is improved. Under the condition of meeting the convergence threshold interval of the clock channel, each data channel independently searches for a delay coefficient interval which can enable the data channel to be correctly sampled and searches out the most appropriate delay coefficient, and the calibration accuracy can be improved.
Claims (8)
1. A parallel data calibration method for interconnection among networks on multiple chips is characterized by comprising the following steps:
s1, setting a convergence threshold interval, and setting initial delay coefficient values of a clock channel and each data channel; wherein the initial interval of the convergence threshold interval is [0, m);
s2, judging whether the left endpoint value of the current convergence threshold value interval is less than or equal to the total number of the data channels, and if so, entering a step S3; otherwise, judging that the calibration cannot be successful;
s3, judging whether the number of the current unaligned data channels meets the current convergence threshold interval or not, and if so, entering a step S4; otherwise, entering step S5;
s4, adjusting the delay coefficient value of each data channel under the current clock channel delay coefficient value, judging whether all the data channels can be correctly sampled or not, and if so, entering the step S6; otherwise, recovering the initial delay coefficient value of the data channel and entering the step S5;
s5, judging whether all the delay coefficient values of the clock channel in the current convergence threshold interval are traversed or not, if so, increasing m to both end point values of the current convergence threshold interval, recovering the initial delay coefficient value of the clock channel, and returning to the step S2; otherwise, selecting a clock channel delay coefficient value which is not traversed under the current convergence threshold interval, and returning to the step S3;
and S6, respectively obtaining the delay coefficient values corresponding to the current clock channel and the data channel, and completing calibration.
2. The method for calibrating parallel data oriented to interconnection between networks on a plurality of chips according to claim 1, wherein the selectable delay coefficient interval of the clock channel is the same as the selectable delay coefficient interval of the data channel; the initial delay coefficient value of the clock channel is the upper limit value of the selectable delay coefficient interval; the initial delay coefficient value of the data channel is the intermediate value of the selectable delay coefficient interval, and the expression is as follows:
wherein a is an initial delay coefficient value of the data channel; a is max The time delay coefficient interval is the upper limit value of the selectable time delay coefficient interval of the data channel; a is min The time delay coefficient is the lower limit value of the selectable time delay coefficient interval of the data channel; [. For]Representing an integer fetch operation.
3. The method for calibrating parallel data for internetwork on multiple chips according to claim 2, wherein the specific method for adjusting the delay coefficient value of each data channel under the current clock channel delay coefficient value in step S4 is as follows:
and traversing the delay coefficient value of each data channel in the selectable delay coefficient interval under the current clock channel delay coefficient value.
4. The method for calibrating parallel data for internetwork on multiple chips according to claim 3, wherein the specific method for selecting the clock path delay coefficient value which is not traversed under the current convergence threshold interval in step S5 is as follows:
subtracting 1 from the current clock channel delay coefficient value, and when the clock channel delay coefficient value after subtracting 1 is smaller than the lower limit of the selectable delay coefficient of the clock channel, judging that all the delay coefficient values of the clock channel under the current convergence threshold interval have been traversed; otherwise, judging that the traversal is not completed.
5. The method for calibrating parallel data for internetwork on multiple chips according to claim 3, wherein the specific method for obtaining the delay coefficient value corresponding to the current data channel in step S6 is as follows:
for each data channel, acquiring a feasible delay coefficient interval which can be correctly sampled and corresponds to the data channel under the current clock channel delay coefficient value, and selecting a middle value of the feasible delay coefficient interval as a final delay coefficient to obtain a delay coefficient value corresponding to the current data channel; the expression is as follows:
wherein s is the middle value of the feasible delay coefficient interval; s max The upper limit value of the feasible time delay coefficient interval is obtained; s min Is the lower limit value of the feasible delay coefficient interval.
6. The method for parallel data calibration oriented to internetwork on chips of claim 2, wherein the value of parameter m is one seventh or one eighth of the total number of data channels to be calibrated.
7. The method for calibrating parallel data oriented to interconnection between networks on multiple chips according to claim 1, wherein the step S2 comprises the following operations after determining that the calibration fails:
and setting the delay coefficient value of the clock channel as the intermediate value of the selectable delay coefficient interval, and taking the best delay coefficient value of each data channel as the final delay coefficient value of the data channel on the basis.
8. An electronic device, comprising:
a memory storing executable instructions; and
a processor configured to execute the executable instructions in the memory to implement the parallel data calibration method for the interconnection between networks on a plurality of chips according to any one of claims 1 to 7.
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