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CN115857871B - A fuzzy logic full hardware computing circuit and its design method - Google Patents

A fuzzy logic full hardware computing circuit and its design method Download PDF

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CN115857871B
CN115857871B CN202310165875.6A CN202310165875A CN115857871B CN 115857871 B CN115857871 B CN 115857871B CN 202310165875 A CN202310165875 A CN 202310165875A CN 115857871 B CN115857871 B CN 115857871B
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memristor
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CN115857871A (en
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李亚
纪少军
戴青云
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Guangdong Polytechnic Normal University
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Abstract

The invention discloses a fuzzy logic full hardware computing circuit and a design method thereof, comprising the following steps: establishing a blurring module through a memristor, acquiring a membership function according to a memristor matrix structure, carrying out blurring processing through the membership function, and outputting membership degree; a fuzzy rule base module is constructed, membership is used as input of the fuzzy rule base module, and fuzzy rules and rule weights are obtained; and converting the rule into a mapping relation between fuzzy sets through an reasoning engine module, regulating and acquiring according to the back-piece relation so as to ensure that the accuracy of the memristive fuzzy logic system reaches the highest, and simulating and outputting the fuzzy logic full-hardware computing circuit. The invention provides a memristor fuzzy logic circuit for realizing large-scale parallel computation, has the distinct advantages of low power consumption, high fault tolerance, high parallelism and the like, and solves the problems that the software operation speed of the existing memristor fuzzy logic circuit is low and full parallel programming cannot be realized.

Description

一种模糊逻辑全硬件计算电路及其设计方法A fuzzy logic full hardware calculation circuit and its design method

技术领域Technical Field

本发明涉及忆阻模糊逻辑电路技术领域，更具体的，涉及一种模糊逻辑全硬件计算电路及其设计方法。The present invention relates to the technical field of memristor fuzzy logic circuits, and more specifically, to a fuzzy logic full hardware computing circuit and a design method thereof.

背景技术Background Art

目前，可穿戴式设备受制于体积、功耗和电池大小，需要更加可靠的实时计算能力。但是，大多数算法计算是在计算机上运行的，这种执行方式中计算和存储功能是相分离的，这就导致了“存储墙”和“冯·诺依曼瓶颈”问题的发生，限制了算法计算的运算速度，间接导致了现代可穿戴设备的高能耗问题。模糊逻辑在健康场景下具有很好的应用前景，模糊逻辑借助于隶属度函数概念可以解决因二值逻辑无法解决的种种不确定问题。忆阻模糊逻辑电路是一种新的模糊逻辑计算模式，有望解决可穿戴设备计算中的冯·诺依曼瓶颈所引发的效能问题。Currently, wearable devices are limited by size, power consumption and battery size, and require more reliable real-time computing capabilities. However, most algorithm calculations are run on computers, and the computing and storage functions are separated in this execution mode, which leads to the occurrence of "storage wall" and "von Neumann bottleneck" problems, limiting the speed of algorithm calculations and indirectly leading to the high energy consumption of modern wearable devices. Fuzzy logic has a good application prospect in health scenarios. Fuzzy logic can solve various uncertain problems that cannot be solved by binary logic with the help of the concept of membership function. Memristor fuzzy logic circuit is a new fuzzy logic computing mode, which is expected to solve the efficiency problem caused by the von Neumann bottleneck in wearable device computing.

现有的忆阻模糊逻辑电路采用软硬件相结合的运算架构，存在软件运算速度慢和无法实现全并行的编程等问题。因此，针对模糊学习的不同环节，设计一种低功耗、小体积、低延时的模糊学习的硬件电路是模糊理论走向产业应用过程亟待解决的问题之一。针对当前忆阻器模糊逻辑电路设计中存在的问题，亟需设计出可执行全并行编程的忆阻器模糊逻辑电路，将模糊算法从软件转移到硬件，加快模糊逻辑的计算速度，以适应当今大数据时代下可穿戴设备的高速信息计算处理要求。The existing memristor fuzzy logic circuit adopts a computing architecture that combines software and hardware, and has problems such as slow software computing speed and inability to implement full parallel programming. Therefore, for different links of fuzzy learning, designing a low-power, small-volume, and low-latency fuzzy learning hardware circuit is one of the problems that need to be solved in the process of fuzzy theory moving towards industrial application. In view of the problems existing in the current memristor fuzzy logic circuit design, it is urgent to design a memristor fuzzy logic circuit that can perform full parallel programming, transfer the fuzzy algorithm from software to hardware, and speed up the calculation speed of fuzzy logic to meet the high-speed information computing and processing requirements of wearable devices in today's big data era.

发明内容Summary of the invention

为了解决上述技术问题，本发明提出了一种模糊逻辑全硬件计算电路及其设计方法。In order to solve the above technical problems, the present invention proposes a fuzzy logic full hardware calculation circuit and a design method thereof.

本发明第一方面提供了一种模糊逻辑全硬件计算电路的设计方法，包括：A first aspect of the present invention provides a design method for a fuzzy logic full hardware calculation circuit, comprising:

通过忆阻器构建模糊化模块，根据忆阻矩阵结构获取隶属函数，通过隶属函数进行模糊化处理，输出隶属度；A fuzzy module is constructed through memristors, the membership function is obtained according to the memristor matrix structure, fuzzy processing is performed through the membership function, and the membership degree is output;

构建模糊规则库模块，将所述隶属度作为模糊规则库模块的输入，获取模糊规则及规则权重；Constructing a fuzzy rule base module, taking the membership degree as input of the fuzzy rule base module, and obtaining fuzzy rules and rule weights;

通过推理引擎模块将所述规则转化为模糊集之间的映射关系，根据后件关系调节获取使得忆阻模糊逻辑系统的精度达到最高；The rules are converted into mapping relationships between fuzzy sets through an inference engine module, and the accuracy of the memristor fuzzy logic system is maximized according to the consequent relationship.

对所述模糊化模块、模糊规则库模块及推理引擎模块进行仿真，获取基于模糊逻辑的全硬件计算电路。The fuzzification module, fuzzy rule base module and inference engine module are simulated to obtain a full hardware computing circuit based on fuzzy logic.

本方案中，通过忆阻器构建模糊化模块，根据忆阻矩阵结构获取隶属函数，通过隶属函数进行模糊化处理，输出隶属度，具体为：In this scheme, a fuzzification module is constructed by memristors, the membership function is obtained according to the memristor matrix structure, the fuzzification process is performed by the membership function, and the membership degree is output, which is specifically:

通过带记忆功能的非线性忆阻器模型构建模糊化模块，基于非线性忆阻器构建忆阻阵列结构实现隶属函数，在模糊化模型中忆阻阵列电路结构由两组平行的导线互相垂直组成，在每一个交叉点上有一个忆阻器连接两根交叉线；A fuzzy module is constructed through a nonlinear memristor model with memory function, and a memristor array structure is constructed based on the nonlinear memristor to realize the membership function. In the fuzzy model, the memristor array circuit structure consists of two sets of parallel wires perpendicular to each other, and there is a memristor connecting the two cross wires at each intersection.

隶属度存储在忆阻阵列交叉点处的忆阻器的记忆状态中，所述忆阻器的阻值通过施加电压在最高阻值

Figure SMS_1
和最低组织
Figure SMS_2
之间变化，将
Figure SMS_3
范围内的忆阻器通过编程映射为[0,1]范围内的隶属度；The membership is stored in the memory state of the memristor at the intersection of the memristor array, and the resistance of the memristor is changed by applying a voltage between the highest resistance value and the lowest resistance value.
Figure SMS_1
and minimum organization
Figure SMS_2
Change between
Figure SMS_3
Memristors in the range are mapped to membership in the range [0,1] through programming;

在忆阻阵列编程中设置单刀双掷开关，开关由NMOS晶体管的源极和PMOS晶体管的漏极连接组成，所述NMOS晶体管和PMOS晶体管的阈值电压分别为

Figure SMS_4
和
Figure SMS_5
；A single-pole double-throw switch is set in the programming of the memristor array. The switch is composed of a source of an NMOS transistor and a drain of a PMOS transistor. The threshold voltages of the NMOS transistor and the PMOS transistor are respectively
Figure SMS_4
and
Figure SMS_5
;

电压

Figure SMS_6
控制单刀双掷开关是否打开，当
Figure SMS_7
，PMOS晶体管导通，此时电路输入电压为
Figure SMS_8
，编程电压
Figure SMS_9
将施加在忆阻器的两端进行编程；当
Figure SMS_10
，NMOS晶体管导通，此时电路输入电压为
Figure SMS_11
，电路进入计算过程。Voltage
Figure SMS_6
Controls whether the single-pole double-throw switch is turned on.
Figure SMS_7
, the PMOS transistor is turned on, and the circuit input voltage is
Figure SMS_8
, programming voltage
Figure SMS_9
will be applied across the memristor for programming;
Figure SMS_10
, the NMOS transistor is turned on, and the circuit input voltage is
Figure SMS_11
, the circuit enters the calculation process.

本方案中，忆阻阵列编程，具体为：In this solution, the memristor array is programmed as follows:

当PMOS晶体管打开，NMOS晶体管关闭时，忆阻阵列电路进入编程操作过程，在编程操作过程中，忆阻阵列电路中的各忆阻器进行并行编程，忆阻器

Figure SMS_12
通过大于忆阻器阈值电压的输入脉冲电压
Figure SMS_13
单独调节When the PMOS transistor is turned on and the NMOS transistor is turned off, the memristor array circuit enters the programming operation process. During the programming operation process, each memristor in the memristor array circuit is programmed in parallel.
Figure SMS_12
By inputting a pulse voltage greater than the memristor threshold voltage
Figure SMS_13
Individual adjustment

定义

Figure SMS_14
和
Figure SMS_19
是输入域上的两个模糊集合，则
Figure SMS_22
和
Figure SMS_17
分别表示其隶属函数，其中
Figure SMS_18
在垂直导线
Figure SMS_21
上对应的忆阻器的阻值
Figure SMS_24
的编程表达式为：
Figure SMS_15
其中
Figure SMS_20
代表运算放大器的反馈电阻，
Figure SMS_23
表示隶属函数
Figure SMS_25
在点
Figure SMS_16
的隶属度；definition
Figure SMS_14
and
Figure SMS_19
are two fuzzy sets on the input domain, then
Figure SMS_22
and
Figure SMS_17
They represent their membership functions respectively, where
Figure SMS_18
On vertical wire
Figure SMS_21
The corresponding resistance of the memristor
Figure SMS_24
The programming expression is:
Figure SMS_15
in
Figure SMS_20
represents the feedback resistor of the operational amplifier,
Figure SMS_23
Represents membership function
Figure SMS_25
At the point
Figure SMS_16
The degree of membership;

将忆阻阵列电路上其它隶属度

Figure SMS_26
为0的忆阻值设置为
Figure SMS_27
，
Figure SMS_28
为忆阻器最大的阻值，对单个忆阻器施加正负电压信号，在正负电压的刺激下，忆阻器实现电阻在
Figure SMS_29
范围内的变化。The other memberships on the memristor array circuit
Figure SMS_26
The memristor value of 0 is set to
Figure SMS_27
,
Figure SMS_28
is the maximum resistance of the memristor. When positive and negative voltage signals are applied to a single memristor, the memristor realizes a resistance of
Figure SMS_29
Changes within the range.

本方案中，忆阻阵列计算，具体为：In this scheme, the memristor array calculation is specifically:

当NMOS晶体管打开，PMOS晶体管关闭时，忆阻阵列电路进入计算过程，定义

Figure SMS_30
和
Figure SMS_31
是输入域上的两个模糊集合，则
Figure SMS_32
和
Figure SMS_33
分别表示其隶属函数；When the NMOS transistor is turned on and the PMOS transistor is turned off, the memristor array circuit enters the calculation process, defined as
Figure SMS_30
and
Figure SMS_31
are two fuzzy sets on the input domain, then
Figure SMS_32
and
Figure SMS_33
Respectively represent their membership functions;

在忆阻阵列的输入端分别输入不超过忆阻器阈值电压的脉冲电压，进行忆阻阵列计算，所述忆阻阵列计算的表达式如下：

Figure SMS_34
其中，
Figure SMS_35
表示忆阻阵列电路某一列的输入，
Figure SMS_36
表示忆阻阵列某一行的输出，
Figure SMS_37
表示运算放大器的反馈电阻，
Figure SMS_38
表示忆阻阵列交叉点的忆阻值。A pulse voltage not exceeding the threshold voltage of the memristor is input to the input end of the memristor array to perform memristor array calculation. The expression of the memristor array calculation is as follows:
Figure SMS_34
in,
Figure SMS_35
represents the input of a column of the memristor array circuit,
Figure SMS_36
represents the output of a row of the memristor array,
Figure SMS_37
represents the feedback resistance of the operational amplifier,
Figure SMS_38
Represents the memristor value at the intersection of the memristor array.

本方案中，构建模糊规则库模块，将所述隶属度作为模糊规则库模块的输入，获取模糊规则及规则权重，具体为：In this solution, a fuzzy rule base module is constructed, and the membership degree is used as the input of the fuzzy rule base module to obtain fuzzy rules and rule weights, specifically:

通过模糊化处理之后，输出隶属度，作为模糊规则库模块的输入，所述模糊规则库模块由运算放大器、电阻、乘法器和除法器组成，其计算表达式为：

Figure SMS_39
其中，
Figure SMS_40
表示第
Figure SMS_41
条模糊规则对输入x i 的隶属度，
Figure SMS_42
表示第k条规则对应的隶属度乘积，
Figure SMS_43
表示第k条规则的权重值，
Figure SMS_44
表示输入变量的维度。After fuzzification processing, the membership degree is output as the input of the fuzzy rule base module. The fuzzy rule base module is composed of an operational amplifier, a resistor, a multiplier and a divider. The calculation expression is:
Figure SMS_39
in,
Figure SMS_40
Indicates
Figure SMS_41
The membership degree of the fuzzy rules to the input xi ,
Figure SMS_42
represents the membership product corresponding to the kth rule,
Figure SMS_43
represents the weight value of the kth rule,
Figure SMS_44
Indicates the dimensions of the input variables.

本方案中，通过推理引擎模块将所述规则转化为模糊集之间的映射关系，具体为：In this solution, the rules are converted into mapping relationships between fuzzy sets through the inference engine module, specifically:

所述推理引擎模块由后件参数权重单元、运算放大器、乘法器及电阻组成，推理引擎模块的计算表达式为：

Figure SMS_45
其中，
Figure SMS_46
表示第
Figure SMS_47
条规则的权重值，
Figure SMS_48
表示输入变量的加权平均和，
Figure SMS_49
表示后件参数权重，即每个输入变量的权重，
Figure SMS_50
表示输入变量的维度，
Figure SMS_51
表示忆阻模糊逻辑电路最终的输出结果。The inference engine module is composed of a subsequent parameter weight unit, an operational amplifier, a multiplier and a resistor. The calculation expression of the inference engine module is:
Figure SMS_45
in,
Figure SMS_46
Indicates
Figure SMS_47
The weight of the rule,
Figure SMS_48
represents the weighted average sum of the input variables,
Figure SMS_49
represents the consequent parameter weight, that is, the weight of each input variable,
Figure SMS_50
represents the dimension of the input variable,
Figure SMS_51
Represents the final output result of the memristor fuzzy logic circuit.

本方案中，所述后件参数权重单元由两个反向连接的忆阻器和一个单刀双掷开关组成，具体为：In this solution, the subsequent parameter weight unit is composed of two reversely connected memristors and a single-pole double-throw switch, specifically:

根据忆阻器及单刀双掷开关盘判断后件参数权重单元进入编程过程或计算过程，定义

Figure SMS_52
和
Figure SMS_53
为两个忆阻器的电导值，在编程过程中忆阻器的电导值
Figure SMS_54
和
Figure SMS_55
之间差值
Figure SMS_56
为是正值或负值；According to the memristor and the SPDT switch, the weight unit of the subsequent parameter is judged to enter the programming process or the calculation process, and the definition
Figure SMS_52
and
Figure SMS_53
is the conductance value of the two memristors. During programming, the conductance value of the memristor
Figure SMS_54
and
Figure SMS_55
Difference
Figure SMS_56
is a positive or negative value;

所述后件参数权重单元在计算过程中对后件参数权重

Figure SMS_57
的调节的计算表达式为：
Figure SMS_58
其中，
Figure SMS_59
，
Figure SMS_60
表示运算放大器的反馈电阻，
Figure SMS_61
表示输入信号，
Figure SMS_62
表示输出信号。The subsequent parameter weight unit weights the subsequent parameter weights during the calculation process.
Figure SMS_57
The calculation expression of the adjustment is:
Figure SMS_58
in,
Figure SMS_59
,
Figure SMS_60
represents the feedback resistance of the operational amplifier,
Figure SMS_61
represents the input signal,
Figure SMS_62
Indicates the output signal.

本发明第二方面提供了一种模糊逻辑全硬件计算电路，利用一种模糊逻辑全硬件计算电路的设计方法得到，包括模糊化模块、模糊规则库模块及推理引擎模块组成；The second aspect of the present invention provides a fuzzy logic full hardware computing circuit, which is obtained by using a design method for a fuzzy logic full hardware computing circuit, and includes a fuzzification module, a fuzzy rule base module and an inference engine module;

所述模糊化模块为忆阻器构成的忆阻阵列结构，所述忆阻阵列结构由两组平行的导线互相垂直组成，在每一个交叉点上有一个忆阻器连接两根交叉线，采用双CMOS控制开关，构建全并行编程的隶属函数存储电路；忆阻值通过施加合适的电压在

Figure SMS_63
及
Figure SMS_64
之间变化，每一行连接着一个运算放大器的负端，运算放大器具有一个固定的电阻Rf作为反馈电阻；The fuzzification module is a memristor array structure composed of memristors. The memristor array structure consists of two sets of parallel wires perpendicular to each other. At each intersection, there is a memristor connecting the two cross wires. A dual CMOS control switch is used to construct a fully parallel programmable membership function storage circuit. The memristor value is adjusted by applying a suitable voltage.
Figure SMS_63
and
Figure SMS_64
Each row is connected to the negative terminal of an operational amplifier, which has a fixed resistor Rf as a feedback resistor;

所述模糊规则库模块由运算放大器、电阻、乘法器和除法器组成，所述除法器将模拟乘法器置于运算放大器的负反馈环路中，构成除法运算电路；The fuzzy rule base module is composed of an operational amplifier, a resistor, a multiplier and a divider, wherein the divider places an analog multiplier in a negative feedback loop of the operational amplifier to form a division operation circuit;

所述推理引擎模块后件参数权重单元、运算放大器，乘法器和电阻组成，所述后件参数权重单元，由两个反向连接的忆阻器和一个单刀双掷开关组成，实现正负后件参数权重的实时调节。The inference engine module is composed of a subsequent parameter weight unit, an operational amplifier, a multiplier and a resistor. The subsequent parameter weight unit is composed of two reversely connected memristors and a single-pole double-throw switch to achieve real-time adjustment of positive and negative subsequent parameter weights.

本发明公开了一种模糊逻辑全硬件计算电路及其设计方法，包括：通过忆阻器构建模糊化模块，根据忆阻矩阵结构获取隶属函数，通过隶属函数进行模糊化处理，输出隶属度；构建模糊规则库模块，将隶属度作为模糊规则库模块的输入，获取模糊规则及规则权重；通过推理引擎模块将所述规则转化为模糊集之间的映射关系，根据后件关系调节获取使得忆阻模糊逻辑系统的精度达到最高，仿真输出模糊逻辑全硬件计算电路。本发明提出忆阻模糊逻辑电路实现大规模并行计算，具有低功耗、高容错、高度并行性等鲜明优势，解决现有忆阻模糊逻辑电路软件运算速度慢和无法实现全并行编程的问题。The present invention discloses a fuzzy logic full hardware computing circuit and a design method thereof, including: constructing a fuzzification module through a memristor, obtaining a membership function according to a memristor matrix structure, performing fuzzification processing through the membership function, and outputting a membership degree; constructing a fuzzy rule base module, using the membership degree as the input of the fuzzy rule base module, and obtaining fuzzy rules and rule weights; converting the rules into a mapping relationship between fuzzy sets through an inference engine module, adjusting and obtaining according to the consequent relationship so that the accuracy of the memristor fuzzy logic system reaches the highest, and simulating and outputting a fuzzy logic full hardware computing circuit. The present invention proposes a memristor fuzzy logic circuit to realize large-scale parallel computing, which has distinct advantages such as low power consumption, high fault tolerance, and high parallelism, and solves the problems of slow computing speed of existing memristor fuzzy logic circuit software and inability to realize full parallel programming.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1示出了本发明一种模糊逻辑全硬件计算电路的设计方法的流程图；FIG1 shows a flow chart of a design method of a fuzzy logic full hardware calculation circuit according to the present invention;

图2示出了本发明中模糊集合

Figure SMS_65
和
Figure SMS_66
的隶属函数表示及忆阻阵列电路实现示意图；FIG. 2 shows the fuzzy set in the present invention.
Figure SMS_65
and
Figure SMS_66
Membership function representation and memristor array circuit implementation schematic diagram;

图3示出了本发明忆阻器编程单刀双掷开关的电路图；FIG3 shows a circuit diagram of a memristor-programmed single-pole double-throw switch according to the present invention;

图4示出了本发明忆阻阵列电路的编程过程的电路实现示意图；FIG4 is a schematic diagram showing a circuit implementation of a programming process of a memristor array circuit of the present invention;

图5示出了本发明忆阻阵列电路的计算过程的电路实现示意图；FIG5 is a schematic diagram showing a circuit implementation of a calculation process of a memristor array circuit of the present invention;

图6示出了本发明模糊规则库模块的电路实现示意图；FIG6 shows a schematic diagram of a circuit implementation of a fuzzy rule base module of the present invention;

图7示出了本发明模糊规则库模块中除法运算电路的实现示意图；FIG7 shows a schematic diagram of the implementation of the division operation circuit in the fuzzy rule base module of the present invention;

图8示出了本发明推理引擎模块的电路实现示意图；FIG8 shows a schematic diagram of a circuit implementation of an inference engine module of the present invention;

图9示出了本发明推理引擎模块中后件参数权重单元电路的实现示意图。FIG. 9 shows a schematic diagram of the implementation of the subsequent parameter weight unit circuit in the inference engine module of the present invention.

具体实施方式DETAILED DESCRIPTION

为了能够更清楚地理解本发明的上述目的、特征和优点，下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用其他不同于在此描述的其他方式来实施，因此，本发明的保护范围并不受下面公开的具体实施例的限制。In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

图1示出了本发明一种模糊逻辑全硬件计算电路的设计方法的流程图。FIG. 1 shows a flow chart of a design method of a fuzzy logic full hardware calculation circuit according to the present invention.

如图1所示，本发明第一方面提供了一种模糊逻辑全硬件计算电路的设计方法，包括：As shown in FIG1 , the first aspect of the present invention provides a design method for a fuzzy logic full hardware calculation circuit, comprising:

S102，通过忆阻器构建模糊化模块，根据忆阻矩阵结构获取隶属函数，通过隶属函数进行模糊化处理，输出隶属度；S102, constructing a fuzzification module through a memristor, obtaining a membership function according to a memristor matrix structure, performing fuzzification processing through the membership function, and outputting a membership degree;

S104，构建模糊规则库模块，将所述隶属度作为模糊规则库模块的输入，获取模糊规则及规则权重；S104, constructing a fuzzy rule base module, taking the membership degree as the input of the fuzzy rule base module, and obtaining fuzzy rules and rule weights;

S106，通过推理引擎模块将所述规则转化为模糊集之间的映射关系，根据后件关系调节获取使得忆阻模糊逻辑系统的精度达到最高；S106, converting the rule into a mapping relationship between fuzzy sets through an inference engine module, and adjusting and acquiring the mapping relationship according to the consequent relationship so that the accuracy of the memristor fuzzy logic system reaches the highest level;

S108，对所述模糊化模块、模糊规则库模块及推理引擎模块进行仿真，获取基于模糊逻辑的全硬件计算电路。S108, simulating the fuzzification module, fuzzy rule base module and reasoning engine module to obtain a full hardware computing circuit based on fuzzy logic.

需要说明的是，采用了带有记忆功能的非线性忆阻器模型，所述忆阻器模型的值是随着输入脉冲电压的变化而变化；当输入的正向脉冲电压达到忆阻器的正阈值时，忆阻器的阻值则快速减少；当输入的负向脉冲电压达到忆阻器的负阈值时，忆阻器的阻值则快速增加，具有记忆功能的忆阻器模型变量参数为：

Figure SMS_77
其中，
Figure SMS_69
表示离子转移率，
Figure SMS_73
和
Figure SMS_81
分别表示忆阻器的最高阻值和最低阻值，
Figure SMS_84
、
Figure SMS_82
和
Figure SMS_85
表示不变量，
Figure SMS_78
表示忆阻器的电流值。
Figure SMS_83
和
Figure SMS_68
分别表示忆阻器阻变层总厚度和掺杂层厚度，当
Figure SMS_74
增加时即掺杂层空间增大（减少），整个忆阻器的阻值降低（增大）；
Figure SMS_70
和
Figure SMS_72
分别表示忆阻器的正阈值电压和负阈值电压。
Figure SMS_76
表示特殊的窗函数；
Figure SMS_80
为正整数。
Figure SMS_67
=
Figure SMS_71
-
Figure SMS_75
，
Figure SMS_79
表示忆阻器最高阻值和最低阻值的差值。It should be noted that a nonlinear memristor model with memory function is used, and the value of the memristor model changes with the input pulse voltage; when the input positive pulse voltage reaches the positive threshold of the memristor, the resistance of the memristor decreases rapidly; when the input negative pulse voltage reaches the negative threshold of the memristor, the resistance of the memristor increases rapidly. The variable parameters of the memristor model with memory function are:
Figure SMS_77
in,
Figure SMS_69
represents the ion transfer rate,
Figure SMS_73
and
Figure SMS_81
Respectively represent the highest and lowest resistance values of the memristor,
Figure SMS_84
,
Figure SMS_82
and
Figure SMS_85
represents an invariant,
Figure SMS_78
represents the current value of the memristor.
Figure SMS_83
and
Figure SMS_68
Respectively represent the total thickness of the resistive switching layer and the thickness of the doping layer of the memristor.
Figure SMS_74
When it increases, the space of the doping layer increases (decreases), and the resistance of the entire memristor decreases (increases);
Figure SMS_70
and
Figure SMS_72
represent the positive threshold voltage and negative threshold voltage of the memristor respectively.
Figure SMS_76
Represents a special window function;
Figure SMS_80
Is a positive integer.
Figure SMS_67
=
Figure SMS_71
-
Figure SMS_75
,
Figure SMS_79
Represents the difference between the highest and lowest resistance values of the memristor.

需要说明的是，模糊化模块的功能主要是通过隶属函数将输入的值转换为隶属度，通过带记忆功能的非线性忆阻器模型构建模糊化模块，基于非线性忆阻器构建忆阻阵列结构实现隶属函数。假设定义

Figure SMS_86
和
Figure SMS_87
是输入域上的两个模糊集合，则
Figure SMS_88
和
Figure SMS_89
分别表示它们两个的隶属函数，如图2(a)所示；每个隶属函数存储在忆阻阵列的每一行中，隶属函数和输入都将离散化，如图2(b)所示。输入变量的分辨率由忆阻阵列的列数（忆阻器的数量）决定，随着列数的逐渐增加，忆阻阵列电路的精度也会随之提高。如图2(c)所示，在模糊化模型中忆阻阵列电路结构由两组平行的导线互相垂直组成，在每一个交叉点上有一个忆阻器连接两根交叉线，每个忆阻器的阻值可以提前通过施加脉冲电压来进行编程。It should be noted that the function of the fuzzification module is mainly to convert the input value into membership through the membership function, and the fuzzification module is constructed through the nonlinear memristor model with memory function, and the memristor array structure is constructed based on the nonlinear memristor to realize the membership function.
Figure SMS_86
and
Figure SMS_87
are two fuzzy sets on the input domain, then
Figure SMS_88
and
Figure SMS_89
Represent their two membership functions respectively, as shown in Figure 2(a); each membership function is stored in each row of the memristor array, and both the membership function and the input are discretized, as shown in Figure 2(b). The resolution of the input variable is determined by the number of columns (the number of memristors) of the memristor array. As the number of columns gradually increases, the accuracy of the memristor array circuit will also increase. As shown in Figure 2(c), in the fuzzy model, the memristor array circuit structure consists of two sets of parallel wires perpendicular to each other. At each intersection, there is a memristor connecting the two cross wires. The resistance value of each memristor can be programmed in advance by applying a pulse voltage.

隶属度存储在忆阻阵列交叉点处的忆阻器的记忆状态中，所述忆阻器的阻值通过施加电压在最高阻值

Figure SMS_90
和最低组织
Figure SMS_91
之间变化，将
Figure SMS_92
范围内的忆阻器通过编程映射为[0,1]范围内的隶属度；The membership is stored in the memory state of the memristor at the intersection of the memristor array, and the resistance of the memristor is changed by applying a voltage between the highest resistance value and the lowest resistance value.
Figure SMS_90
and minimum organization
Figure SMS_91
Change between
Figure SMS_92
Memristors in the range are mapped to membership in the range [0,1] through programming;

由于在传统的忆阻阵列电路编程过程中会存在漏电流的问题，所以无法实现同时对电路中所有的忆阻器进行编程，所以本发明中在忆阻阵列编程中设置单刀双掷开关，开关由NMOS晶体管的源极和PMOS晶体管的漏极连接组成，所述NMOS晶体管和PMOS晶体管的阈值电压分别为

Figure SMS_94
和
Figure SMS_96
；电压
Figure SMS_98
控制单刀双掷开关是否打开，当
Figure SMS_95
，PMOS晶体管导通，此时电路输入电压为
Figure SMS_97
，编程电压
Figure SMS_99
将施加在忆阻器的两端进行编程；当
Figure SMS_100
，NMOS晶体管导通，此时电路输入电压为
Figure SMS_93
，电路进入计算过程。Since leakage current may exist in the conventional memristor array circuit programming process, it is impossible to program all memristors in the circuit at the same time. Therefore, a single-pole double-throw switch is provided in the memristor array programming in the present invention. The switch is composed of a source of an NMOS transistor and a drain of a PMOS transistor. The threshold voltages of the NMOS transistor and the PMOS transistor are respectively
Figure SMS_94
and
Figure SMS_96
;Voltage
Figure SMS_98
Controls whether the single-pole double-throw switch is turned on.
Figure SMS_95
, the PMOS transistor is turned on, and the circuit input voltage is
Figure SMS_97
, programming voltage
Figure SMS_99
will be applied across the memristor for programming;
Figure SMS_100
, the NMOS transistor is turned on, and the circuit input voltage is
Figure SMS_93
, the circuit enters the calculation process.

图4示出了本发明忆阻阵列电路的编程过程的电路实现示意图，忆阻阵列编程，具体为：当PMOS晶体管打开，NMOS晶体管关闭时，忆阻阵列电路进入编程操作过程，在编程操作过程中，忆阻阵列电路中的各忆阻器进行并行编程，忆阻器

Figure SMS_101
通过大于忆阻器阈值电压的输入脉冲电压
Figure SMS_108
单独调节，需要注意的是，电压
Figure SMS_112
需要大于忆阻器的阈值电压，因为每个忆阻器都可以进行单独的编程，所以忆阻阵列电路可以实现并行编程，定义
Figure SMS_102
和
Figure SMS_107
是输入域上的两个模糊集合，则
Figure SMS_111
和
Figure SMS_115
分别表示其隶属函数，其中
Figure SMS_103
在垂直导线
Figure SMS_105
上对应的忆阻器的阻值
Figure SMS_109
的编程表达式为：
Figure SMS_113
其中
Figure SMS_104
代表运算放大器的反馈电阻，
Figure SMS_106
表示隶属函数
Figure SMS_110
在点
Figure SMS_114
的隶属度；FIG4 shows a schematic diagram of a circuit implementation of a programming process of a memristor array circuit of the present invention. Specifically, when the PMOS transistor is turned on and the NMOS transistor is turned off, the memristor array circuit enters a programming operation process. During the programming operation process, each memristor in the memristor array circuit is programmed in parallel.
Figure SMS_101
By inputting a pulse voltage greater than the memristor threshold voltage
Figure SMS_108
Adjust separately, it should be noted that the voltage
Figure SMS_112
Need to be greater than the threshold voltage of the memristor. Since each memristor can be programmed individually, the memristor array circuit can be programmed in parallel. Define
Figure SMS_102
and
Figure SMS_107
are two fuzzy sets on the input domain, then
Figure SMS_111
and
Figure SMS_115
They represent their membership functions respectively, where
Figure SMS_103
On vertical wire
Figure SMS_105
The corresponding resistance of the memristor
Figure SMS_109
The programming expression is:
Figure SMS_113
in
Figure SMS_104
represents the feedback resistor of the operational amplifier,
Figure SMS_106
Represents membership function
Figure SMS_110
At the point
Figure SMS_114
The degree of membership;

将忆阻阵列电路上其它隶属度

Figure SMS_116
为0的忆阻值设置为
Figure SMS_117
，
Figure SMS_118
为忆阻器最大的阻值，对单个忆阻器施加正负电压信号，在正负电压的刺激下，忆阻器实现电阻在
Figure SMS_119
范围内的变化。The other memberships on the memristor array circuit
Figure SMS_116
The memristor value of 0 is set to
Figure SMS_117
,
Figure SMS_118
is the maximum resistance of the memristor. When positive and negative voltage signals are applied to a single memristor, the memristor realizes a resistance of
Figure SMS_119
Changes within the range.

图5示出了本发明忆阻阵列电路的计算过程的电路实现示意图，忆阻阵列计算，具体为：当NMOS晶体管打开，PMOS晶体管关闭时，忆阻阵列电路进入计算过程，定义

Figure SMS_120
和
Figure SMS_125
是输入域上的两个模糊集合，则
Figure SMS_127
和
Figure SMS_122
分别表示其隶属函数，获取编程后的忆阻器阻值；在忆阻阵列的输入端分别输入不超过忆阻器阈值电压的脉冲电压，进行忆阻阵列计算，所述忆阻阵列计算的表达式如下：
Figure SMS_123
其中，
Figure SMS_126
表示忆阻阵列电路某一列的输入，
Figure SMS_128
表示忆阻阵列某一行的输出，
Figure SMS_121
表示运算放大器的反馈电阻，
Figure SMS_124
表示忆阻阵列交叉点的忆阻值。FIG5 shows a schematic diagram of a circuit implementation of the calculation process of the memristor array circuit of the present invention. The memristor array calculation is specifically as follows: when the NMOS transistor is turned on and the PMOS transistor is turned off, the memristor array circuit enters the calculation process, and defines
Figure SMS_120
and
Figure SMS_125
are two fuzzy sets on the input domain, then
Figure SMS_127
and
Figure SMS_122
Respectively represent their membership functions, and obtain the resistance value of the programmed memristor; respectively input a pulse voltage that does not exceed the threshold voltage of the memristor at the input end of the memristor array to perform memristor array calculation, and the expression of the memristor array calculation is as follows:
Figure SMS_123
in,
Figure SMS_126
represents the input of a column of the memristor array circuit,
Figure SMS_128
represents the output of a row of the memristor array,
Figure SMS_121
represents the feedback resistance of the operational amplifier,
Figure SMS_124
Represents the memristor value at the intersection of the memristor array.

假设在忆阻阵列的输入端

Figure SMS_130
分别输入1V的脉冲电压，输入的脉冲电压幅度不能超过忆阻器的阈值电压，否则会改变忆阻器的阻值。隶属函数
Figure SMS_133
和
Figure SMS_137
的输出结果分别为隶属度
Figure SMS_131
)和
Figure SMS_136
。以输入信号
Figure SMS_140
为例，隶属度
Figure SMS_143
和
Figure SMS_129
均等于0.5。值得一提的是，当输入信号为
Figure SMS_134
和
Figure SMS_138
时，隶属函数
Figure SMS_141
(
Figure SMS_132
)和
Figure SMS_135
(
Figure SMS_139
)对应的输出等于
Figure SMS_142
，理想情况下输出应该为0。Assume that at the input of the memristor array
Figure SMS_130
Input a pulse voltage of 1 V respectively. The input pulse voltage amplitude cannot exceed the threshold voltage of the memristor, otherwise it will change the resistance value of the memristor. Membership function
Figure SMS_133
and
Figure SMS_137
The output results are membership
Figure SMS_131
)and
Figure SMS_136
. With input signal
Figure SMS_140
For example, the membership
Figure SMS_143
and
Figure SMS_129
are all equal to 0.5. It is worth mentioning that when the input signal is
Figure SMS_134
and
Figure SMS_138
When
Figure SMS_141
(
Figure SMS_132
)and
Figure SMS_135
(
Figure SMS_139
) corresponds to the output
Figure SMS_142
, ideally the output should be 0.

需要说明的是，模糊规则库模块主要存放根据模糊语义集制定的模糊规则。通常模糊规则的数量会随着模糊语义集的增加而增加。在模糊化处理之后，输出的是隶属度，将其作为模糊规则库模块的输入。图6示出了本发明模糊规则库模块的电路实现示意图，图中

Figure SMS_144
和
Figure SMS_145
是同一个输入信号经过模糊化模块输出的两个不同的隶属度值，
Figure SMS_146
是另外一个输入信号产生的隶属度值，
Figure SMS_147
和
Figure SMS_148
是经过规则库电路模块计算的两个规则权重输出值。It should be noted that the fuzzy rule base module mainly stores fuzzy rules formulated according to fuzzy semantic sets. Usually, the number of fuzzy rules increases with the increase of fuzzy semantic sets. After fuzzification, the output is the membership degree, which is used as the input of the fuzzy rule base module. FIG6 shows a schematic diagram of the circuit implementation of the fuzzy rule base module of the present invention.
Figure SMS_144
and
Figure SMS_145
These are two different membership values output by the fuzzification module for the same input signal.
Figure SMS_146
is the membership value generated by another input signal,
Figure SMS_147
and
Figure SMS_148
These are the two rule weight output values calculated by the rule base circuit module.

所述模糊规则库模块由运算放大器、电阻、乘法器和除法器组成，其计算表达式为：

Figure SMS_149
其中，
Figure SMS_150
表示第
Figure SMS_151
条模糊规则对输入x i 的隶属度。
Figure SMS_152
表示第k条规则对应的隶属度乘积。
Figure SMS_153
表示第k条规则的权重值，
Figure SMS_154
表示输入变量的维度。The fuzzy rule base module is composed of an operational amplifier, a resistor, a multiplier and a divider, and its calculation expression is:
Figure SMS_149
in,
Figure SMS_150
Indicates
Figure SMS_151
The membership degree of the fuzzy rules to the input xi .
Figure SMS_152
Represents the membership product corresponding to the kth rule.
Figure SMS_153
represents the weight value of the kth rule,
Figure SMS_154
Indicates the dimensions of the input variables.

图7示出了本发明模糊规则库模块中除法运算电路的实现示意图，将模拟乘法器置于运算放大器的负反馈环路中，则可构成除法运算电路。

Figure SMS_155
和
Figure SMS_156
为除法电路的输入，
Figure SMS_157
为输出；为了得到适当的反馈极性，输入信号
Figure SMS_158
必须是正值的。当图中电阻
Figure SMS_159
时，除法电路的运算表达式如下：
Figure SMS_160
需要说明的是，推理引擎模块的功能是将存储在规则库中的规则转化为模糊集之间的映射关系。通常推理引擎主要实现的是模糊逻辑中的后件（THEN）部分，通过推理引擎模块将所述规则转化为模糊集之间的映射关系。FIG7 shows a schematic diagram of the implementation of the division operation circuit in the fuzzy rule base module of the present invention. By placing an analog multiplier in the negative feedback loop of an operational amplifier, a division operation circuit can be constructed.
Figure SMS_155
and
Figure SMS_156
is the input of the division circuit,
Figure SMS_157
For output; in order to obtain the appropriate feedback polarity, the input signal
Figure SMS_158
Must be positive.
Figure SMS_159
When , the operation expression of the division circuit is as follows:
Figure SMS_160
It should be noted that the function of the inference engine module is to convert the rules stored in the rule base into mapping relationships between fuzzy sets. Usually, the inference engine mainly implements the THEN part in fuzzy logic, and converts the rules into mapping relationships between fuzzy sets through the inference engine module.

图8示出了本发明推理引擎模块的电路实现示意图，图中

Figure SMS_161
和
Figure SMS_162
是分别输入推理引擎模块和模糊化模块的初始信号源，
Figure SMS_163
和
Figure SMS_164
是输入信号所对应的规则输出权重值，
Figure SMS_165
和
Figure SMS_166
是规则后件参数的输出。FIG8 shows a schematic diagram of a circuit implementation of the inference engine module of the present invention.
Figure SMS_161
and
Figure SMS_162
are the initial signal sources input into the inference engine module and the fuzzification module respectively,
Figure SMS_163
and
Figure SMS_164
is the rule output weight value corresponding to the input signal,
Figure SMS_165
and
Figure SMS_166
It is the output of the rule's consequent parameter.

所述推理引擎模块由后件参数权重单元、运算放大器、乘法器及电阻组成，推理引擎模块的计算表达式为：

Figure SMS_167
其中，
Figure SMS_168
表示第
Figure SMS_169
条规则的权重值，
Figure SMS_170
表示输入变量的加权平均和，
Figure SMS_171
表示后件参数权重，即每个输入变量的权重，
Figure SMS_172
表示输入变量的维度，
Figure SMS_173
表示忆阻模糊逻辑电路最终的输出结果。The inference engine module is composed of a subsequent parameter weight unit, an operational amplifier, a multiplier and a resistor. The calculation expression of the inference engine module is:
Figure SMS_167
in,
Figure SMS_168
Indicates
Figure SMS_169
The weight of the rule,
Figure SMS_170
represents the weighted average sum of the input variables,
Figure SMS_171
represents the consequent parameter weight, that is, the weight of each input variable,
Figure SMS_172
represents the dimension of the input variable,
Figure SMS_173
Represents the final output result of the memristor fuzzy logic circuit.

图9示出了本发明推理引擎模块中后件参数权重单元电路的实现示意图，所述后件参数权重单元由两个反向连接的忆阻器和一个单刀双掷开关组成，具体为：根据忆阻器及单刀双掷开关盘判断后件参数权重单元进入编程过程或计算过程，定义

Figure SMS_175
和
Figure SMS_178
为两个忆阻器的电导值；当PMOS打开，NMOS关闭时，后件参数权重单元进入编程过程。输入编程电压
Figure SMS_181
，忆阻器的电导值
Figure SMS_176
和
Figure SMS_180
之间的差值
Figure SMS_183
的值可以是正和负。当NMOS打开，PMOS关闭时，后件参数权重单元进入计算过程，所述后件参数权重单元在计算过程中对后件参数权重
Figure SMS_185
的调节的计算表达式为：
Figure SMS_174
其中，
Figure SMS_179
，
Figure SMS_182
表示运算放大器的反馈电阻，
Figure SMS_184
表示输入信号，
Figure SMS_177
表示输出信号。FIG9 shows a schematic diagram of the implementation of the subsequent parameter weight unit circuit in the inference engine module of the present invention. The subsequent parameter weight unit is composed of two reversely connected memristors and a single-pole double-throw switch. Specifically, the subsequent parameter weight unit is judged to enter the programming process or the calculation process according to the memristor and the single-pole double-throw switch disk, and the definition
Figure SMS_175
and
Figure SMS_178
is the conductance value of the two memristors; when PMOS is turned on and NMOS is turned off, the subsequent parameter weight unit enters the programming process. Input programming voltage
Figure SMS_181
, the conductance of the memristor
Figure SMS_176
and
Figure SMS_180
The difference between
Figure SMS_183
The value of can be positive or negative. When NMOS is turned on and PMOS is turned off, the subsequent parameter weight unit enters the calculation process. The subsequent parameter weight unit calculates the subsequent parameter weight in the calculation process.
Figure SMS_185
The calculation expression of the adjustment is:
Figure SMS_174
in,
Figure SMS_179
,
Figure SMS_182
represents the feedback resistance of the operational amplifier,
Figure SMS_184
represents the input signal,
Figure SMS_177
Indicates the output signal.

推理引擎的最终计算输出结果为

Figure SMS_186
，输出结果y是忆阻模糊逻辑系统一个精确的值，不需要再进行去模糊化处理。本发明中的模糊逻辑系统的输出量在没有去模糊化的情况下仍然是精确值，优点是由于输出量可以用输入值的线性组合来表示。因而能够利用参数估计方法来确定系统的参数，同时可以应用线性控制系统的分析方法来近似分析和设计模糊逻辑系统。The final calculation output of the inference engine is
Figure SMS_186
, the output result y is an accurate value of the memristor fuzzy logic system, and no defuzzification is required. The output of the fuzzy logic system in the present invention is still an accurate value without defuzzification, and the advantage is that the output can be represented by a linear combination of input values. Therefore, the parameter estimation method can be used to determine the parameters of the system, and the analysis method of the linear control system can be applied to approximate the analysis and design of the fuzzy logic system.

本发明第二方面提供了一种模糊逻辑全硬件计算电路，利用一种模糊逻辑全硬件计算电路的设计方法得到，包括模糊化模块、模糊规则库模块及推理引擎模块组成；The second aspect of the present invention provides a fuzzy logic full hardware computing circuit, which is obtained by using a design method for a fuzzy logic full hardware computing circuit, and includes a fuzzification module, a fuzzy rule base module and an inference engine module;

所述模糊化模块为忆阻器构成的忆阻阵列结构，所述忆阻阵列结构由两组平行的导线互相垂直组成，在每一个交叉点上有一个忆阻器连接两根交叉线，采用双CMOS控制开关，构建全并行编程的隶属函数存储电路；忆阻值通过施加合适的电压在

Figure SMS_187
及
Figure SMS_188
之间变化，每一行连接着一个运算放大器的负端，运算放大器具有一个固定的电阻Rf作为反馈电阻；The fuzzification module is a memristor array structure composed of memristors. The memristor array structure consists of two sets of parallel wires perpendicular to each other. At each intersection, there is a memristor connecting the two cross wires. A dual CMOS control switch is used to construct a fully parallel programmable membership function storage circuit. The memristor value is adjusted by applying a suitable voltage.
Figure SMS_187
and
Figure SMS_188
Each row is connected to the negative terminal of an operational amplifier, which has a fixed resistor Rf as a feedback resistor;

所述模糊规则库模块由运算放大器、电阻、乘法器和除法器组成，所述除法器将模拟乘法器置于运算放大器的负反馈环路中，构成除法运算电路；The fuzzy rule base module is composed of an operational amplifier, a resistor, a multiplier and a divider, wherein the divider places an analog multiplier in a negative feedback loop of the operational amplifier to form a division operation circuit;

所述推理引擎模块后件参数权重单元、运算放大器，乘法器和电阻组成，所述后件参数权重单元，由两个反向连接的忆阻器和一个单刀双掷开关组成，实现正负后件参数权重的实时调节。The inference engine module is composed of a subsequent parameter weight unit, an operational amplifier, a multiplier and a resistor. The subsequent parameter weight unit is composed of two reversely connected memristors and a single-pole double-throw switch to achieve real-time adjustment of positive and negative subsequent parameter weights.

在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器（ROM，Read-OnlyMemory）、随机存取存储器（RAM，RandomAccessMemory）、磁碟或者光盘等各种可以存储程序代码的介质。Those skilled in the art can understand that: all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, and other media that can store program codes.

或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备（可以是个人计算机、服务器、或者网络设备等）执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (5)

1. The design method of the fuzzy logic all-hardware computing circuit is characterized by comprising the following steps of:
establishing a blurring module through a memristor, acquiring a membership function according to a memristor matrix structure, carrying out blurring processing through the membership function, and outputting membership degree;
a fuzzy rule base module is constructed, the membership is used as the input of the fuzzy rule base module, and a fuzzy rule and rule weight are obtained;
converting the rule into a mapping relation between fuzzy sets through an reasoning engine module, and regulating and acquiring according to the back-piece relation so as to ensure that the accuracy of the memristive fuzzy logic system reaches the highest;
simulating the blurring module, the blurring rule base module and the reasoning engine module to obtain a full hardware computing circuit based on fuzzy logic;
establishing a blurring module through a memristor, acquiring a membership function according to a memristor matrix structure, carrying out blurring processing through the membership function, and outputting membership degree, wherein the blurring module comprises the following specific steps:
building a fuzzy module through a nonlinear memristor model with a memory function, building a memristor array structure based on the nonlinear memristors to realize membership functions, wherein the memristor array circuit structure in the fuzzy module is composed of two groups of parallel wires which are mutually perpendicular, and one memristor is connected with two cross wires at each cross point;
membership is stored in the memory state of memristors at memristive array intersections, the resistance of the memristors being at the lowest resistance by applying a voltage
Figure QLYQS_1
And highest resistance->
Figure QLYQS_2
Change between, will->
Figure QLYQS_3
Memristors within range are programmed to map to [0,1 ]]Membership in the range;
setting a single-pole double-throw switch in memristor array programming, wherein the switch is formed by connecting a source electrode of an NMOS transistor and a drain electrode of a PMOS transistor, and threshold voltages of the NMOS transistor and the PMOS transistor are respectively
Figure QLYQS_4
and
Figure QLYQS_5
；
Voltage (V)
Figure QLYQS_6
Controlling single-pole double-throw openingWhether or not the switch is open, when->
Figure QLYQS_7
The PMOS transistor is turned on, and the input voltage of the circuit is +.>
Figure QLYQS_8
Programming voltage->
Figure QLYQS_9
Programming the memristor applied at both ends; when->
Figure QLYQS_10
The NMOS transistor is turned on, and the input voltage of the circuit is +.>
Figure QLYQS_11
The circuit enters a calculation process;
converting the rule into a mapping relation between fuzzy sets through an inference engine module, wherein the mapping relation specifically comprises the following steps:
the reasoning engine module consists of a back-piece parameter weight unit, an operational amplifier, a multiplier and a resistor, and the calculation expression of the reasoning engine module is as follows:
Figure QLYQS_12
；
wherein ,
Figure QLYQS_13
indicate->
Figure QLYQS_14
Weight value of bar rule +.>
Figure QLYQS_15
Representing a weighted average sum of the input variables +.>
Figure QLYQS_16
Representing the weight of a back-piece parameter, i.eWeight of each input variable, +.>
Figure QLYQS_17
Representing the dimension of the input variable ∈>
Figure QLYQS_18
Representing the final output result of the memristor fuzzy logic circuit;
the back-piece parameter weight unit consists of two memristors which are connected in reverse direction and a single-pole double-throw switch, and is specifically as follows:
defining according to the fact that the memristor and the single-pole double-throw switch judge that the back-piece parameter weight unit enters a programming process or a calculating process
Figure QLYQS_19
and
Figure QLYQS_20
For the conductance values of two memristors, the conductance value of the memristor during programming is +.>
Figure QLYQS_21
and
Figure QLYQS_22
Difference between them
Figure QLYQS_23
Is positive or negative; />
The back-part parameter weight unit weights back-part parameters in the calculation process
Figure QLYQS_24
The calculated expression of the adjustment of (c) is:
Figure QLYQS_25
；
wherein ,
Figure QLYQS_26
，
Figure QLYQS_27
representing the feedback resistance of the operational amplifier, +.>
Figure QLYQS_28
Representing the input signal>
Figure QLYQS_29
Representing the output signal.
2. The method for designing a fuzzy logic full hardware computing circuit according to claim 1, wherein the memristor array programming is specifically:
when the PMOS transistor is turned on and the NMOS transistor is turned off, the memristor array circuit enters a programming operation process, and each memristor in the memristor array circuit is programmed in parallel in the programming operation process, wherein the memristor is turned off
Figure QLYQS_30
By an input pulse voltage greater than the memristor threshold voltage +.>
Figure QLYQS_31
Independently adjusting;
definition of the definition
Figure QLYQS_32
and
Figure QLYQS_33
Is two fuzzy sets on the input field, +.>
Figure QLYQS_34
and
Figure QLYQS_35
Respectively represent membership functions thereof, wherein ∈>
Figure QLYQS_36
In the vertical wire->
Figure QLYQS_37
Resistance value of memristor corresponding to the upper part +.>
Figure QLYQS_38
The programming expression of (2) is:
Figure QLYQS_39
；
wherein
Figure QLYQS_40
Feedback resistor representing operational amplifier, +.>
Figure QLYQS_41
Representing membership functions->
Figure QLYQS_42
In the vertical wire->
Figure QLYQS_43
Membership in the list;
other membership degrees on memristive array circuit
Figure QLYQS_44
Memristance value of 0 is set to +.>
Figure QLYQS_45
，
Figure QLYQS_46
Applying positive and negative voltage signals to single memristors for maximum resistance of the memristors, and realizing resistance of the memristors under the stimulation of positive and negative voltages
Figure QLYQS_47
Variations within the scope.
3. The method for designing a fuzzy logic full hardware computing circuit according to claim 1, wherein the memristor array is computed specifically as follows:
when the NMOS transistor is turned on and the PMOS transistor is turned off, the memristor array circuit enters a calculation process to define
Figure QLYQS_48
and
Figure QLYQS_49
Is two fuzzy sets on the input field, +.>
Figure QLYQS_50
and
Figure QLYQS_51
Respectively representing membership functions thereof;
pulse voltages which do not exceed the threshold voltage of the memristor are respectively input to the input end of the memristor array, memristor array calculation is carried out, and the expression of the memristor array calculation is as follows:
Figure QLYQS_52
；
wherein ,
Figure QLYQS_53
input representing a certain column of memristive array circuitry, < >>
Figure QLYQS_54
Output representing a certain row of the memristive array, +.>
Figure QLYQS_55
Representing the feedback resistance of the operational amplifier, +.>
Figure QLYQS_56
Representing the memristance of the memristive array cross-point.
4. The method for designing a fuzzy logic full hardware computing circuit according to claim 1, wherein a fuzzy rule base module is constructed, the membership is used as an input of the fuzzy rule base module, and the fuzzy rule and rule weight are obtained, specifically:
after the blurring processing, the membership degree is output and is used as the input of a blurring rule base module, wherein the blurring rule base module consists of an operational amplifier, a resistor, a multiplier and a divider, and the calculation expression is as follows:
Figure QLYQS_57
；
wherein ,
Figure QLYQS_58
indicate->
Figure QLYQS_59
Bar fuzzy rule pair input->
Figure QLYQS_60
Membership of->
Figure QLYQS_61
Representing the membership product corresponding to the kth rule, +.>
Figure QLYQS_62
Represent the firstkWeight value of bar rule +.>
Figure QLYQS_63
Representing the dimensions of the input variables.
5. A fuzzy logic full hardware computing circuit obtained by the design method of the fuzzy logic full hardware computing circuit according to any one of claims 1-4, which is characterized by comprising a fuzzification module, a fuzzy rule base module and an inference engine module;
the blurring module is a memristor array structure formed by memristors, the memristor array structure is formed by two groups of parallel wires which are mutually perpendicular, one memristor at each intersection is connected with two intersection wires, and a double CMOS control switch is adopted to construct a membership function storage circuit of full parallel programming; memristance is determined by applying appropriate voltages to
Figure QLYQS_64
Is->
Figure QLYQS_65
Each row is connected with the negative end of an operational amplifier, and the operational amplifier is provided with a fixed resistor Rf as a feedback resistor;
the fuzzy rule base module consists of an operational amplifier, a resistor, a multiplier and a divider, wherein the divider is used for placing the analog multiplier in a negative feedback loop of the operational amplifier to form a division operation circuit;
the reasoning engine module consists of a back-piece parameter weight unit, an operational amplifier, a multiplier and a resistor, wherein the back-piece parameter weight unit consists of two memristors which are connected in opposite directions and a single-pole double-throw switch, and the real-time adjustment of the positive and negative back-piece parameter weights is realized.
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