CN115840486B - Curvature compensation band gap reference circuit - Google Patents

Abstract

The present invention discloses a curvature compensation bandgap reference circuit, including a startup circuit for making the circuit leave the zero state point and enter the working state; a first-order temperature compensation bandgap reference unit for generating a positive temperature coefficient current and a negative temperature coefficient current, and summing them to eliminate the first-order term related to temperature in the bandgap reference voltage; a second-order temperature compensation bandgap reference unit for generating a compensation current to eliminate the second-order term of the bandgap reference voltage. The curvature compensation bandgap reference circuit provided by the present invention can eliminate the first-order term and the second-order term related to temperature in the output reference voltage, reduce the temperature drift coefficient, and enhance the stability of the circuit through a negative feedback structure, so as to obtain a higher power supply rejection ratio and good temperature characteristics in a wider temperature range.

Description

A curvature compensation bandgap reference circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and in particular relates to a curvature compensation bandgap reference circuit.

Background Art

The bandgap reference circuit is a basic module in the field of analog integrated circuit design. Its function is to provide a reference voltage for the overall circuit that varies very little with external factors. The voltage should have good temperature stability and a high power supply rejection ratio, that is, it should vary little with temperature and power supply voltage.

The traditional bandgap reference circuit uses bipolar junction transistors (BJTs) and op amp clamping technology to obtain a current IPTAT that is positively correlated with temperature and a current ICTAT that is negatively correlated with temperature. The two are then added and multiplied by the resistor to obtain the reference voltage. This solution eliminates the first-order term of the temperature coefficient.

However, the above method only performs first-order compensation on the temperature characteristic curve, and the obtained reference voltage still contains high-order terms related to temperature, so the temperature characteristic curve presents a parabolic shape dominated by quadratic terms. The temperature coefficient of this reference voltage is generally still a dozen or dozens after calculation, which is generally difficult to meet the high stability requirements put forward in the design of high-precision analog integrated circuits.

Summary of the invention

In order to solve the above problems existing in the prior art, the present invention provides a curvature compensation bandgap reference circuit. The technical problem to be solved by the present invention is achieved by the following technical solution:

A curvature-compensated bandgap reference circuit, comprising:

The starting circuit is used to make the circuit leave the zero state point and enter the working state;

A first-order temperature-compensated bandgap reference unit for generating a positive temperature coefficient current and a negative temperature coefficient current and summing them to eliminate a first-order term related to temperature in a bandgap reference voltage;

The second-order temperature-compensated bandgap reference unit is used to generate a compensation current to eliminate the second term of the bandgap reference voltage.

In one embodiment of the present invention, the startup circuit includes a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1 and an NMOS transistor NM2; wherein,

The source of the PMOS transistor PM1 is connected to the power supply voltage VDD terminal, and the gate and drain thereof are connected and commonly connected to the source of the PMOS transistor PM2;

The gate and drain of the PMOS tube PM2, the drain of the NMOS tube NM1, and the gate of the NMOS tube NM2 are connected;

The gate of the NMOS tube NM1 is connected to the bandgap reference output voltage vref;

The source of the NMOS tube NM1 and the source of the NMOS tube NM2 are both connected to a common ground terminal;

The drain of the NMOS tube NM2 is connected to the input end of the first-order temperature compensation bandgap reference unit as the output end of the startup circuit.

In one embodiment of the present invention, the first-order temperature compensation bandgap reference unit includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1 and a PNP transistor Q2; wherein,

The gate of the PMOS tube PM3, the gate of the PMOS tube PM4 and the gate of the PMOS tube PM5 are connected to each other and then used as the input end of the first-order temperature compensation bandgap reference unit to be connected to the output end of the startup circuit;

The source of the PMOS tube PM3, the source of the PMOS tube PM4 and the source of the PMOS tube PM5 are all connected to the power supply voltage VDD terminal;

The drain of the PMOS transistor PM3 is connected to the positive input terminal VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter of the PNP transistor Q1;

The drain of the PMOS tube PM4 is connected to the negative input terminal VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;

The other end of the resistor R0 is connected to the emitter of the PNP transistor Q2;

The output terminal VOUT of the operational amplifier OPA1 is connected to the gate of the PMOS transistor PM3, the gate of the PMOS transistor PM4 and the gate of the PMOS transistor PM5;

The other end of the resistor R1, the base and collector of the PNP transistor Q1, the base and collector of the PNP transistor Q2, and the other end of the resistor R2 are all connected to a common ground;

The drain of the PMOS tube PM5 is connected to the common ground through the resistor R3, and the drain of the PMOS tube PM5 is connected to the input end of the second-order temperature compensation bandgap reference unit as the output end of the first-order temperature compensation bandgap reference unit;

The drain of the PMOS transistor PM5 also serves as an output terminal of the bandgap reference circuit to output a bandgap reference voltage vref.

In one embodiment of the present invention, the operational amplifier OPA1 includes a PMOS transistor PM2-1, a PMOS transistor PM2-2, a PMOS transistor PM2-3, a PMOS transistor PM2-4, a PMOS transistor PM2-5, a PMOS transistor PM2-6, an NMOS transistor NM2-1, an NMOS transistor NM2-2, an NMOS transistor NM2-3, an NMOS transistor NM2-4, an NMOS transistor NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,

The source of the PMOS tube PM2-1, the source of the PMOS tube PM2-2, the source of the PMOS tube PM2-3 and the source of the PMOS tube PM2-6 are all connected to the power supply voltage VDD terminal;

The drain of the PMOS tube PM2-1, the drain and gate of the NMOS tube NM2-1, and the gate of the NMOS tube NM2-2 are connected;

The gate of the PMOS tube PM2-1, the gate and drain of the PMOS tube PM2-2, the drain of the NMOS tube NM2-2, the gate of the PMOS tube PM2-3 and the gate of the PMOS tube PM2-6 are connected;

The source of the NMOS tube NM2-2 is connected to the common ground through the resistor R2-1;

The drain of the PMOS tube PM2-3 is connected to the source of the PMOS tube PM2-4 and the source of the PMOS tube PM2-5;

The drain of the PMOS tube PM2-4, the drain and gate of the NMOS tube NM2-3, and the gate of the NMOS tube NM2-4 are connected;

The gate of the PMOS tube PM2-4 serves as the negative input terminal VIN of the operational amplifier OPA1;

The drain of the PMOS transistor PM2-5 is connected to the drain of the NMOS transistor NM2-4, one end of the capacitor C2-1 and the gate of the NMOS transistor NM2-5;

The other end of the capacitor C2-1 is connected to the drain of the NMOS transistor NM2-5 through the resistor R2-2;

The gate of the PMOS tube PM2-5 serves as the positive input terminal VIP of the operational amplifier OPA1;

The drain of the PMOS tube PM2-6 is connected to the drain of the NMOS tube NM2-5 and serves as the output terminal VOUT of the operational amplifier OPA1;

The source of the NMOS transistor NM2 - 1 , the source of the NMOS transistor NM2 - 3 , the source of the NMOS transistor NM2 - 4 , and the source of the NMOS transistor NM2 - 5 are all connected to a common ground terminal.

In one embodiment of the present invention, the sizes of the PMOS transistor PM3, the PMOS transistor PM4 and the PMOS transistor PM5 are equal.

In one embodiment of the present invention, the second-order temperature compensation bandgap reference unit includes a PMOS transistor PM6, an operational amplifier OPA2, an NMOS transistor NM3, a capacitor C1, a resistor R4 and a resistor R5; wherein,

The source of the PMOS tube PM6 is connected to the power supply voltage VDD terminal, the gate thereof is connected to the output terminal VOUT of the operational amplifier OPA2, and the drain thereof is connected to the positive input terminal VIP of the operational amplifier OPA2;

The negative input terminal VIN of the operational amplifier OPA2 is connected to the drain of the NMOS tube NM3, and is connected to the output terminal of the first-order temperature compensation bandgap reference unit as the input terminal of the second-order temperature compensation bandgap reference unit;

The capacitor C1 is connected between the drain and the gate of the NMOS tube NM3;

The drain of the NMOS tube NM3 is connected to the common ground;

The resistor R4 and the resistor R5 are connected in series between the drain of the PMOS tube PM6 and the common ground terminal;

The gate of the NMOS transistor NM3 is also connected to the common end of the resistor R4 and the resistor R5.

In one embodiment of the present invention, the operational amplifier OPA2 includes a PMOS transistor PM2-1, a PMOS transistor PM2-2, a PMOS transistor PM2-3, a PMOS transistor PM2-4, a PMOS transistor PM2-5, a PMOS transistor PM2-6, an NMOS transistor NM2-1, an NMOS transistor NM2-2, an NMOS transistor NM2-3, an NMOS transistor NM2-4, an NMOS transistor NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,

The source of the PMOS tube PM2-1, the source of the PMOS tube PM2-2, the source of the PMOS tube PM2-3 and the source of the PMOS tube PM2-6 are all connected to the power supply voltage VDD terminal;

The drain of the PMOS tube PM2-1, the drain and gate of the NMOS tube NM2-1, and the gate of the NMOS tube NM2-2 are connected;

The gate of the PMOS tube PM2-1, the gate and drain of the PMOS tube PM2-2, the drain of the NMOS tube NM2-2, the gate of the PMOS tube PM2-3 and the gate of the PMOS tube PM2-6 are connected;

The source of the NMOS tube NM2-2 is connected to the common ground through the resistor R2-1;

The drain of the PMOS tube PM2-3 is connected to the source of the PMOS tube PM2-4 and the source of the PMOS tube PM2-5;

The drain of the PMOS tube PM2-4, the drain and gate of the NMOS tube NM2-3, and the gate of the NMOS tube NM2-4 are connected;

The gate of the PMOS tube PM2-4 serves as the negative input terminal VIN of the operational amplifier OPA2;

The drain of the PMOS transistor PM2-5 is connected to the drain of the NMOS transistor NM2-4, one end of the capacitor C2-1 and the gate of the NMOS transistor NM2-5;

The other end of the capacitor C2-1 is connected to the drain of the NMOS transistor NM2-5 through the resistor R2-2;

The gate of the PMOS tube PM2-5 serves as the positive input terminal VIP of the operational amplifier OPA2;

The drain of the PMOS tube PM2-6 is connected to the drain of the NMOS tube NM2-5 and serves as the output terminal VOUT of the operational amplifier OPA2;

The source of the NMOS transistor NM2 - 1 , the source of the NMOS transistor NM2 - 3 , the source of the NMOS transistor NM2 - 4 , and the source of the NMOS transistor NM2 - 5 are all connected to a common ground terminal.

Beneficial effects of the present invention:

1. The curvature compensation bandgap reference circuit provided by the present invention uses a first-order temperature compensation bandgap reference unit to generate a bandgap reference voltage that does not contain a first-order term related to temperature, and uses a second-order temperature compensation bandgap reference unit to generate a compensation current to eliminate the second-order term related to temperature in the reference voltage, thereby obtaining a lower temperature drift coefficient;

2. The second-order temperature compensation bandgap reference unit in the curvature compensation bandgap reference circuit provided by the present invention also constitutes a negative feedback structure. When the bandgap reference voltage vref changes significantly due to external factors, the negative feedback structure can be used to keep it stable, thereby further obtaining a lower temperature drift coefficient and a higher power supply rejection ratio.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a curvature compensation bandgap reference circuit provided by an embodiment of the present invention;

FIG2 is a schematic diagram of the structure of an operational amplifier provided in an embodiment of the present invention;

3 is a test result diagram of the variation of the bandgap reference voltage output by the curvature compensation bandgap reference circuit with temperature according to an embodiment of the present invention;

FIG. 4 is a test result diagram showing the variation of the power supply rejection ratio of the curvature-compensated bandgap reference circuit with frequency according to an embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Embodiment 1

Please refer to FIG. 1 , which is a schematic diagram of the structure of a curvature (second-order) compensation bandgap reference circuit provided by an embodiment of the present invention, which includes:

The starting circuit 1 is used to make the circuit leave the zero state point and enter the working state;

A first-order temperature-compensated bandgap reference unit 2, used for generating a positive temperature coefficient current and a negative temperature coefficient current, and summing them to eliminate a first-order term related to temperature in a bandgap reference voltage;

The second-order temperature-compensated bandgap reference unit 3 is used to generate a compensation current to eliminate the second term of the bandgap reference voltage.

Specifically, in this embodiment, the startup circuit 1 includes a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1 and an NMOS transistor NM2; wherein,

The source of the PMOS transistor PM1 is connected to the power supply voltage VDD terminal, and the gate and drain thereof are connected and commonly connected to the source of the PMOS transistor PM2;

The gate and drain of the PMOS tube PM2, the drain of the NMOS tube NM1, and the gate of the NMOS tube NM2 are connected;

The gate of the NMOS tube NM1 is connected to the bandgap reference output voltage vref;

The source of the NMOS tube NM1 and the source of the NMOS tube NM2 are both connected to a common ground terminal;

The drain of the NMOS tube NM2 is connected to the input end of the first-order temperature compensation bandgap reference unit 2 as the output end of the startup circuit 1 .

Further, please continue to refer to FIG. 1 , wherein the first-order temperature compensation bandgap reference unit 2 includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1, and a PNP transistor Q2; wherein,

The gate of the PMOS transistor PM3, the gate of the PMOS transistor PM4 and the gate of the PMOS transistor PM5 are connected to each other and then connected to the output end of the start-up circuit 1 as the input end of the first-order temperature compensation bandgap reference unit 2;

The source of the PMOS tube PM3, the source of the PMOS tube PM4 and the source of the PMOS tube PM5 are all connected to the power supply voltage VDD terminal;

The drain of the PMOS tube PM3 is connected to the positive input terminal VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter of the PNP transistor Q1;

The drain of the PMOS tube PM4 is connected to the negative input terminal VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;

The other end of the resistor R0 is connected to the emitter of the PNP transistor Q2;

The output terminal VOUT of the operational amplifier OPA1 is connected to the gate of the PMOS transistor PM3, the gate of the PMOS transistor PM4 and the gate of the PMOS transistor PM5;

The other end of the resistor R1, the base and collector of the PNP transistor Q1, the base and collector of the PNP transistor Q2, and the other end of the resistor R2 are all connected to a common ground;

The drain of the PMOS tube PM5 is connected to the common ground terminal through the resistor R3, and the drain of the PMOS tube PM5 is connected to the input terminal of the second-order temperature compensation bandgap reference unit 3 as the output terminal of the first-order temperature compensation bandgap reference unit 2;

The drain of the PMOS transistor PM5 also serves as an output terminal of the bandgap reference circuit to output a bandgap reference voltage vref.

In this embodiment, the operational amplifier OPA1 adopts a two-stage amplification structure, which can obtain a higher gain, a better clamping effect, and a higher power supply rejection ratio.

For example, the operational amplifier structure shown in FIG2 may be used in this embodiment to implement the operational amplifier OPA1 in the first-order temperature compensation bandgap reference unit 2. Specifically, it includes: PMOS transistor PM2-1, PMOS transistor PM2-2, PMOS transistor PM2-3, PMOS transistor PM2-4, PMOS transistor PM2-5, PMOS transistor PM2-6, NMOS transistor NM2-1, NMOS transistor NM2-2, NMOS transistor NM2-3, NMOS transistor NM2-4, NMOS transistor NM2-5, capacitor C2-1, resistor R2-1 and resistor R2-2; wherein,

The source of the PMOS tube PM2-1, the source of the PMOS tube PM2-2, the source of the PMOS tube PM2-3 and the source of the PMOS tube PM2-6 are all connected to the power supply voltage VDD terminal;

The drain of the PMOS tube PM2-1, the drain and gate of the NMOS tube NM2-1, and the gate of the NMOS tube NM2-2 are connected;

The gate of the PMOS tube PM2-1, the gate and drain of the PMOS tube PM2-2, the drain of the NMOS tube NM2-2, the gate of the PMOS tube PM2-3 and the gate of the PMOS tube PM2-6 are connected;

The source of the NMOS tube NM2-2 is connected to the common ground through the resistor R2-1;

The drain of the PMOS tube PM2-3 is connected to the source of the PMOS tube PM2-4 and the source of the PMOS tube PM2-5;

The drain of the PMOS tube PM2-4, the drain and gate of the NMOS tube NM2-3, and the gate of the NMOS tube NM2-4 are connected;

The gate of the PMOS tube PM2-4 serves as the negative input terminal VIN of the operational amplifier OPA1;

The drain of the PMOS transistor PM2-5 is connected to the drain of the NMOS transistor NM2-4, one end of the capacitor C2-1 and the gate of the NMOS transistor NM2-5;

The other end of the capacitor C2-1 is connected to the drain of the NMOS tube NM2-5 through the resistor R2-2;

The gate of the PMOS tube PM2-5 serves as the positive input terminal VIP of the operational amplifier OPA1;

The drain of the PMOS tube PM2-6 is connected to the drain of the NMOS tube NM2-5 and serves as the output terminal VOUT of the operational amplifier OPA1;

The source of the NMOS transistor NM2 - 1 , the source of the NMOS transistor NM2 - 3 , the source of the NMOS transistor NM2 - 4 , and the source of the NMOS transistor NM2 - 5 are all connected to the common ground terminal.

Further, please continue to refer to FIG. 1 , wherein the second-order temperature compensation bandgap reference unit 3 includes a PMOS transistor PM6 , an operational amplifier OPA2 , an NMOS transistor NM3 , a capacitor C1 , a resistor R4 and a resistor R5 ; wherein,

The source of the PMOS tube PM6 is connected to the power supply voltage VDD terminal, the gate thereof is connected to the output terminal VOUT of the operational amplifier OPA2, and the drain thereof is connected to the positive input terminal VIP of the operational amplifier OPA2;

The negative input terminal VIN of the operational amplifier OPA2 is connected to the drain of the NMOS tube NM3 and is connected to the output terminal of the first-order temperature compensation bandgap reference unit 2 as the input terminal of the second-order temperature compensation bandgap reference unit (3);

The capacitor C1 is connected between the drain and the gate of the NMOS tube NM3;

The drain of the NMOS tube NM3 is connected to the common ground terminal;

The resistor R4 and the resistor R5 are connected in series between the drain of the PMOS tube PM6 and the common ground terminal;

The gate of the NMOS tube NM3 is also connected to the common end of the resistor R4 and the resistor R5.

In this embodiment, the operational amplifier OPA2 can adopt the same circuit structure as the operational amplifier OPA1, that is, the circuit structure shown in Figure 2. In Figure 2, the gate of the PMOS tube PM2-4 serves as the negative input terminal VIN of the operational amplifier OPA2, the gate of the PMOS tube PM2-5 serves as the positive input terminal VIP of the operational amplifier OPA2, and the drain of the PMOS tube PM2-6 is connected to the drain of the NMOS tube NM2-5 and serves as the output terminal VOUT of the operational amplifier OPA2.

The working principle of the curvature compensation bandgap reference circuit provided in this embodiment is as follows:

In the startup circuit, when power is turned on, the gate voltage of the NMOS tube NM2 becomes high potential, pulling down the gate potentials of the PMOS tubes PM3 and PM4, and the first-order temperature compensation bandgap reference unit starts to work. Then the output reference voltage vref controls the NMOS tube NM1 to turn it on, thereby pulling down the gate potential of the NMOS tube NM2 to turn off the NMOS tube NM2, completing the startup process.

In the first-order temperature-compensated bandgap reference unit, through the clamping action of the operational amplifier OPA1, the potentials of its positive and negative input terminals are equal, and the current flowing through the resistor R2 is a negative temperature coefficient current ICTAT:

Wherein, V _be1 is the base-emitter voltage of the PNP transistor Q1.

The current flowing through resistor R0 is a positive temperature coefficient current:

Among them, _Vbe2 is the base-emitter voltage of PNP transistor Q2, _VT is the transistor thermal voltage, _I0 and _NI0 are the collector currents of PNP transistor Q1 and PNP transistor Q2 respectively, _IS1 and _IS2 are the saturation currents of PNP transistor Q1 and PNP transistor Q2 respectively, and N is the ratio of the emitter area of PNP transistor Q2 to that of PNP transistor Q1.

In this embodiment, the sizes of PMOS transistors PM3, PM4 and PM5 are equal, so that the currents in the branches where the three PMOS transistors are located are equal, which are all the sum of the positive temperature coefficient current and the negative temperature coefficient current, that is, the current does not contain a first-order term related to temperature.

In the second-order temperature-compensated bandgap reference unit, through the clamping effect of the operational amplifier OPA2, the potentials of its positive and negative input terminals are equal, that is, the potential of its positive input terminal is equal to the bandgap reference output voltage vref. By adjusting the size of the resistor R4 and the resistor R5, the NMOS tube NM3 works in the saturation region, and the current _I1 flowing through the NMOS tube NM3 is:

Wherein, μ _N is the carrier mobility of the NMOS tube, _Cox is the gate oxide capacitance per unit area, W is the width of the NMOS tube NM3, L is the length of the NMOS tube NM3, and V _TH is the threshold voltage of the NMOS tube NM3.

The vref voltage formula is:

From this formula, vref can be further expressed as:

Among them, k is _I0 is the sum of the positive temperature coefficient current _IPTAT and the negative temperature coefficient current _ICTAT , and contains a quadratic term related to temperature.

Therefore, the first-order temperature relationship in _VTH can be used to eliminate the second-order relationship between vref and temperature in the above formula, thereby obtaining a lower temperature drift coefficient.

In addition, the second-order temperature compensated bandgap reference unit also forms a negative feedback loop, that is, the operational amplifier OPA2, the PMOS tube PM6, the resistor R4, the capacitor C1 and the NMOS tube NM3 form a negative feedback structure, which can improve the stability of the circuit. When the output bandgap reference voltage vref changes greatly due to temperature increase or other external factors, the current of the NMOS tube NM3 will increase, thereby drawing away the current flowing through the resistor R3, so that the output bandgap reference voltage vref is reduced and remains stable, further reducing the temperature drift coefficient and greatly improving the power supply rejection ratio.

In order to further verify the beneficial effects of the present invention, this embodiment also tests the variation of the bandgap reference voltage of the curvature-compensated bandgap reference circuit with temperature and the variation of the power supply rejection ratio with frequency, and the results are shown in Figures 3 and 4. Among them, Figure 3 is a test result diagram of the variation of the bandgap reference voltage output by the curvature-compensated bandgap reference circuit provided by the embodiment of the present invention with temperature, which mainly shows the temperature characteristic curve of the output reference voltage in a wider temperature variation range (-40°C to 160°C). The results show that the temperature drift coefficient of the curvature-compensated bandgap reference circuit provided by the present invention can be as low as 00440000°C. In addition, it can be seen from Figure 3 that the reference voltage remains stable within the range of -40°C to 160°C, and the voltage only changes by 10607uV, which shows that the bandgap reference voltage output by the present invention can remain stable within a wider temperature range.

Figure 4 is a test result diagram of the power supply rejection ratio of the curvature compensation bandgap reference circuit provided by the embodiment of the present invention as a function of frequency. As can be seen from Figure 4, at low frequency, the power supply rejection ratio of the present invention is -77dB, indicating that the present invention has a higher power supply rejection ratio.

In summary, the curvature compensated bandgap reference circuit provided by the present invention can eliminate the first-order and second-order terms related to temperature in the output reference voltage, reduce the temperature drift coefficient, and enhance the stability of the circuit through the negative feedback structure, thereby obtaining a higher power supply rejection ratio and good temperature characteristics in a wider temperature range.

In another embodiment of the present invention, the operational amplifier OPA2 in the second-order temperature compensation bandgap reference unit 3 can also be replaced by a common source and common gate negative feedback structure, which can also achieve a clamping effect, thereby obtaining a voltage that is the same as the output reference voltage change to control the gate of the NMOS tube NM3. The specific implementation process will not be described in detail here.

The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims (2)

1. A curvature compensated bandgap reference circuit, comprising:

The starting circuit (1) is used for enabling the circuit to be separated from a zero state point and enter a working state;

a first-order temperature compensated bandgap reference unit (2) for generating a positive temperature coefficient current and a negative temperature coefficient current and summing to eliminate a temperature dependent primary term in the bandgap reference voltage;

a second-order temperature-compensated bandgap reference unit (3) for generating a compensation current to cancel two terms of the bandgap reference voltage;

The starting circuit (1) comprises a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1 and an NMOS tube NM2; wherein,

The source electrode of the PMOS tube PM1 is connected with the power supply voltage VDD end, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected and commonly connected with the source electrode of the PMOS tube PM 2;

The grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;

the grid electrode of the NMOS tube NM1 is connected with a band gap reference output voltage vref;

The source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground terminal;

The drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit (1) to be connected with the input end of the first-order temperature compensation band gap reference unit (2);

the first-order temperature compensation band gap reference unit (2) comprises a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP type transistor Q1 and a PNP type transistor Q2; wherein,

The grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then used as the input end of the first-order temperature compensation band gap reference unit (2) to be connected with the output end of the starting circuit (1);

the source electrode of the PMOS tube PM3, the source electrode of the PMOS tube PM4 and the source electrode of the PMOS tube PM5 are all connected with a power supply voltage VDD end;

The drain electrode of the PMOS tube PM3 is connected with the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter electrode of the PNP transistor Q1;

the drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;

The other end of the resistor R0 is connected with the emitter of the PNP transistor Q2;

the output end VOUT of the operational amplifier OPA1 is connected to the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM 5;

The other end of the resistor R1, the base and collector of the PNP type transistor Q2 and the other end of the resistor R2 are all connected to a common ground terminal;

The drain electrode of the PMOS tube PM5 is connected with a common ground end through the resistor R3, and the drain electrode of the PMOS tube PM5 is used as the output end of the first-order temperature compensation band gap reference unit (2) to be connected with the input end of the second-order temperature compensation band gap reference unit (3);

The drain electrode of the PMOS tube PM5 is also used as the output end of the band-gap reference circuit to output band-gap reference voltage vref;

The operational amplifier OPA1 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,

The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;

the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;

the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;

The source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;

the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;

the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;

the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 1;

the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;

the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;

the grid electrode of the PMOS tube PM2-5 is used as a positive input end VIP of the operational amplifier OPA 1;

The drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;

The source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground terminal;

The second-order temperature compensation band gap reference unit (3) comprises a PMOS tube PM6, an operational amplifier OPA2, an NMOS tube NM3, a capacitor C1, a resistor R4 and a resistor R5; wherein,

The source electrode of the PMOS tube PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS tube PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS tube PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;

The negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3 and is used as the input end of the second-order temperature compensation band gap reference unit (3) to be connected with the output end of the first-order temperature compensation band gap reference unit (2);

the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;

the drain electrode of the NMOS tube NM3 is connected with a common ground terminal;

the resistor R4 and the resistor R5 are connected in series between the drain electrode of the PMOS tube PM6 and the common ground;

The grid electrode of the NMOS tube NM3 is also connected with the common end of the resistor R4 and the resistor R5;

The operational amplifier OPA2 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,

The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;

the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;

the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;

The source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;

the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;

the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;

the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 2;

the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;

the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;

The grid electrode of the PMOS tube PM2-5 is used as a positive input end VIP of the operational amplifier OPA 2;

The drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 2;

The source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground terminal.

2. The curvature compensated bandgap reference circuit of claim 1, wherein said PMOS tube PM3, said PMOS tube PM4 and said PMOS tube PM5 are equal in size.