CN115792580B - Chip detection system and editable chip detection system - Google Patents
Chip detection system and editable chip detection system Download PDFInfo
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- CN115792580B CN115792580B CN202310045789.1A CN202310045789A CN115792580B CN 115792580 B CN115792580 B CN 115792580B CN 202310045789 A CN202310045789 A CN 202310045789A CN 115792580 B CN115792580 B CN 115792580B
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Abstract
The application provides a chip detection system and an editable chip detection system, wherein a data processing module, a storage module and a comparison module are arranged on a circuit board; the data processing module is preset with a scheduling instruction set, the storage module is used for storing detection data transmitted by the data processing module, and the comparison module is preset with verification data; the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, and the comparison module compares the output data of the chip to be tested with preset verification data. The data processing module, the storage module and the comparison module are arranged on the circuit board, so that the influence on the detection efficiency of the chip due to low transmission rate of an external interface and low transmission rate of wires is avoided, and the transmission efficiency is greatly improved. The storage module dispatches corresponding detection data to the chip to be detected according to different dispatching instructions, and the dispatching of the detection data is quicker.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a chip inspection system and an editable chip inspection system.
Background
In the last decades, the performance of a chip can be doubled every 18 months in the semiconductor industry according to moore's law, and the quality requirements on the chip are more and more strict along with the continuous improvement of the performance of the chip, especially the high-end chip is often low in yield, so that the chip still needs to be detected after production.
In the traditional chip detection technology, a comprehensive verification code is compiled by constructing a software function test platform, the design is needed according to an implementation block diagram of the software function test platform, an external computer inputs detection data to a chip to be detected, the operation detection data of the chip to be detected obtain output data, the output data is transmitted to the external computer and is compared with the known verification data, and finally, a set of system platform capable of carrying out hardware function test on the chip is completed.
Because the transmission speed of the data is affected by the connection wire, the interface speed and the like, the upper limit of the transmission speed of the data is not high, and the traditional chip detection technology is suitable for chip detection with low transmission speed at the middle and low ends. When a high-end chip to be tested or a plurality of chips to be tested are tested simultaneously, the transmission data amount is large, and the upper limit of the transmission rate of the connecting wire, the interface and the like can limit the efficiency of chip detection, so that the detection efficiency is limited.
Disclosure of Invention
An object of the embodiment of the application is to provide a chip detection system and an editable chip detection system, which are used for realizing the technical effect of high-speed chip detection.
A first embodiment of the present application provides a chip detection system, including: the data processing module, the storage module and the comparison module are arranged on the circuit board; the data processing module is preset with a scheduling instruction set, the storage module is used for storing detection data transmitted by the data processing module, and the comparison module is preset with verification data; the data processing module issues a scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, and the comparison module compares output data of the chip to be tested with preset verification data.
In the implementation process, the data processing module is arranged on the circuit board, the storage module is electrically connected with the data processing module, and the comparison module is electrically connected with the storage module and the chip to be tested. The data processing module may be a central processing unit CPU such as RISC-V instructions, a field programmable gate array FPGA or a microprocessor ARM core, the storage module may be a mass storage unit, and the comparison module may be a chip. Before testing, the data processing module is preset with a dispatching instruction set, dispatches the detection data to the storage module for storing the detection data, and the comparison module is preset with verification data. After the test is started, the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, the chip to be tested runs the detection data and outputs the data, the comparison module compares the output data of the chip to be tested with preset verification data, whether the chip has problems or not is judged according to whether the comparison result is consistent, if the result is consistent, the chip has problems, and if the result is inconsistent, the chip has problems. The data processing module, the storage module and the comparison module are all arranged on the circuit board, so that the influence on the detection efficiency of the chip due to low transmission rate of an external interface and low transmission rate of wires is avoided, the whole data processing module, the storage module and the comparison module are integrated on the circuit board, the transmission efficiency is greatly improved, and a plurality of high-end chips can be detected simultaneously. The data processing module is preset with a scheduling instruction set, different scheduling instructions correspondingly schedule different detection data, and during the detection process, the corresponding detection data are scheduled to the chip to be detected according to the different scheduling instructions, so that the detection data are scheduled more rapidly. The integrated chip detection system can also detect a plurality of chips in the same category, other contents do not need to be replaced, and the detection efficiency of the chips is improved.
In one possible implementation manner, an operating system is arranged in the data processing module and is used for generating a scheduling instruction set, detection data and verification data.
In the implementation process, an operating system is arranged in the data processing module, the operating system can be a linux operating system so as to generate a scheduling instruction set, detection data and verification data, the operating system is integrated in the data processing module, the operating instructions and programs can be flexibly written without developing corresponding upper computer software, after different chips to be tested are replaced, a new scheduling instruction set, detection data and verification data are generated in the data processing module through the operating system, the data module transmits the new verification data to the comparison module, and the whole process does not need to replace other modules, so that more flexible test and verification are realized.
In one possible implementation, the data processing module is provided with an interface, which interfaces with an external computer, which external computer is capable of transmitting the set of scheduling instructions, the detection data and the verification data to the data processing module.
In the implementation process, the data processing module is provided with an interface, the interface is connected with the computer, and when other types of chips are required to be detected, the computer can transmit a new scheduling instruction set, detection data and verification data to the data processing module, so that the other types of chips are detected, the other modules are not required to be replaced, and the use is more flexible.
In one possible implementation manner, a matching rate threshold value of the verification data and the output data of the chip to be tested is preset in the comparison module, and when the comparison module detects that the matching rate of the verification data and the output data of the chip to be tested is lower than the matching rate threshold value, the data processing module transmits the output data of the chip to be tested to an external computer, and the external computer compares the output data of the chip to be tested with the verification data again.
In the implementation process, a matching rate threshold value of the output data and the verification data of the chip to be detected is preset in the comparison module, and the matching rate is calculated in the following manner: when the comparison module detects that the matching rate is lower than the matching rate threshold, the error in the chip to be tested is more, the data processing module is required to transmit the output data of the chip to be tested to an external computer, the external computer is internally provided with the verification data, and the output data of the chip to be tested and the verification data are compared again in more detail in the external computer. When the chip errors are more, the chip errors can be compared in more detail in an external computer so as to record the chip error addresses, fault types and the like, and an operator can find the defects of the chip more accurately.
In one possible implementation manner, a temperature detection module is arranged in the comparison module and is used for detecting the current temperature of the comparison module in real time, and when the temperature of the comparison module is higher than a temperature threshold value, the data processing module transmits remaining un-compared output data of the chip to be tested to an external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with verification data.
In the implementation process, the temperature detection module is arranged inside the comparison module, so that the current temperature of the comparison module can be detected in real time, the temperature threshold value is preset for the comparison module before detection, and the comparison efficiency of the comparison module is reduced when the temperature of the comparison module is higher than the preset temperature threshold value. At this time, the comparison module stops comparing, the data processing module transmits the remaining un-compared output data of the chip to be tested to the external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with the verification data, so as to reduce the working strength of the comparison module, avoid the reduction of the comparison efficiency caused by the overhigh temperature of the comparison module, and transfer the comparison place from the comparison module to the external computer, so as to maintain higher comparison efficiency.
The second embodiment of the application provides an editable chip detection system, which is provided with a data processing module, a storage module and a comparison module which are arranged on a circuit board; the data processing module is internally provided with an operating system for generating a scheduling instruction set, detection data and verification data, the storage module is used for storing the detection data transmitted by the data processing module, and the comparison module is pre-provided with the verification data; the data processing module issues a scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, and the comparison module compares output data of the chip to be tested with preset verification data.
In the implementation process, the data processing module is arranged on the circuit board, the storage module is electrically connected with the data processing module, and the comparison module is electrically connected with the storage module and the chip to be tested. The data processing module may be a Central Processing Unit (CPU) such as a RISC-V instruction set, a Field Programmable Gate Array (FPGA) or a microprocessor (ARM) core, the storage module may be a mass storage unit, and the comparison module may be a chip. Before chip testing, the data processing module is preset with a dispatching instruction set, dispatches the detection data to the storage module for storing the detection data, and the comparison module is preset with verification data. After the test is started, the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, the chip to be tested runs the detection data and outputs the data, the comparison module compares the output data of the chip to be tested with preset verification data, whether the chip has problems or not is judged according to whether the comparison result is consistent, if the result is consistent, the chip has problems, and if the result is inconsistent, the chip has problems. The data processing module, the storage module and the comparison module are all arranged on the circuit board, so that the influence on the detection efficiency of the chip due to low transmission rate of an external interface and low transmission rate of wires is avoided, the whole data processing module, the storage module and the comparison module are integrated on the circuit board, the transmission efficiency is greatly improved, and a plurality of high-end chips can be detected simultaneously. The data processing module is preset with a scheduling instruction set, different scheduling instructions correspondingly schedule different detection data, and the storage module schedules the detection data corresponding to the different scheduling instructions into the chip to be detected according to the detection data corresponding to the different scheduling instructions during the detection process, so that the detection data is scheduled more rapidly. The integrated chip detection system can also detect a plurality of chips in the same category, other contents do not need to be replaced, and the detection efficiency of the chips is improved. The operation system is arranged in the data processing module, can be a linux operation system, can generate a scheduling instruction set, detection data and verification data, is integrated in the data processing module, can flexibly write operation instructions and programs, does not need to develop corresponding upper computer software, and can generate a new scheduling instruction set, detection data and verification data in the data processing module through the operation system after different chips to be tested are replaced, so that other modules do not need to be replaced, and more flexible test and verification are realized.
In one possible implementation, the data processing module is provided with an interface, which interfaces with an external computer, which external computer is capable of transmitting the set of scheduling instructions, the detection data and the verification data to the data processing module.
In the implementation process, the data processing module is provided with an interface, the interface is connected with the computer, and when other types of chips are required to be detected, the computer can transmit a new scheduling instruction set, detection data and verification data to the data processing module, so that the other types of chips are detected, the other modules are not required to be replaced, and the use is more flexible.
In one possible implementation manner, a matching rate threshold value of the verification data and the output data of the chip to be tested is preset in the comparison module, and when the comparison module detects that the matching rate of the verification data and the output data of the chip to be tested is lower than the matching rate threshold value, the data processing module transmits the output data of the chip to be tested to an external computer, and the external computer compares the output data of the chip to be tested with the verification data again.
In the implementation process, a matching rate threshold value of the output data and the verification data of the chip to be detected is preset in the comparison module, and the matching rate is calculated in the following manner: when the comparison module detects that the matching rate is lower than the matching rate threshold, the error in the chip is more, the data processing module is required to transmit the output data of the chip to be tested to an external computer, the external computer is internally provided with the verification data, and the output data of the chip to be tested and the verification data are compared again in more detail in the external computer. When the chip errors are more, the chip errors can be compared in more detail in an external computer so as to record the chip error addresses, fault types and the like, and an operator can find the defects of the chip more accurately.
In one possible implementation manner, a temperature detection module is arranged in the comparison module and is used for detecting the current temperature of the comparison module in real time, and when the temperature of the comparison module is higher than a temperature threshold value, the data processing module transmits remaining un-compared output data of the chip to be tested to an external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with verification data.
In the implementation process, the temperature detection module is arranged inside the comparison module, so that the current temperature of the comparison module can be detected in real time, the temperature threshold value is preset for the comparison module before detection, and the comparison efficiency of the comparison module is reduced when the temperature of the comparison module is higher than the preset temperature threshold value. At this time, the comparison module stops comparing, the data processing module transmits the remaining un-compared output data of the chip to be tested to the external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with the verification data, so as to reduce the working strength of the comparison module, avoid the reduction of the comparison efficiency caused by the overhigh temperature of the comparison module, and transfer the comparison place from the comparison module to the external computer, so as to maintain higher comparison efficiency.
In one possible implementation manner, when the comparison module detects that the output data of the chip to be tested is consistent with the preset verification data, the data processing module transmits the output data of the chip to be tested to an external computer, and the external computer compares the output data of the chip to be tested with the verification data again.
In the implementation process, when the comparison module detects that the output data of the chip to be tested is consistent with the preset verification data, the detection of the chip to be tested is finished. The output data of the chip to be tested can be transmitted to an external computer through the data processing module, the output data of the chip to be tested and the verification data are compared again by the external computer, and the comparison result is more accurate through the two comparison.
In one possible implementation manner, a scheduling module is arranged in the data processing module, and after the data processing module transmits one section of detection data to the storage module, the scheduling module transmits the next section of detection data to the storage module.
In the implementation process, the scheduling module is arranged in the data processing module, after the data processing module transmits one section of detection data to the storage module, the scheduling module transmits the next section of detection data to the storage module, and the efficiency of the detection data from the data processing module to the storage module is improved through the scheduling of the detection data by the scheduling module.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a chip detection system according to an embodiment of the present application;
fig. 2 is a block diagram of an editable chip detection system according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, an embodiment of the present application provides a chip detection system, please refer to fig. 1, which illustrates a data processing module, a memory module and a comparison module disposed on a circuit board; the data processing module is preset with a scheduling instruction set, the storage module is used for storing detection data transmitted by the data processing module, and the comparison module is preset with verification data; the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, and the comparison module compares the output data of the chip to be tested with preset verification data.
In the implementation process, the data processing module is arranged on the circuit board, the storage module is electrically connected with the data processing module, and the comparison module is electrically connected with the storage module and the chip to be tested. The data processing module may be a central processor CPU (central processing unit) such as a RISC-V instruction set (RISC-V instruction setarchitecture), a field programmable gate array FPGA (Field Programmable Gate Array), or a microprocessor ARM core (Advanced RISC Machine), the memory module may be a mass storage unit, and the alignment module may be a chip. Before chip testing, the data processing module is preset with a dispatching instruction set, dispatches the detection data to the storage module for storing the detection data, and the comparison module is preset with verification data. After the test is started, the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, the chip to be tested runs the detection data and outputs the data, the comparison module compares the output data of the chip to be tested with preset verification data, whether the chip has problems or not is judged according to whether the comparison result is consistent, if the result is consistent, the chip has problems, and if the result is inconsistent, the chip has problems. The data processing module, the storage module and the comparison module are all arranged on the circuit board, so that the influence on the detection efficiency of the chip due to low transmission rate of an external interface and low transmission rate of wires is avoided, the whole data processing module, the storage module and the comparison module are integrated on the circuit board, the transmission efficiency is greatly improved, and a plurality of high-end chips can be detected simultaneously. The data processing module is preset with a scheduling instruction set, and can realize reading, writing, moving, comparing, calculating and batched block operation instructions of data in an instruction mode, wherein the data processing module is divided into two types, one type is operation aiming at single data, and the other type is batched operation aiming at data blocks. Type one: for operation of single data, instruction definition is carried out for reading, writing, moving, comparing and calculating which are most common in chip detection. Default to 32 bits, with the first 4 bits being instruction type definitions; the middle 24 bits are defined for the positions of the operand A, the operand B and the output number C or the data itself; defining a 1-bit operand address or a data switching identifier, which is used for operand address or data switching, when the value is 0, the instruction operation object is considered as the operand address, and when the value is 1, the instruction operation object is considered as the operand address; and reserves 3 bits as reserved bits.
Type two: batch operations for data blocks. In order to increase instruction efficiency, the invention also protects a data block operation-based mode, and instruction block operation definition is carried out aiming at most common reading, writing, moving, comparing and calculating in chip detection. Default to 40 bits, where the first 4 bits are instruction type definitions, the first bits are 1 to distinguish between single data operations of type one; the middle 24 bits are defined for the initial positions of the operation array A, the operation array B and the output array C or the data itself; defining 8 bits as block operation data depth, indicating the number of data of an operand and an output number, and limiting the operand A, B to be consistent with the number of depth of the output number C for the sake of simple definition; defining a 1-bit operand address or data switching identification, which is used for operand address or data switching, and is used for operand address or data switching, when the value is 0, the instruction operation object is considered as an operand starting address, when the value is 1, the instruction operation object is considered as an operand, and only the scene that all operands are consistent is supported at the moment; and reserves 3 bits as reserved bits.
Different scheduling instructions correspondingly schedule different detection data, and during the detection process, the corresponding detection data are scheduled to the chip to be detected according to the different scheduling instructions, so that the detection data are scheduled more rapidly. The integrated chip detection system can also detect a plurality of chips in the same category, other contents do not need to be replaced, and the detection efficiency of the chips is improved.
In one possible implementation, an operating system is provided within the data processing module for generating a set of scheduling instructions, detection data, and verification data.
In the implementation process, an operating system is arranged in the data processing module, the operating system can be a Linux (GNU/Linux) operating system so as to generate a scheduling instruction set, detection data and verification data, the operating system is integrated in the data processing module, the operating instructions and programs can be flexibly written without developing corresponding upper computer software, when different chips to be tested are replaced, a new scheduling instruction set, detection data and verification data are generated in the data processing module through the operating system, the data module transmits the new verification data to the comparison module, and the whole process does not need to replace other modules, so that more flexible test and verification are realized.
With reference to fig. 2, in one possible implementation, the data processing module is provided with an interface, which is connected to an external computer, which is capable of transmitting the set of scheduling instructions, the detection data and the verification data to the data processing module.
In the implementation process, the data processing module is provided with an interface, the interface is connected with the computer, and when other types of chips are required to be detected, the computer can transmit a new scheduling instruction set, detection data and verification data to the data processing module, so that the other types of chips are detected, the other modules are not required to be replaced, and the use is more flexible.
Referring to fig. 2, in one possible implementation manner, a matching rate threshold value of the verification data and the output data of the chip to be tested is preset in the comparison module, when the comparison module detects that the matching rate of the verification data and the output data of the chip to be tested is lower than the matching rate threshold value, the data processing module transmits the output data of the chip to be tested to an external computer, and the external computer compares the output data of the chip to be tested with the verification data again.
In the implementation process, a matching rate threshold value of the output data and the verification data of the chip to be detected is preset in the comparison module, and the matching rate is calculated in the following manner: when the comparison module detects that the matching rate is lower than the matching rate threshold, the error in the chip is more, the data processing module is required to transmit the output data of the chip to be tested to an external computer, the external computer is internally provided with the verification data, and the output data of the chip to be tested and the verification data are compared again in more detail in the external computer. When the chip errors are more, the chip errors can be compared in more detail in an external computer so as to record the chip error addresses, fault types and the like, and an operator can find the defects of the chip more accurately.
Referring to fig. 2, in one possible implementation manner, a temperature detection module is disposed in the comparison module, and is configured to detect a current temperature of the comparison module in real time, and when the temperature of the comparison module is higher than a temperature threshold, the data processing module transmits remaining un-compared output data of the chip to be tested to an external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with verification data.
In the implementation process, the temperature detection module is arranged inside the comparison module, so that the current temperature of the comparison module can be detected in real time, the temperature threshold value is preset for the comparison module before detection, and the comparison efficiency of the comparison module is reduced when the temperature of the comparison module is higher than the preset temperature threshold value. At this time, the comparison module stops comparing, the data processing module transmits the remaining un-compared output data of the chip to be tested to the external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with the verification data, so as to reduce the working strength of the comparison module, avoid the reduction of the comparison efficiency caused by the overhigh temperature of the comparison module, and transfer the comparison place from the comparison module to the external computer, so as to maintain higher comparison efficiency.
In a second aspect, please refer to fig. 1, the present application further provides an editable chip detection system, which includes a data processing module, a memory module and a comparison module disposed on a circuit board; the data processing module is internally provided with an operating system for generating a scheduling instruction set, detection data and verification data, the storage module is used for storing the detection data transmitted by the data processing module, and the comparison module is pre-provided with the verification data; the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, and the comparison module compares the output data of the chip to be tested with preset verification data.
In the implementation process, the data processing module is arranged on the circuit board, the storage module is electrically connected with the data processing module, and the comparison module is electrically connected with the storage module and the chip to be tested. The data processing module may be a Central Processing Unit (CPU) such as a RISC-V instruction set, a Field Programmable Gate Array (FPGA) or a microprocessor (ARM) core, the storage module may be a mass storage unit, and the comparison module may be a chip. Before chip testing, the data processing module is preset with a dispatching instruction set, dispatches the detection data to the storage module for storing the detection data, and the comparison module is preset with verification data. After the test is started, the data processing module issues the scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to the chip to be tested, the chip to be tested runs the detection data and outputs the data, the comparison module compares the output data of the chip to be tested with preset verification data, whether the chip has problems or not is judged according to whether the comparison result is consistent, if the result is consistent, the chip has problems, and if the result is inconsistent, the chip has problems. The data processing module, the storage module and the comparison module are all arranged on the circuit board, so that the influence on the detection efficiency of the chip due to low transmission rate of an external interface and low transmission rate of wires is avoided, the whole data processing module, the storage module and the comparison module are integrated on the circuit board, the transmission efficiency is greatly improved, and a plurality of high-end chips can be detected simultaneously. The data processing module is preset with a scheduling instruction set, different scheduling instructions correspondingly schedule different detection data, and the storage module schedules the detection data corresponding to the different scheduling instructions into the chip to be detected according to the detection data corresponding to the different scheduling instructions during the detection process, so that the detection data is scheduled more rapidly. The integrated chip detection system can also detect a plurality of chips in the same category, other contents do not need to be replaced, and the detection efficiency of the chips is improved. The operation system is arranged in the data processing module, can be a linux operation system, can generate a scheduling instruction set, detection data and verification data, is integrated in the data processing module, can flexibly write operation instructions and programs, does not need to develop corresponding upper computer software, and can generate a new scheduling instruction set, detection data and verification data in the data processing module through the operation system after different chips to be tested are replaced, so that other modules do not need to be replaced, and more flexible test and verification are realized.
Referring to fig. 2, in one possible implementation, the data processing module is provided with an interface, which is connected to an external computer, and the external computer may transmit the scheduling instruction set, the detection data, and the verification data to the data processing module.
In the implementation process, the data processing module is provided with an interface, the interface is connected with the computer, and when other types of chips are required to be detected, the computer can transmit a new scheduling instruction set, detection data and verification data to the data processing module, so that the other types of chips are detected, the other modules are not required to be replaced, and the use is more flexible.
Referring to fig. 2, in one possible implementation manner, a matching rate threshold value of the verification data and the output data of the chip to be tested is preset in the comparison module, when the comparison module detects that the matching rate of the verification data and the output data of the chip to be tested is lower than the matching rate threshold value, the data processing module transmits the output data of the chip to be tested to an external computer, and the external computer compares the output data of the chip to be tested with the verification data again.
In the implementation process, a matching rate threshold value of the output data and the verification data of the chip to be detected is preset in the comparison module, and the matching rate is calculated in the following manner: when the comparison module detects that the matching rate is lower than the matching rate threshold, the error in the chip is more, the data processing module is required to transmit the output data of the chip to be tested to an external computer, the external computer is internally provided with the verification data, and the output data of the chip to be tested and the verification data are compared again in more detail in the external computer. When the chip errors are more, the chip errors can be compared in more detail in an external computer so as to record the chip error addresses, fault types and the like, and an operator can find the defects of the chip more accurately.
Referring to fig. 2, in one possible implementation manner, a temperature detection module is disposed in the comparison module, and is configured to detect a temperature of a chip to be tested in real time, and when the temperature of the chip to be tested is higher than a temperature threshold, the data processing module transmits output data of the remaining chip to be tested to an external computer, and the external computer compares the output data of the remaining chip to be tested with verification data.
In the implementation process, the temperature detection module is arranged inside the comparison module, so that the current temperature of the comparison module can be detected in real time, the temperature threshold value is preset for the comparison module before detection, and the comparison efficiency of the comparison module is reduced when the temperature of the comparison module is higher than the preset temperature threshold value. At this time, the comparison module stops comparing, the data processing module transmits the remaining un-compared output data of the chip to be tested to the external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with the verification data, so as to reduce the working strength of the comparison module, avoid the reduction of the comparison efficiency caused by the overhigh temperature of the comparison module, and transfer the comparison place from the comparison module to the external computer, so as to maintain higher comparison efficiency.
Referring to fig. 2, in one possible implementation manner, when the comparison module detects that the output data of the chip to be tested is consistent with the preset verification data, the data processing module transmits the output data of the chip to be tested to the external computer, and the external computer compares the output data of the chip to be tested with the verification data again.
In the implementation process, when the comparison module detects that the output data of the chip to be tested is consistent with the preset verification data, the detection of the chip to be tested is finished. The output data of the chip to be tested can be transmitted to an external computer through the data processing module, the output data of the chip to be tested and the verification data are compared again by the external computer, and the comparison result is more accurate through the two comparison.
In one possible implementation, a scheduling module is disposed in the data processing module, and after the data processing module transmits one segment of detection data to the storage module, the scheduling module transmits the next segment of detection data to the storage module.
In the implementation process, the scheduling module is arranged in the data processing module, after the data processing module transmits one section of detection data to the storage module, the scheduling module transmits the next section of detection data to the storage module, and the efficiency of the detection data from the data processing module to the storage module is improved through the scheduling of the detection data by the scheduling module.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (3)
1. A chip testing system, comprising:
the data processing module, the storage module and the comparison module are arranged on the circuit board;
the data processing module is preset with a scheduling instruction set, the scheduling instruction set comprises single data operation and batch operation on data blocks, the storage module is used for storing detection data transmitted by the data processing module, and the comparison module is preset with verification data;
the data processing module issues a scheduling instruction to the storage module, the storage module sends detection data corresponding to the scheduling instruction to a chip to be tested, and the comparison module compares output data of the chip to be tested with preset verification data;
the data processing module is provided with an interface, the interface is connected with an external computer, and the external computer can transmit a scheduling instruction set, detection data and verification data to the data processing module;
the comparison module is internally preset with a matching rate threshold value of the verification data and the output data of the chip to be tested, when the comparison module detects that the matching rate of the verification data and the output data of the chip to be tested is lower than the matching rate threshold value, the error of the chip to be tested is indicated, the data processing module transmits the output data of the chip to be tested to an external computer, and the external computer compares the output data of the chip to be tested with the verification data again, and the comparison module comprises the following steps: recording the error address and the fault type of the chip to be tested;
and the comparison module is internally provided with a temperature detection module for detecting the current temperature of the comparison module in real time, and when the temperature of the comparison module is higher than a temperature threshold value, the data processing module transmits remaining un-compared output data of the chip to be tested to an external computer, and the external computer compares the remaining un-compared output data of the chip to be tested with verification data.
2. The chip inspection system of claim 1, wherein an operating system is provided in the data processing module for generating a set of scheduling instructions, inspection data, and verification data.
3. The chip inspection system according to claim 2, wherein the data processing module transmits the chip output data to be inspected to an external computer when the comparison module detects that the chip output data to be inspected is consistent with the preset verification data, and the external computer compares the chip output data to be inspected with the verification data again.
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| CN113742202A (en) * | 2020-05-29 | 2021-12-03 | 上海商汤智能科技有限公司 | AI chip verification system, method, device and storage medium |
| CN111856258B (en) * | 2020-07-24 | 2023-05-09 | 北京百度网讯科技有限公司 | Method, device, storage medium and corresponding chip for testing chip |
| CN112014726B (en) * | 2020-08-05 | 2023-09-05 | 广东省新一代通信与网络创新研究院 | DSP chip testing device and method |
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