CN115798414A

CN115798414A - Gate drive circuit and drive method thereof, panel drive circuit and panel

Info

Publication number: CN115798414A
Application number: CN202211679766.8A
Authority: CN
Inventors: 陆旭; 朱俊锋; 刘颖; 周鹏
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2023-03-14

Abstract

The embodiment of the disclosure provides a gate driving circuit, a driving method thereof, a panel driving circuit and a panel. The gate driving circuit includes: the driving signal output module is respectively connected with a first control signal terminal, a first input terminal and a first output terminal, and is configured to control the first input terminal to provide a driving signal to the first output terminal based on a first control signal provided by the first control signal terminal; and the signal output control module is respectively connected with a second control signal terminal, the first output terminal and the second output terminal and is configured to control whether the first output terminal provides the driving signal to the second output terminal or not based on a second control signal provided by the second control signal. The embodiment of the disclosure can realize whether the driving signal is output or not so as to realize refreshing in different panel display areas according to different refreshing frequencies.

Description

Gate drive circuit and drive method thereof, panel drive circuit and panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a gate driving circuit, a driving method thereof, a panel driving circuit, and a panel.

Background

For a display panel, such as an OLED panel, the gate driving circuits are connected in stages, and the output terminal of the gate driving circuit of the previous stage is connected to the control terminal of the gate driving circuit of the next stage. Thus, when the display panel refreshes the current frame image, the whole display panel refreshes according to the same refreshing frequency. Therefore, different areas of the display panel cannot be refreshed at different refresh frequencies.

Disclosure of Invention

Embodiments of the present disclosure provide a gate driving circuit, a driving method thereof, a panel driving circuit and a panel, so as to solve or alleviate one or more technical problems in the prior art.

As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a gate driving circuit, including:

the driving signal output module is respectively connected with a first control signal terminal, a first input terminal and a first output terminal, and is configured to control the first input terminal to provide a driving signal to the first output terminal based on a first control signal provided by the first control signal terminal;

and the signal output control module is respectively connected with a second control signal terminal, the first output terminal and the second output terminal and is configured to control whether the first output terminal provides the driving signal to the second output terminal or not based on a second control signal provided by the second control signal.

As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a panel driving circuit including:

the gate driving circuit comprises a plurality of cascaded gate driving circuits, wherein the gate driving circuit is provided by any one embodiment of the disclosure, and a first output end of a previous-stage gate driving circuit in two adjacent stages of gate driving circuits is connected with a first control signal end of a next-stage gate driving circuit.

As a third aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a driving method applied to a gate driving circuit provided in any embodiment of the present disclosure, the method including:

providing a first control signal to a first control signal terminal in the gate driving circuit, so that a driving signal output module in the gate driving circuit controls the first input terminal to provide a driving signal to the first output terminal based on the first control signal;

and providing a second control signal to a second control signal terminal in the gate driving circuit, so that a signal output control module in the gate driving circuit controls whether the first output terminal provides the driving signal to the second output terminal or not based on the second control signal.

As a fourth aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a panel including the panel driving circuit provided in any embodiment of the present disclosure.

According to the technical scheme provided by the embodiment of the disclosure, the signal output control module is arranged between the first output end and the second output end of the gate driving circuit, so that whether the driving signal of the gate driving circuit is output or not can be controlled, and therefore, when the gate driving circuits are cascaded, different gate driving circuits can be controlled in different areas to output signals, and different areas of the display panel can refresh the current frame according to different refreshing frequencies.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure;

FIG. 5 is a block diagram of a panel driver circuit according to an embodiment of the present disclosure;

fig. 6 is a structural diagram of a panel driving circuit according to another embodiment of the present disclosure;

FIG. 7 is a block diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 8 is a timing diagram for the pixel circuit of the disclosed embodiment of FIG. 7;

fig. 9 is a timing diagram of a panel driving circuit according to an embodiment of the present disclosure;

fig. 10 is a flowchart of a driving method according to an embodiment of the disclosure.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the source and the drain of the transistor used herein are symmetrical, the source and the drain can be interchanged. In the embodiments of the present invention, a source (source electrode) is referred to as a first pole and a drain (drain electrode) is referred to as a second pole, or alternatively, the drain may be referred to as the first pole and the source may be referred to as the second pole. In the form shown in the drawings, the transistor has a gate (which may be called a gate electrode or a control terminal) as an intermediate terminal, a source as a signal input terminal, and a drain as a signal output terminal. The transistor adopted by the embodiment of the invention can be a P-type transistor or an N-type transistor, wherein the P-type transistor is switched on when the grid electrode is at a low level and is switched off when the grid electrode is at a high level; the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, the plurality of signals in the embodiments of the present invention may correspond to one or two potentials, for example, the two potentials are a first potential and a second potential, respectively. The first potential and the second potential represent only 2 different potential state quantities of the signal and do not represent that the first potential or the second potential has a specific value throughout. In the embodiment of the present invention, the first potential is taken as an example of the effective potential.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the disclosure.

The cascaded gate driving circuit includes a plurality of gate driving circuits GOAs shown in fig. 1, and fig. 1 only takes 3 GOAs as an example, and is not limited to 3 GOAs in practical application. The control signal end of the first stage of gate driving circuit inputs a control signal STV, the driving signal of the output end Out of each stage of gate driving circuit is used for driving the display of the pixels in the corresponding row, and the driving signal is used as the input signal of the control signal end of the next stage of gate driving circuit, so that the cascade connection of the gate driving circuits is realized. However, since there are no interrupt signals and control signals in the middle of the cascade gate driving circuit, the display panel cannot achieve the split-area display.

In order to solve the technical problem, the present disclosure provides a gate driving circuit, which can implement a panel split-area display and a split-area refresh.

Fig. 2 is a schematic diagram of a gate driving circuit according to another embodiment of the disclosure.

As shown in fig. 2, the present disclosure provides a gate driving circuit including a driving signal output module 210 and a signal output control module 220. The driving signal output module 210 is respectively connected to the first control signal terminal STV, the first input terminal IN1 and the first output terminal Out _1, and is configured to control the first input terminal IN1 to provide the driving signal to the first output terminal Out _1 based on the first control signal provided by the first control signal terminal STV. The signal output control module 220 is respectively connected to the second control signal terminal Part _ Ctl, the first output terminal Out _1, and the second output terminal Out _2, and is configured to control whether the first output terminal Out _1 provides the driving signal to the second output terminal Out _2 based on a second control signal provided by the second control signal terminal Part _ Ctl.

In this example, a driving signal is generated by the driving signal output module 210 and output to the first output terminal Out _1, and a signal output control module 220 is disposed between the first output terminal Out _1 and the second output terminal Out _2, and controls on/off between the first output terminal Out _1 and the second output terminal Out _2, so as to control whether the driving signal can be output to the panel, so as to control display of a corresponding pixel in the panel. Therefore, different grid driving circuits can be controlled to output signals according to different panel display areas, and the current frame image can be refreshed according to different refreshing frequencies in different display areas of the display panel.

Optionally, the second control signal terminal Part _ Ctl is connected to the signal output control module 220 corresponding to all the gate driving circuits in the panel display area, so that different gate driving circuits can be controlled to output signals according to different panel display areas, and different display areas of the display panel can refresh the current frame image according to different refresh frequencies.

Fig. 3 is a schematic diagram of a gate driving circuit according to another embodiment of the disclosure.

As shown in fig. 3, the signal output control module 220 is further connected to the first power signal terminal VGH, and the signal output control module 220 is configured to control the first output terminal Out _1 to provide the driving signal to the second output terminal Out _2 or control the first power signal terminal VGH to provide the first power signal to the second output terminal Out _2 based on the second control signal provided by the second control signal terminal Part _ Ctl.

In this example, the signal output control module 220 controls the first output terminal Out _1 to provide the driving signal to the second output terminal Out _2 or controls the first power supply signal terminal VGH to provide the first power supply signal to the second output terminal Out _2 through the second control signal. Thus, when the pixel display needs to be driven, the driving signal is provided to the second output terminal Out _2, and when the pixel display does not need to be driven, the first power supply signal is provided to the second output terminal Out _2, the power supply signal is a signal with a specified potential, for example, a high level signal, and the level of the output terminal can be pulled up, so that the pixel does not display.

Fig. 4 is a schematic diagram of a gate driving circuit according to another embodiment of the disclosure.

As shown in fig. 4, the signal output control module 220 includes a first transistor and a second transistor, a control end, a first pole, and a second pole of the first transistor are respectively connected to the second control signal end Part _ Ctl, the first output end Out _1, and the second output end Out _2, and a control end, a first pole, and a second pole of the second transistor are respectively connected to the second control signal end Part _ Ctl, the first power signal end VGH, and the second output end Out _ 2.

In this example, with the two transistors each serving as one switch, turning on the first transistor turns on the first output terminal Out _1 and the second output terminal Out _2, and turning off the second transistor turns off the first power supply signal terminal VGH and the second output terminal Out _ 2. Or, the first transistor is turned off to disconnect the first output terminal Out _1 from the second output terminal Out _2, or the second transistor is turned on to conduct the first power supply signal terminal VGH and the second output terminal Out _ 2.

In this example, two transistors are controlled simultaneously by one control terminal and one of the transistors is controlled to turn the other transistor off, so that the channel types selected by the two transistors are different, one of which is a P-channel field effect transistor (PMOS transistor) and the other is an N-channel field effect transistor (NMOS transistor).

Illustratively, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

In this example, when the second control signal terminal Part _ Ctl is at a low level, the first transistor is turned on, the second transistor is turned off, and the first output terminal Out _1 normally outputs a driving signal to the second output terminal Out _2 to the corresponding pixel. When the second control signal terminal Part _ Ctl is at a high level, the first transistor is turned off, the second transistor is turned on, and the first output terminal Out _1 cannot normally output a driving signal to the corresponding pixel to the second output terminal Out _ 2. Therefore, whether the driving signal of the driving signal output module 210 is output to the corresponding pixel can be controlled, so that different gate driving circuits are controlled to output signals according to different panel display areas, and the current frame image is refreshed according to different refreshing frequencies in different display areas of the display panel.

Illustratively, the first transistor near the driving signal input block is a PMOS transistor, and the second transistor near the panel driving circuit of the display panel is an NMOS transistor. The first power supply end connected with the second transistor is a high level VGH, the requirement on the turn-off of the VGH is higher, the requirement on the uniformity of the second transistor is higher, and the second transistor is an NMOS transistor.

Illustratively, since the second transistor is in an off state for a long time, the leakage requirement is high, i.e., it is prevented from leaking, and thus the second transistor is an NMOS transistor. For example: an oxide transistor.

Illustratively, the width-to-length ratio W/L of the second transistor is larger than that of the first transistor because the anti-leakage requirement of the second transistor is higher than that of the first transistor. For example: the width-to-length ratio of the second transistor is 2.5/3.5.

In some embodiments, the second control signal terminal Part _ Ctl may connect gates of the first transistor and the second transistor in all gate driving circuits of the display panel. The design can control the on and off of the gate driving circuits in different areas through one control signal (for example, a second control signal), so that the number of signal lines is reduced.

Illustratively, the second transistor is a low temperature poly oxide transistor.

In this example, since the driving signal cannot be normally output to the corresponding pixel from the first output terminal Out _1 to the second output terminal Out _2, the pixel corresponding to the high-level signal is output from the first power signal to the second output terminal Out _2, so that the display of the pixel is stopped. In order to avoid the phenomenon of electric leakage when the display is stopped for a long time, the second transistor may be a low-temperature polycrystalline oxide transistor to avoid the phenomenon.

As shown IN fig. 3, the first input terminal IN1 includes a first power signal terminal VGH and a second power signal terminal VGL, the driving signal output module 210 is further connected to the first clock signal terminal CK and the second clock signal terminal CB, and the driving signal output module 210 is configured to control the first power signal terminal VGH to provide the first power signal to the first output terminal Out _1, control the second power signal terminal VGL to provide the second power signal to the first output terminal Out _1, control the first clock signal terminal to provide the first clock signal to the first output terminal Out _1, or control the second clock signal terminal CB to provide the second clock signal to the first output terminal Out _1 based on the first control signal provided by the first control signal terminal STV, the first clock signal provided by the first clock signal terminal CK, and the second clock signal provided by the second clock signal terminal CB, so as to form the driving signal output by the first output terminal Out _ 1.

In this example, one of the power supply signal terminal or the clock signal terminal is selected by the first control signal, the first clock signal, and the second clock signal to supply the potential signal to the first output terminal Out _1, thereby forming the driving signal in timing.

As shown in fig. 4, the driving signal output module 210 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

A control end, a first pole and a second pole of the third transistor T3 are respectively connected with the first clock signal end CK, the first control signal end STV and a control end of the fourth transistor T4, a first pole and a second pole of the fourth transistor T4 are respectively connected with the first clock signal end CK and a first pole of the fifth transistor T5, and a control end and a second pole of the fifth transistor T5 are respectively connected with the first clock signal end CK and the second power signal end VGL.

A control end, a first pole and a second pole of the sixth transistor T6 are respectively connected to the first pole of the fifth transistor T5, the first power signal end VGH and the first pole of the seventh transistor T7, a control end and a second pole of the seventh transistor T7 are respectively connected to the second clock signal end CB and the second pole of the third transistor T3, a control end, a first pole and a second pole of the eighth transistor T8 are respectively connected to the first pole of the fifth transistor T5, the first power signal end VGH and the first pole of the ninth transistor T9, and a control end and a second pole of the ninth transistor T9 are connected to the second pole of the third transistor T3 and the second clock signal end CB.

In some embodiments, the control terminal and the second pole of the ninth transistor T9 are connected to the second pole of the third transistor T3 and the second power signal terminal VGL.

In this example, the second pole of the ninth transistor T9 may be connected to the second power signal terminal VGL, and may also be connected to the second clock signal terminal CB.

As shown in fig. 4, the driving signal output module 210 further includes a first capacitor C1 and a second capacitor C2; the first end and the second end of the first capacitor C1 are respectively connected to the control end and the first pole of the eighth transistor T8, and the first end and the second end of the second capacitor C2 are respectively connected to the control end and the first pole of the ninth transistor T9.

As shown in fig. 4, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be PMOS transistors.

In this example, the driving signal output module 210 is only one example, and other types of driving signal output modules 210 may be applied to the embodiments of the present disclosure.

Fig. 5 is a structural diagram of a panel driving circuit according to an embodiment of the present disclosure.

As shown in fig. 5, the embodiment of the present disclosure provides a panel driving circuit including a plurality of gate driving circuits connected in cascade, where the gate driving circuit is the gate driving circuit of any one of the embodiments of the present disclosure, and the first output terminal Out _1 of the previous gate driving circuit in two adjacent stages of gate driving circuits is connected to the first control signal terminal STV of the next gate driving circuit.

The second output end Out _2 of each stage of gate driving circuit is connected to a row of pixels to drive the row of pixels for display.

In this example, the signal output control module 220 of each stage of gate driving circuit can control whether the driving signal of each row of pixels is normally output, so as to control different regions of the panel to perform different displays, thereby implementing the display in different regions.

Fig. 6 is a structural diagram of a panel driving circuit according to another embodiment of the present disclosure.

As shown in fig. 6, the plurality of gate driving circuits includes at least two groups of gate driving circuits, each group of gate driving circuits includes a plurality of gate driving circuits in cascade connection;

in each group of gate drive circuits, a first output end Out _1 of a previous gate drive circuit in two adjacent stages of gate drive circuits is connected with a first control signal end STV of a next gate drive circuit, and second signal control ends of each stage of gate drive circuit are connected with each other;

in the two adjacent groups of gate driving circuits, the first output terminal Out _1 of the last stage of gate driving circuit in the previous group of gate driving circuits is connected with the first control signal terminal STV of the first stage of gate driving circuit in the next group of gate driving circuits.

In this example, each group of gate driving circuits controls the display of pixels in one area of the panel, and the second signal control terminals of the gate driving circuits of the same group are connected with each other, so that the pixels in the area can be synchronously displayed or not displayed.

In some embodiments, the panel comprises a plurality of rows of pixels, and each gate driving circuit in the panel drives the display of a row of pixels respectively. In the plurality of gate driving circuits in the panel driving circuit, the second signal control terminals of the gate driving circuits in odd-numbered rows are connected with each other, and the second signal control terminals of the gate driving circuits in even-numbered rows are connected with each other.

For example, as shown in fig. 3 to 6, the first power signal line (e.g., VGH) of the signal output control block 220 and the first power signal line (e.g., VGH) of the driving signal output block 210 may be the same signal line.

Illustratively, as shown in fig. 3 to 6, the first power signal line (e.g., VGH) of the signal output control module 220 is located between the second control signal line Part _ Ctl and the display area panel driving circuit of the display panel. Fig. 7 is a structural diagram of a pixel circuit according to an embodiment of the disclosure, and fig. 8 is a timing diagram of the pixel circuit according to an embodiment of the disclosure; the gate driving circuit of any embodiment of the present disclosure provides driving signals for the pixel circuits of the display panel, for example: any of the embodiments of the gate driver circuits of fig. 1-6 provides a driving signal to the M4 transistor in the pixel circuit of fig. 7.

The operation of the pixel circuit of fig. 7 is described below with reference to the signal timing diagram of fig. 8.

Specifically, four phases of the first initialization phase T1', the data writing phase T2', the second initialization phase T3 'and the light emitting phase T4' of one frame period in the signal timing diagram of fig. 8 are selected.

In the first initialization stage T1', the first control terminal PSR1 inputs a low level signal, the first initialization transistor M1 is turned on, and the first initialization signal terminal Vint1 provides an initialization signal to the N3 node to initialize the N3 node.

In the Data writing phase T2', the first Scan control terminal P _ Scan inputs a low level signal, the second Scan control terminal N _ Scan inputs a high level signal, the first Scan transistor M2 and the second Scan transistor M4 are both turned on, and the driving transistor M3 maintains the on state of the previous frame light emitting phase, so that the Data voltage of the Data signal terminal Data is written into the N1 node.

In the second initialization stage T3', the second control terminal PSR2 inputs a low level signal, the second initialization transistor M7 is turned on, and the second initialization signal terminal Vint2 provides an initialization signal to the anode of the OLED to initialize the anode.

In the light-emitting period T4', a low level signal is input to the light-emitting control terminal EM, the first light-emitting control transistors M5 and M6 are both turned on, and a signal of the first power terminal VDD generates a current through the driving transistor M3 to drive the OLED to emit light.

For example, the working timing of the pixel circuit is a first frame, if the refresh rate of the first frame needs to be maintained in a second frame (i.e., the second frame does not need to be refreshed), the second Scan transistor M4 needs to be controlled to be turned off in the data writing stage T2', so that the output end Out2 of the gate driving circuit provided in any embodiment of the disclosure needs to output a high level signal, that is, the low level signal (dashed line a) originally input by the first Scan control end P _ Scan in fig. 8 needs to be changed into a high level signal, thereby realizing that the second frame is a refresh rate maintaining frame of the first frame.

Of course, only one frame is taken as an example for description, and different regions of different display panels may be refreshed or not refreshed; or the display panel is refreshed or not refreshed at different frames.

As shown in fig. 7 to 9, the operation principle thereof will be described below in conjunction with the driving circuit of fig. 6.

1) In the normal display process, the second control terminal Part _ Ctl of the gate driving circuit is pulled down to a low level VGL, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first output terminal Out _1 of each stage of gate driving circuit normally outputs a driving signal to the second output terminal Out _2, so that the gate driving circuit of fig. 6 outputs a driving signal to the pixel circuit of fig. 7 line by line;

2) When the panel is judged not to need refreshing from the pixels in the Nth row, a signal provided to the second control end Part _ Ctl of the gate driving circuit in the Nth row is pulled high, the first transistor T1 is closed, the second transistor T2 is conducted, the second output ends Out _2 of all the gate driving circuits output high levels to VGH, and charging is closed corresponding to the row.

3) When the panel starts refreshing again from the N +2 th row, the Part _ Ctl signal is pulled low, the first transistor T1 is turned on, the second transistor T2 is turned off, and the second output end Out2_ N +2 of the gate driving circuit of the N +2 th row recovers the output waveform, i.e., outputs the driving signal.

4) By repeating the above operation, the screen can be divided into different display areas, namely a refresh area and a non-refresh area, by the Part _ Ctl signal.

5) By matching with the operational logic of the driving chip DIC, the Output of the Nth row of the Part _ Ctl is high, and meanwhile, the data Output Source Output of the corresponding row can be closed, so that the Gate driving circuit Gate and the data Source unit can be simultaneously reduced in power consumption.

The present disclosure also provides a panel, which may include the panel driving circuit of any embodiment of the present disclosure.

Fig. 10 is a schematic diagram of a driving method according to an embodiment of the disclosure.

As shown in fig. 10, an embodiment of the present disclosure provides a driving method applied to a gate driving circuit provided in any embodiment of the present disclosure, where the method includes:

s810, providing a first control signal to a first control signal terminal in the gate driving circuit, so that a driving signal output module in the gate driving circuit controls a first input terminal to provide a driving signal to a first output terminal based on the first control signal;

s820, providing a second control signal to a second control signal terminal in the gate driving circuit, so that the signal output control module in the gate driving circuit controls whether the first output terminal provides the driving signal to the second output terminal based on the second control signal.

In this example, the driving signal output module generates a driving signal and outputs the driving signal to the first output end, and a signal output control module is arranged between the first output end and the second output end and controls on-off between the first output end and the second output end, so as to control whether the driving signal can be output to the panel or not and control display of a corresponding pixel in the panel. Therefore, different grid driving circuits can be controlled to output signals according to different panel display areas, and the current frame image can be refreshed according to different refreshing frequencies in different display areas of the display panel.

As shown in fig. 3, the signal output control module is further connected to the first power signal terminal, and at this time, the method further includes:

and providing the first power supply signal to the first power supply signal end so that the signal output control module controls the first output end to provide the driving signal to the second output end based on the second control signal, or controls a power supply signal end to provide the first power supply signal to the second output end.

In this example, the signal output control module controls the first output terminal to provide the driving signal to the second output terminal or controls the first power signal terminal to provide the first power signal to the second output terminal through the second control signal. Thus, when the pixel display needs to be driven, the driving signal can be provided to the second output end, and when the pixel display does not need to be driven, the first power supply signal is provided to the second output end, the power supply signal is a signal with a specified electric potential, for example, the power supply signal is a high-level signal, and the level of the output end can be pulled high, so that the pixel does not display.

As shown in fig. 3, the first input terminal includes a first power signal terminal and a second power signal terminal, the driving signal output module is further connected to a first clock signal terminal and a second clock signal terminal, and the providing of the first control signal to the first control signal terminal in the gate driving circuit is performed so that the driving signal output module in the gate driving circuit controls the first input terminal to provide the driving signal to the first output terminal based on the first control signal, including:

the method comprises the steps of providing a first control signal, a first clock signal, a second clock signal, a first power signal and a second power signal to a first control signal end, a first clock signal end, a second clock signal end, a first power signal end and a second power signal end in a grid driving circuit respectively, so that a driving signal output module in the grid driving circuit controls the first power signal end to provide the first power signal to a first output end, controls the second power signal end to provide the second power signal to the first output end, and controls the first clock signal end to provide the first clock signal to the first output end or controls the second clock signal end to provide the second clock signal to the first output end based on the first control signal, the first clock signal and the second clock signal, so as to form a driving signal output by the first output end.

In this example, one of the power supply signal terminals is selected by the first control signal, the first clock signal, and the second clock signal to supply the potential signal to the first output terminal, thereby forming the driving signal in time series.

In some embodiments, as shown in fig. 3, the providing the first power signal to the first power signal terminal by the second control signal includes providing the first power signal to the first power signal terminal, so that the signal output control module controls the first output terminal to provide the driving signal to the second output terminal or controls the first power signal terminal to provide the first power signal to the second output terminal based on the second control signal, including:

providing a first potential signal to a second control signal end in the grid drive circuit so that the signal output control module controls the first output end to provide a drive signal to the second output end based on the first potential signal; or,

and providing a second potential signal to a second control signal end in the grid drive circuit so that the signal output control module controls the first power supply signal end to provide the first power supply signal to the second output end based on the second potential signal.

Illustratively, when the second control signal terminal is at a low level, the connection between the first output terminal and the second output terminal is on, the connection between the first power signal terminal and the second output terminal is off, and the first output terminal normally outputs the driving signal to the second output terminal for the corresponding pixel. When the second control signal terminal is at a high level, the connection between the first output terminal and the second output terminal is disconnected, the connection between the first power signal terminal and the second output terminal is conducted, and the first output terminal cannot normally output a driving signal to the second output terminal to a corresponding pixel.

The detailed driving process of the switch circuit has been described above, and is not described herein again.

The electronic device in the embodiments of the present disclosure may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integral with; the connection can be mechanical connection, electrical connection or communication; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation that the first and second features are not in direct contact, but are in contact via another feature between them. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. The first feature being "under," "beneath," and "under" the second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A gate drive circuit, comprising:

and the signal output control module is respectively connected with a second control signal terminal, the first output terminal and the second output terminal, and is configured to control whether the first output terminal provides the driving signal to the second output terminal or not based on a second control signal provided by the second control signal terminal.

2. A gate driving circuit as claimed in claim 1, wherein the signal output control module is connected to a first power signal terminal, and the signal output control module is configured to control the first output terminal to provide the driving signal to the second output terminal or control the first power signal terminal to provide the first power signal to the second output terminal based on a second control signal provided by the second control signal terminal.

3. A gate driving circuit according to claim 2, wherein the signal output control module comprises a first transistor and a second transistor, the control terminal, the first pole and the second pole of the first transistor are respectively connected to the second control signal terminal, the first output terminal and the second output terminal, and the control terminal, the first pole and the second pole of the second transistor are respectively connected to the second control signal terminal, the first power signal terminal and the second output terminal.

4. A gate drive circuit as claimed in claim 3, wherein the first transistor is a P-channel field effect transistor and the second transistor is an N-channel field effect transistor.

5. A gate drive circuit as claimed in claim 3, wherein the second transistor is a low temperature poly-oxide transistor.

6. The gate driving circuit of claim 1, wherein the first input terminal comprises a first power signal terminal and a second power signal terminal, the driving signal output module is further connected to a first clock signal terminal and a second clock signal terminal, and the driving signal output module is configured to control the first power signal terminal to provide a first power signal to the first output terminal, the second power signal terminal to provide a second power signal to the first output terminal, the first clock signal terminal to provide a first clock signal to the first output terminal, or the second clock signal terminal to provide a second clock signal to the second output terminal based on a first control signal provided by the first control signal terminal, a first clock signal provided by the first clock signal terminal, and a second clock signal provided by the second clock signal terminal, so as to form the driving signal output by the first output terminal.

7. The gate driving circuit according to claim 6, wherein the driving signal output module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;

a control end, a first pole and a second pole of the third transistor are respectively connected with the first clock signal end, the first control signal end and a control end of the fourth transistor, a first pole and a second pole of the fourth transistor are respectively connected with the first clock signal end and a first pole of the fifth transistor, and a control end and a second pole of the fifth transistor are respectively connected with the first clock signal end and the second power signal end;

a control end, a first pole and a second pole of the sixth transistor are respectively connected with a first pole of the fifth transistor, the first power signal end and a first pole of a seventh transistor, a control end and a second pole of the seventh transistor are respectively connected with the second clock signal end and a second pole of the third transistor, a control end, a first pole and a second pole of the eighth transistor are respectively connected with a first pole of the fifth transistor, the first power signal end and a first pole of the ninth transistor, and a control end and a second pole of the ninth transistor are respectively connected with a second pole of the third transistor and the second clock signal end.

8. The gate driving circuit according to claim 7, wherein the driving signal output module further comprises a first capacitor and a second capacitor;

and the first end and the second end of the first capacitor are respectively connected with the control end and the first pole of the eighth transistor, and the first end and the second end of the second capacitor are respectively connected with the control end and the first pole of the ninth transistor.

9. A gate driver circuit according to claim 7, wherein the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-channel field effect transistors.

10. A panel driving circuit, comprising a plurality of gate driving circuits connected in cascade, wherein the gate driving circuit is the gate driving circuit according to any one of claims 1 to 9, and the first output terminal of the previous gate driving circuit in two adjacent stages of gate driving circuits is connected to the first control signal terminal of the next gate driving circuit.

11. The panel driving circuit according to claim 10, wherein the plurality of gate driving circuits includes at least two groups of gate driving circuits, each group of gate driving circuits including a plurality of the gate driving circuits in cascade;

in each group of gate drive circuits, a first output end of a previous gate drive circuit in two adjacent stages of gate drive circuits is connected with a first control signal end of a next gate drive circuit, and second signal control ends of each stage of gate drive circuit are connected with each other;

in two adjacent groups of gate drive circuits, the first output end of the last stage of gate drive circuit in the previous group of gate drive circuits is connected with the first control signal end of the first stage of gate drive circuit in the next group of gate drive circuits.

12. A panel comprising the panel driving circuit according to claim 10 or 11.

13. A driving method applied to the gate driving circuit according to any one of claims 1 to 9, the method comprising:

14. The method of claim 13, wherein the signal output control module is connected to a first power signal terminal, the method further comprising:

and providing a first power supply signal to the first power supply signal terminal, so that the signal output control module controls the first output terminal to provide the driving signal to the second output terminal based on the second control signal, or controls the first power supply signal terminal to provide the first power supply signal to the second output terminal.

15. The method of claim 13, wherein the first input terminal comprises a first power signal terminal and a second power signal terminal, the driving signal output module is further connected to a first clock signal terminal and a second clock signal terminal, and the providing the first control signal to the first control signal terminal of the gate driving circuit causes the driving signal output module of the gate driving circuit to control the first input terminal to provide the driving signal to the first output terminal based on the first control signal comprises:

and providing a first control signal, a first clock signal, a second clock signal, a first power signal and a second power signal to a first control signal end, a first clock signal end, a second clock signal end, a first power signal end and a second power signal end in the gate driving circuit respectively, so that a driving signal output module in the gate driving circuit controls the first power signal end to provide a first power signal to the first output end, the second power signal end to provide a second power signal to the first output end, the first clock signal end to provide a first clock signal to the first output end or the second clock signal end to provide a second clock signal to the first output end based on the first control signal, the first clock signal and the second clock signal, thereby forming a driving signal output by the first output end.

16. The method of claim 14, wherein the second control signal comprises a first potential signal and a second potential signal, and the providing the first power signal to the first power signal terminal to cause the signal output control module to control the first output terminal to provide the driving signal to the second output terminal or control the first power signal terminal to provide the first power signal to the second output terminal based on the second control signal comprises:

providing the first potential signal to a second control signal terminal in the gate driving circuit, so that the signal output control module controls the first output terminal to provide the driving signal to the second output terminal based on the first potential signal; or,

and providing the second potential signal to a second control signal terminal in the gate driving circuit, so that the signal output control module controls the first power supply signal terminal to provide the first power supply signal to the second output terminal based on the second potential signal.