CN115774649A - Automatic memory parameter adjusting system, method and device - Google Patents
Automatic memory parameter adjusting system, method and device Download PDFInfo
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- CN115774649A CN115774649A CN202211586627.0A CN202211586627A CN115774649A CN 115774649 A CN115774649 A CN 115774649A CN 202211586627 A CN202211586627 A CN 202211586627A CN 115774649 A CN115774649 A CN 115774649A
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Abstract
The invention is suitable for the technical field of semiconductor devices, and particularly provides an automatic memory parameter adjusting system, a method and a device, wherein the automatic memory parameter adjusting system comprises a test board and an MCU (microprogrammed control unit) processor, wherein the test board comprises a plurality of memory slots for plugging a tested memory and the MCU processor is connected with the memory slots; the main control board comprises a connecting slot which is in plug-in fit with the test board and a main control processor which is connected with the connecting slot; the main control board is used for testing the tested memory through the test board, receiving a test result returned by the test board, transmitting unmatched parameters between the tested memory and the main control board to the test board according to the test result, adjusting the parameters and burning the parameters to the SPD chip of the tested memory. The invention can effectively improve the memory testing efficiency, reduce the production cost and simplify the memory testing process by automatically capturing the unmatched parameters between the tested memory and the main control board in the testing process and further regulating the parameters and burning the parameters into the SPD chip of the tested memory again.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an automatic memory parameter adjusting system, method and device.
Background
A Memory (Memory) is an important part of a computer, and is also called an internal Memory and a main Memory, and stores operation data in a CPU and data exchanged with an external Memory such as a hard disk. Before the memory is produced and delivered from a factory, the frequency and time sequence matching performance of the memory and a PC mainboard needs to be judged, namely, the frequency and time sequence matching performance of a large batch of memories needs to be tested, so that the yield of the memories is ensured.
The existing matching problem of the memory frequency is closely related to the time sequence of the memory, and in the testing process, when the time sequence of the memory is not matched, the frequency of the memory and the PC mainboard can not be matched, the time sequence and the frequency parameters are usually adjusted by manual operation and are burned into the memory SPD through a burning tool, so that the efficiency is low and the labor cost is high. And because the burning tool and the test platform of the SPD information of the memory are completely separated, the memory needs to be frequently plugged and unplugged in the test process to transfer the memory for testing and burning, the SPD burning and testing process is repeated, and the steps are complicated.
Disclosure of Invention
The invention provides an automatic memory parameter adjusting system, which solves the problems of low testing efficiency, high cost and complicated steps of memory frequency and time sequence matching performance in the prior art.
The invention is realized in this way, an automatic memory parameter adjusting system, comprising:
the test board comprises a plurality of memory slots for inserting the tested memory and an MCU (microprogrammed control unit) processor connected with the memory slots; and
the main control board comprises a connecting slot which is in plug-in fit with the test board and a main control processor which is connected with the connecting slot;
the main control board is used for testing the tested memory through the test board, receiving a test result returned by the test board, transmitting unmatched parameters between the tested memory and the main control board to the test board according to the test result, adjusting the parameters and burning the parameters to the SPD chip of the tested memory.
Furthermore, the system also comprises a display end connected with the main control panel.
Further, the test performed on the memory under test is an AI DA64 test.
Furthermore, the test board also comprises a power supply module and a signal conversion module;
the power supply module is connected with the memory slots and the MCU processor and supplies power to the memory slots and the MCU processor;
the signal conversion module is connected with the memory slots and the serial ports of the test board, and the serial ports are used for being matched with the connecting slots in an inserted mode.
In a second aspect, the present application further provides an automatic memory parameter adjusting control method applied to an automatic memory parameter adjusting system, where the automatic memory parameter adjusting system includes a test board and a main control board, the test board has a plurality of memory slots for plugging a tested memory and an MCU processor connected to the memory slots, the main control board has a connection slot for plugging the test board and a main control processor connected to the connection slot, and the method includes:
testing the tested memory plugged into the memory slot;
obtaining a test result, and judging whether the test is successful according to the test result;
when the test is judged to fail, determining the unmatched parameters between the tested memory and the main control board according to the test result;
and adjusting the unmatched parameters according to a preset adjustment rule, and burning the adjusted parameters to the SPD chip of the tested memory.
Further, the step of adjusting the unmatched parameters according to a preset adjustment rule and burning the adjusted parameters to the SPD chip of the tested memory comprises the following steps:
acquiring the type information of a tested memory;
selecting SPD information corresponding to the category information from a preset SPD database;
and burning the SPD information serving as the adjusted parameter to the SPD chip of the tested memory.
Further, after the steps of adjusting the unmatched parameters according to the preset adjustment rule and burning the adjusted parameters to the SPD chip of the tested memory, the method further comprises the following steps:
repeatedly executing the step of testing the tested memory plugged into the memory slot until the adjusted parameters are burned into the SPD chip of the tested memory, and recording the repeated times;
and reporting an error when the repetition times reach a preset threshold value.
The third aspect, this application still provides an automatic memory parameter adjustment controlling means, be applied to in the automatic memory parameter adjustment system, automatic memory parameter adjustment system is including surveying test panel and main control board, survey the test panel and have a plurality of memory slots that are used for pegging graft the memory under test and with a plurality of memory slot connected's MCU treater, the main control board have with survey test panel grafting complex connection slot and with connection slot connection's main control treater, the device includes:
the test execution unit is used for testing the tested memory plugged into the memory slot;
the result obtaining unit is used for obtaining the test result and judging whether the test is successful according to the test result;
the parameter determining unit is used for determining unmatched parameters between the tested memory and the main control board according to the test result when the test failure is judged;
and the parameter adjusting unit is used for adjusting the unmatched parameters according to a preset adjusting rule and burning the adjusted parameters to the SPD chip of the tested memory.
Further, the parameter adjusting unit includes:
the information acquisition subunit is used for acquiring the type information of the tested memory;
the information selection subunit is used for selecting SPD information corresponding to the category information from a preset SPD database;
and the information burning subunit is used for burning the SPD information serving as the adjusted parameter to the SPD chip of the tested memory.
Further, the apparatus further comprises:
the repeated testing unit is used for repeatedly executing the steps of testing the tested memory plugged into the memory slot until the adjusted parameters are burned into the SPD chip of the tested memory, and recording the repeated times;
and the error reporting execution unit is used for reporting errors when the repetition times reach a preset threshold value.
The test board is provided with a plurality of memory slots and an MCU processor, the memory slots can be used for inserting the tested memory, the main control board is provided with a connecting slot and a main control processor, the test board can be matched with the connecting slot in an inserting mode, so that the MCU processor is connected with the main control processor, the test board provided with the tested memory is inserted into the connecting slot on the main control board in the test process, the MCU processor realizes the mode of automatically controlling the communication between the test board and the main control board, the main control board can test the tested memory and receive the test result, the test board can capture unmatched parameters between the tested memory and the main control board generated in the test process, and then the parameters are adjusted and are burned into the SPD chip of the tested memory again. On one hand, the testing of the memory is completed by the main control board, the parameter grabbing, the parameter adjusting and the SPD burning are automatically realized by the testing board, manual participation is not needed, the memory testing efficiency can be effectively improved, and the production cost is reduced; on the other hand, the testing and burning of the memory are completed by a whole set of system, and the memory does not need to be frequently plugged and unplugged to transfer the memory for testing and burning, so that the memory testing process is simplified.
Drawings
FIG. 1 is a schematic diagram of an embodiment of an automated memory parameter tuning system according to the present application;
FIG. 2 is a schematic diagram of another embodiment of an automated memory parameter adjustment system according to the present invention;
FIG. 3 is a flow chart illustrating an embodiment of an automated memory parameter adjustment control method according to the present invention;
FIG. 4 is a schematic flow chart illustrating adjusting parameters for re-programming according to an embodiment of the method for controlling adjustment of memory parameters in an automated system according to the present invention;
FIG. 5 is a flowchart illustrating a retest of one embodiment of the method for controlling the adjustment of the parameters of the automated memory of the present invention;
FIG. 6 is a block diagram illustrating an embodiment of an apparatus for controlling automatic memory parameter adjustment according to the present invention;
FIG. 7 is a schematic diagram of the operation of the automated memory parameter adjustment system of the present invention;
FIG. 8 is a diagram illustrating operational timing parameters of a memory according to one embodiment of the present invention;
FIG. 9 is a diagram illustrating operating frequencies of a memory according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention realizes the test of the memory to be tested by arranging the test board to be matched with the main control board, captures the unmatched parameters between the memory to be tested and the main control board generated in the test process, and then re-burns the parameters into the SPD chip of the memory to be tested after adjusting the parameters. On one hand, the testing of the memory is completed by the main control board, the parameter grabbing, the parameter adjusting and the SPD burning are automatically realized by the testing board, manual participation is not needed, the memory testing efficiency can be effectively improved, and the production cost is reduced; on the other hand, the testing and burning of the memory are finished by a whole set of system, so that the memory does not need to be frequently plugged and unplugged to transfer the memory for testing and burning, and the memory testing process is simplified.
Example one
As shown in fig. 1, the present embodiment provides an automatic memory parameter adjusting system, which includes:
the test board 100 includes a plurality of memory slots 110 for plugging the tested memory 300, and an MCU processor 120 connected to the plurality of memory slots 110; and
the main control board 200 comprises a connection slot 210 which is in plug-in fit with the test board 100, and a main control processor 220 connected with the connection slot 210;
the main control board 200 is configured to test the memory 300 under test through the test board 100, receive a test result returned by the test board 100, transmit a parameter that is not matched between the memory 300 under test and the main control board 200 to the test board 100 according to the test result, adjust the parameter, and burn the adjusted parameter into the SPD chip 310 of the memory under test.
In implementation, the automatic memory parameter adjusting system provided by the present application includes a test board 100 and a main control board 200, wherein the test board 100 is provided with a plurality of memory slots 110, and each memory slot 110 can be correspondingly plugged with one tested memory 300.
Optionally, the memory 300 to be tested includes, but is not limited to, different types of memory products or tool fixtures such as DDR2, DDR3, DDR4, DDR5, and the like.
Alternatively, the SPD (seri al Presence Detect) chip 310 is referred to as a serial Presence Detect, which is a 1-8 pin SO ic packaged EEPROM chip with a capacity of 256 bytes. The SPD chip records the speed, capacity, voltage, row and column address bandwidth and other parameter information of the memory. The bai OS reads in information stored in the SPD when the electronic device is started, and automatically adjusts to optimize the setting. In the actual use process, the electronic device usually needs the bi OS to detect SPD data to normally operate, otherwise, the problems of incompatibility or crash occur.
Optionally, the MCU processor 120 may adopt a single chip MCU, such as a 51-chip microcomputer, and the like, which is not limited herein.
The main control board 200 is provided with a connection slot 210 and a main control processor 220, wherein the connection slot 210 is used for being in plug-in fit with the test board 100, so that the main control processor 220 communicates with the MCU processor 120.
Alternatively, the main control board 200 is a PC motherboard and the main control processor 220 is a CPU on the PC motherboard. The test board 100 is in communication connection with the main control board 200 through a serial port, and at this time, the main control processor 220 may automatically identify relevant parameters of the memory 300 to be tested through the MCU 120, such as a frequency and/or a timing of the memory 300 to be tested, which is not limited herein.
Alternatively, the parameters of the working timing (unit is time period) of the memory are shown in fig. 8, and the working frequency (MHz) of the memory is shown in fig. 9.
Optionally, during the testing process, the tested memory 300 is plugged into the memory slot 110, and then the testing board 100 is plugged into the connection slot 210, so that the tested memory 300 can be tested. In some possible embodiments, the test on the memory 300 under test is an AI DA6 test, for example, the main control processor 220 of the main control board 200 stores therein program data of the AI DA6 test, or the main control board 200 is further provided with a memory, in which the program data of the AI DA6 test is stored, and the main control processor 220 may call the program data and perform the AI DA6 test on the memory 300 under test through the MCU processor 120.
Optionally, the main control board 200 may further receive a test result returned by the test board 100, and the test board 100 obtains a parameter that does not match between the memory 300 under test and the main control board 200. Optionally, the parameter for testing the memory 300 to be tested is frequency and/or timing, specifically, the MCU processor 120 captures the information of mismatch between the frequency and timing of the memory 300 to be tested and the main control board 200 generated during the testing process by using the serial port of the testing board 100, and then adjusts and re-burns the mismatch parameter to the SPD chip 310 of the memory to be tested.
In some optional embodiments, the master processor 220 automatically identifies the type of the memory according to the io of the memory 300 to be tested through the MCU processor 120, and then the MCU processor 120 adjusts the unmatched parameters to correspond to the type of the memory 300 to be tested, such as adjusting the frequency or timing parameters, and then burns the adjusted timing or frequency parameters to the SPD chip 310 of the memory to be tested through the serial port.
In the embodiment of the application, the test board 100 is provided with the plurality of memory slots 110 and the MCU processor 120, the memory slots 110 can be used for inserting the tested memory 300, the main control board 200 is provided with the connection slot 210 and the main control processor 220, the test board 100 can be inserted and matched with the connection slot 210, so that the MCU processor 120 is connected with the main control processor 220, in the test process, the test board 100 provided with the tested memory 300 is inserted into the connection slot 210 on the main control board 200, the MCU processor 120 can automatically control the communication between the test board 100 and the main control board 200, the main control board 200 can test the tested memory 300 and receive the test result, the test board 100 can capture the unmatched parameters between the tested memory 300 and the main control board 200 generated in the test process, and then the parameters are adjusted and burned into the SPD chip 310 of the tested memory. On one hand, the testing of the memory is finished by the main control board 200, the parameter grabbing, the parameter adjusting and the SPD burning are automatically realized by the testing board 100 without manual participation, the memory testing efficiency can be effectively improved, and the production cost is reduced; on the other hand, the testing and burning of the memory are finished by a whole set of system, so that the memory does not need to be frequently plugged and unplugged to transfer the memory for testing and burning, and the memory testing process is simplified.
Example two
In some optional embodiments, the automatic memory parameter adjusting system provided in the present application further includes a display terminal 400 connected to the main control board 200.
Optionally, the display terminal 400 may be a display of a PC terminal, and in implementation, the display terminal 400 is connected to the main control board 200 to display relevant information in the detection process, for example, a test result of each tested memory 300, so that a user can conveniently and intuitively obtain information of the detection result.
EXAMPLE III
In some alternative embodiments, as shown in fig. 2, the test board 100 further includes a power supply module 130 and a signal conversion module 140;
the power supply module 130 is connected with the memory slots 110 and the MCU processor 120, and supplies power to the memory slots 110 and the MCU processor 120;
the signal conversion module 140 is connected to the memory slots 110 and the serial ports of the test board 100, and the serial ports are used for being plugged and matched with the connection slots 210.
In implementation, the test board 110 is provided with a serial port, which can be plugged into the connection slot 210 of the main control board 200, and the serial port can be designed as a metal terminal disposed on the test board 100, and the metal terminal is connected to each memory slot 110 on the test board 100.
Example four
In some optional embodiments, as shown in fig. 3, the present application further provides an automatic memory parameter adjustment control method, applied to the above automatic memory parameter adjustment system, where the automatic memory parameter adjustment system includes a test board and a main control board, the test board has a plurality of memory slots for plugging a memory to be tested and an MCU processor connected to the memory slots, the main control board has a connection slot for plugging and matching with the test board and a main control processor connected to the connection slot, and the automatic memory parameter adjustment control method provided in the present application includes:
s1100, testing a tested memory plugged into a memory slot;
the automatic memory parameter adjusting system comprises a test board and a main control board, wherein the test board is provided with a plurality of memory slots, a tested memory is pluggable into the memory slots, and the test board is pluggable into a connecting slot of the main control board, so that an MCU processor on the test board is communicated with a main control processor of the main control board.
Optionally, the steps of the automatic memory parameter adjustment control method provided in the present application are implemented by the main control processor and the MCU processor, in some embodiments, the main control processor and the MCU processor may be actual processors respectively disposed on the main control board and the test board, or may be virtual processors in a cloud, which is not limited herein.
In the using process, the test board provided with the tested memory is inserted into the connecting slot of the main control board, so that the AI DA64 test can be carried out on the tested memory. Optionally, the main control board corresponds to a PC end, corresponding test software is provided in the PC end, the tested memory 300 can be tested by starting the test software, and the test result can be checked in real time through a display of the PC end.
S1200, obtaining a test result, and judging whether the test is successful according to the test result;
in the test process, the MCU processor returns the test result to the main control processor, and the main control processor obtains the test result and judges whether the test is successful. Specifically, the MCU processor captures information in the test process by using the serial port of the test board, and transmits the captured information to the main control processor to determine whether the parameters of the tested memory and the parameters of the main control board are matched, if not, it determines that the test is failed, and executes step S1300, and if so, it determines that the test is successful, and executes step S1500.
Illustratively, taking parameters of the test as frequency and time sequence as an example, the MCU processor captures the memory under test and the log of the frequency or time sequence of the main control board generated during the test. And if the frequencies and the time sequences of the tested memory and the main control board are matched, the test is successful, and the step S1500 is executed.
S1300, determining unmatched parameters between the tested memory and the main control board according to the test result;
when it is determined that the tested memory fails to be tested, determining parameters that do not match between the tested memory and the main control board according to the test result, in some embodiments, the test items of the tested memory include, but are not limited to, frequency and timing, and the embodiments of the present application are illustrated with the frequency and timing, but not specifically limited to the present application.
And S1400, adjusting the unmatched parameters according to a preset adjustment rule, and burning the adjusted parameters to the SPD chip of the tested memory.
When the unmatched parameters between the tested memory and the main control board are determined, the MCU processor can adjust the unmatched parameters according to preset adjustment rules, and optionally, the adjustment rules are prestored in the MCU processor.
Optionally, the implementation principle of the adjustment rule may be: the MCU processor reads the IO of the tested memory to identify the type of the tested memory, further determines parameter information adaptive to the type of the tested memory according to the type of the tested memory, and then adjusts the parameters according to the parameter information. Illustratively, taking a non-matching parameter as a time sequence example, when it is determined that the time sequences of the tested memory and the main control board are not matched, the MCU processor automatically identifies the type of the tested memory according to the io of the tested memory, automatically selects corresponding SPD information, then adjusts the non-matching parameter to match the selected SPD information, and burns the adjusted parameter to the SPD chip of the tested memory.
In some possible embodiments, taking the unmatched parameter as an example, when it is determined that the timings of the memory to be tested and the main control board are not matched, the MCU processor adjusts the timing by multiple iterations, referring to fig. 7, the system is powered on to start MCU (MCU processor) initialization and perform memory test, and in the implementation, the memory test refers to performing AI DA64 test on the memory to be tested, and obtaining a test result to determine whether the memory passes the test result. When the test signal does not pass through the SPD chip, the red light of the system is normally on, the unmatched parameters are adjusted through the MCU processor, for example, the memory time sequence or frequency is adjusted, and then the adjusted parameters are burnt to the SPD chip of the tested memory again. And resetting the system again, and carrying out the memory test again when the red light is turned off. And when the test is passed, the system normally lights up in green, and the test of the tested memory of the batch is ended.
Optionally, after the adjusted parameters are burned into the SPD chip of the memory again, the system may be restarted to test the tested memory, and if the test still fails, the steps S1100 to S1400 are continuously executed until the test is successful, and step S1500 is executed.
S1500: the test is ended.
The test board is provided with a plurality of memory slots and an MCU processor, the memory slots can be used for being plugged with a tested memory, the main control board is provided with a connecting slot and a main control processor, the test board can be plugged and matched with the connecting slot, the MCU processor is connected with the main control processor, in the test process, the test board provided with the tested memory is plugged in the connecting slot on the main control board, the MCU processor realizes the mode of automatically controlling the communication between the test board and the main control board, the main control board can test the tested memory and receive the test result, the test board can capture unmatched parameters between the tested memory and the main control board generated in the test process, and then the parameters are adjusted and then burnt into the SPD chip of the tested memory again. On one hand, the testing of the memory is completed by the main control board, the parameter grabbing, the parameter adjusting and the SPD burning are automatically realized by the testing board, manual participation is not needed, the memory testing efficiency can be effectively improved, and the production cost is reduced; on the other hand, the testing and burning of the memory are finished by a whole set of system, so that the memory does not need to be frequently plugged and unplugged to transfer the memory for testing and burning, and the memory testing process is simplified.
EXAMPLE five
In some optional embodiments, as shown in fig. 4, the step of adjusting the unmatched parameters according to the preset adjustment rule and burning the adjusted parameters to the SPD chip of the tested memory includes:
s1410, obtaining the type information of the tested memory;
s1420, selecting SPD information corresponding to the category information from a preset SPD database;
and S1430, burning the SPD information serving as the adjusted parameters to the SPD chip of the tested memory.
When the SPD information is implemented, the tested memory is plugged in the memory slot of the test board, the test board is plugged in the connecting slot of the main control board, and the main control processor automatically identifies the type of the memory according to the IO of the memory through the test board and then automatically selects the corresponding SPD information. Optionally, an SPD database is provided in the test system, the SPD database stores SPD information of different memory types, and the master processor may obtain the SPD information corresponding to the type of the memory to be tested by traversing the SPD database. And then, using the obtained SPD information as an adjusted parameter, specifically, adjusting relevant parameters of the tested memory by the MCU processor according to the obtained SPD information, for example, adjusting the frequency or the timing sequence and burning the adjusted SPD information into an SPD chip of the tested memory.
Example six
In some optional embodiments, as shown in fig. 5, after the steps of adjusting the unmatched parameters according to the preset adjustment rule and burning the adjusted parameters to the SPD chip of the tested memory, the method further includes:
s1600, repeatedly executing the steps of testing the tested memory plugged into the memory slot and burning the adjusted parameters to the SPD chip of the tested memory, and recording the repeated times;
and S1700, reporting an error when the repetition times reach a preset threshold value.
Optionally, after the adjusted parameters are burned into the SPD chip of the tested memory, the tested memory needs to be tested again. Specifically, after burning the adjusted parameters into the SPD chip of the tested memory, the main control processor and the MCU processor together circularly execute the steps S1100 to S1400, and the situation that the memory product cannot normally work due to unsuccessful single burning of the SPD information of the tested memory is avoided by testing the tested memory for many times and burning the SPD information of the tested memory again when the test fails.
In implementation, in order to avoid entering infinite repeated execution of the test and burning processes, when the step of repeatedly executing the step of testing the tested memory plugged into the memory slot to burn the adjusted parameters into the SPD chip of the tested memory is performed, the number of times of repetition can be recorded simultaneously, when the number of times of repetition reaches a preset threshold value, for example, the number of times of repetition reaches 5 times, 7 times or 10 times, it is determined that the tested memory has a defect that the normal working state cannot be returned by burning the SPD information again, and at this time, an error can be reported.
Optionally, the system error reporting includes, but is not limited to, a light error reporting, a sound error reporting, and an error reporting message uploading, and is not limited herein.
It should be noted that the preset threshold is not limited to the above 5 times, 7 times or 10 times, and in other embodiments, the preset threshold may also take other values, which is not limited herein.
It can be clearly understood by those skilled in the art that, for convenience and convenience of description, reference may be made to the corresponding structures and implementation principles in the first to third embodiments of the foregoing automatic memory parameter adjustment control method, and details are not described herein again.
EXAMPLE seven
In some optional embodiments, as shown in fig. 6, the present application further provides an automatic memory parameter adjustment control device, which is applied to the automatic memory parameter adjustment system described above, where the automatic memory parameter adjustment system includes a test board and a main control board, the test board has a plurality of memory slots for plugging a memory to be tested and an MCU processor connected to the memory slots, the main control board has a connection slot for plugging and matching with the test board and a main control processor connected to the connection slot, and the automatic memory parameter adjustment control device provided in the present application includes:
a test execution unit 2100, configured to test a memory under test plugged into a memory slot;
a result obtaining unit 2200, configured to obtain a test result, and determine whether the test is successful according to the test result;
a parameter determining unit 2300, configured to determine, when the test is determined to fail, a parameter that is not matched between the memory under test and the main control board according to the test result;
and a parameter adjusting unit 2400, configured to adjust the unmatched parameters according to a preset adjustment rule, and burn the adjusted parameters into the SPD chip of the tested memory.
The test board is provided with a plurality of memory slots and an MCU processor, the memory slots can be used for being plugged with a tested memory, the main control board is provided with a connecting slot and a main control processor, the test board can be plugged and matched with the connecting slot, the MCU processor is connected with the main control processor, in the test process, the test board provided with the tested memory is plugged in the connecting slot on the main control board, the MCU processor realizes the mode of automatically controlling the communication between the test board and the main control board, the main control board can test the tested memory and receive the test result, the test board can capture unmatched parameters between the tested memory and the main control board generated in the test process, and then the parameters are adjusted and then burnt into the SPD chip of the tested memory again. On one hand, the testing of the memory is finished by the main control board, the parameter grabbing, the parameter adjusting and the SPD burning are automatically realized by the test board, manual participation is not needed, the memory testing efficiency can be effectively improved, and the production cost is reduced; on the other hand, the testing and burning of the memory are finished by a whole set of system, so that the memory does not need to be frequently plugged and unplugged to transfer the memory for testing and burning, and the memory testing process is simplified.
Further, the parameter adjusting unit 2400 includes:
the information acquisition subunit is used for acquiring the type information of the tested memory;
the information selection subunit is used for selecting SPD information corresponding to the category information from a preset SPD database;
and the information burning subunit is used for burning the SPD information serving as the adjusted parameter to the SPD chip of the tested memory.
Further, the apparatus further comprises:
the repeated testing unit is used for repeatedly executing the steps of testing the tested memory plugged into the memory slot until the adjusted parameters are burned into the SPD chip of the tested memory, and recording the repeated times;
and the error reporting execution unit is used for reporting errors when the repetition times reach a preset threshold value.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the structure and implementation principle of the above described automatic memory parameter adjustment control apparatus may refer to the corresponding structure and implementation principle in the first to sixth embodiments, and are not described herein again.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An automated memory parameter adjustment system, comprising:
the test board comprises a plurality of memory slots for inserting the tested memory and an MCU (microprogrammed control unit) processor connected with the memory slots; and
the main control board comprises a connecting slot which is in plug-in fit with the test board and a main control processor which is connected with the connecting slot;
the main control board is used for testing the tested memory through the test board, receiving a test result returned by the test board, transmitting unmatched parameters between the tested memory and the main control board to the test board according to the test result, adjusting the parameters and burning the parameters to the SPD chip of the tested memory.
2. The automated memory parameter adjustment system of claim 1, further comprising a display connected to the master control board.
3. The automated memory parameter tuning system of claim 1, wherein the test performed on the memory under test is an AIDA64 test.
4. The automated memory parameter adjusting system of claim 1, wherein the test board further comprises a power supply module and a signal conversion module;
the power supply module is connected with the memory slots and the MCU processor and supplies power to the memory slots and the MCU processor;
the signal conversion module is connected with the memory slots and the serial ports of the test boards, and the serial ports are used for being matched with the connecting slots in an inserted mode.
5. An automatic memory parameter adjusting control method is applied to an automatic memory parameter adjusting system, the automatic memory parameter adjusting system comprises a test board and a main control board, the test board is provided with a plurality of memory slots for plugging tested memories and an MCU processor connected with the memory slots, the main control board is provided with a connecting slot matched with the test board in a plugging mode and a main control processor connected with the connecting slot, and the method is characterized by comprising the following steps:
testing the tested memory plugged in the memory slot;
obtaining a test result, and judging whether the test is successful according to the test result;
when the test is judged to fail, determining unmatched parameters between the tested memory and the main control board according to the test result;
and adjusting the unmatched parameters according to a preset adjustment rule, and burning the adjusted parameters to the SPD chip of the tested memory.
6. The method according to claim 5, wherein the step of adjusting the unmatched parameters according to a preset adjustment rule and burning the adjusted parameters to the SPD chip of the tested memory comprises:
acquiring the category information of the tested memory;
selecting SPD information corresponding to the category information from a preset SPD database;
and burning the SPD information serving as the adjusted parameter to the SPD chip of the tested memory.
7. The method according to claim 5, wherein after the step of adjusting the unmatched parameters according to a preset adjustment rule and burning the adjusted parameters to the SPD chip of the tested memory, the method further comprises:
repeatedly executing the step of testing the tested memory plugged into the memory slot until the adjusted parameters are burned into the SPD chip of the tested memory, and recording the repeated times;
and reporting an error when the repetition times reach a preset threshold value.
8. The utility model provides an automatic change memory parameter adjustment controlling means, is applied to in the automatic memory parameter adjustment system, automatic memory parameter adjustment system includes and surveys test panel and main control board, survey the test panel have be used for pegging graft by a plurality of memory slots of memory and with a plurality of memory slot connected's MCU treater, the main control board have with survey test panel grafting complex connection slot and with connection slot connected's main control treater, its characterized in that, the device includes:
the test execution unit is used for testing the tested memory plugged in the memory slot;
the result obtaining unit is used for obtaining a test result and judging whether the test is successful according to the test result;
the parameter determining unit is used for determining unmatched parameters between the tested memory and the main control board according to the test result when the test failure is judged;
and the parameter adjusting unit is used for adjusting the unmatched parameters according to a preset adjusting rule and burning the adjusted parameters to the SPD chip of the tested memory.
9. The automated memory parameter tuning control device of claim 8, wherein the parameter tuning unit comprises:
the information acquisition subunit is used for acquiring the type information of the tested memory;
an information selecting subunit, configured to select SPD information corresponding to the category information from a preset SPD database;
and the information burning subunit is used for burning the SPD information serving as the adjusted parameter to the SPD chip of the tested memory.
10. The automated memory parameter adjustment control apparatus of claim 8, wherein the apparatus further comprises:
the device comprises a repeated test unit, a memory slot and an SPD chip, wherein the repeated test unit is used for repeatedly executing the steps of testing the tested memory plugged into the memory slot and burning the adjusted parameters into the SPD chip of the tested memory and recording the repeated times;
and the error reporting execution unit is used for reporting an error when the repetition times reach a preset threshold value.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI840227B (en) * | 2023-05-18 | 2024-04-21 | 威剛科技股份有限公司 | Memory programming equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI840227B (en) * | 2023-05-18 | 2024-04-21 | 威剛科技股份有限公司 | Memory programming equipment |
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