CN115729600A - NVDIMM (non-volatile memory Module) upgrading method and device, electronic equipment and computer storage medium - Google Patents

Abstract

The invention provides an NVDIMM (nonvolatile dual in-line memory module) upgrading method, an NVDIMM upgrading device, electronic equipment and a storage medium, wherein the method receives an upgrading instruction, the upgrading instruction at least carries indication information and address information, the indication information comprises information for indicating upgrading of the NVDIMM, and the address information comprises information for storing the address of a data packet; obtaining a data packet from a first memory based on the upgrade instruction, the first memory being a volatile memory in the NVDIMM; and upgrading by using the data packet. According to the method, the data packet for upgrading is stored in the first storage in advance and is directly acquired during upgrading, and the upgrading speed can be increased.

Description

NVDIMM (non-volatile memory Module) upgrading method and device, electronic equipment and computer storage medium

Technical Field

The present invention relates to the field of computer server technologies, and in particular, to a method and an apparatus for upgrading an NVDIMM, an electronic device, and a computer storage medium.

Background

NVDIMM (non-volatile dual in-line memory module) is mainly applied to a server, and is the same as a common memory bank in form. Referring to fig. 1 in particular, when the NVDIMM is upgraded online in the prior art, first the NVDIMM obtains an upgrade command and a data packet through an SMBUS (DSM) interface, that is, control data and upgraded firmware data, which are both sent to the NVDIMM through the SMBUS, and then the controller on the NVDIMM completes the upgrade, that is, the upgraded firmware data replaces the firmware data on the nonvolatile memory in the NVDIMM.

However, the maximum frequency of the data receiving interface corresponding to the nonvolatile memory is only 100KHZ, and when the upgrade package is slightly larger, the upgrade process is very slow.

Therefore, the prior art is in need of improvement.

Disclosure of Invention

The invention provides an NVDIMM upgrading method, an NVDIMM upgrading device, electronic equipment and a computer storage medium, which can improve upgrading speed.

In order to solve the above technical problem, a first technical solution provided by the present invention is: provided is an NVDIMM upgrading method, which comprises the following steps: receiving an upgrading instruction, wherein the upgrading instruction at least carries indication information and address information, the indication information comprises information for indicating upgrading of a nonvolatile dual in-line memory module (NVDIMM), and the address information comprises information of an address of a storage data packet; acquiring a data packet from a first memory based on the upgrading instruction; the first memory is a volatile memory in the NVDIMM and is upgraded by the data packet.

Before the step of receiving the upgrade instruction, the method further includes: receiving the data packet by using a first memory interface, and storing the data packet into the first memory; and sending storage parameters to first equipment, wherein the storage parameters at least comprise address information for storing the data packet, and the first equipment comprises equipment for sending the upgrading instruction.

Before receiving the upgrade instruction, the method further includes: and dividing the first memory to obtain a reserved area, wherein the reserved area comprises an area for storing the data packet.

Wherein, the step of receiving the upgrade order comprises: receiving the upgrade instruction through a first memory interface; or receiving the upgrading instruction through the SMBUS interface.

In order to solve the above technical problem, the second technical solution provided by the present invention is: an NVDIMM upgrading apparatus is provided, including: the system comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving an upgrading instruction, the upgrading instruction at least carries indication information and address information, the indication information comprises information for indicating upgrading of a nonvolatile dual in-line memory module (NVDIMM), and the address information comprises information for storing the address of a data packet; the obtaining module is used for obtaining a data packet from a first memory based on the upgrading instruction, wherein the first memory is a volatile memory in the NVDIMM; and the upgrading module is used for upgrading by utilizing the data packet.

In order to solve the above technical problem, a third technical solution provided by the present invention is: an NVDIMM upgrading method is provided, which comprises the following steps: sending an upgrade instruction to enable an NVDIMM to acquire a data packet from a first memory and upgrade the data packet based on the data packet, wherein the first memory is a volatile memory in the NVDIMM, the upgrade instruction at least carries indication information and address information, the indication information comprises information indicating that the NVDIMM is upgraded, and the address information comprises information of an address for storing the data packet.

Wherein, before the step of sending the upgrade instruction, the method comprises: sending the data packet to the NVDIMM using a first memory interface; and receiving storage parameters sent by the NVDIMM, wherein the storage parameters at least comprise address information for storing the data packet.

Wherein, before the step of sending the data packet to the NVDIMM by using the first memory interface, the method further comprises: determining whether the data packet is a big data packet or not according to a preset condition; the sending of the upgrade instruction includes: if the data packet is determined to be a large data packet, the data packet is sent to the NVDIMM through the first memory interface.

The step of sending the upgrade instruction includes: sending the upgrading instruction through a first memory interface; or sending the upgrading instruction through an SMBUS interface.

In order to solve the above technical problems, a fourth technical solution provided by the present invention is: an NVDIMM upgrading apparatus is provided, including: the system comprises an upgrade instruction sending module and an upgrade instruction updating module, wherein the upgrade instruction sending module is used for sending an upgrade instruction so that the NVDIMM can obtain a data packet from a first memory and upgrade the data packet based on the data packet, the first memory is a volatile memory in the NVDIMM, the upgrade instruction at least carries indication information and address information, the indication information comprises information indicating that the NVDIMM is upgraded, and the address information comprises information of an address of a storage data packet.

In order to solve the above technical problem, a fifth technical solution provided by the present invention is: there is provided an electronic device comprising an interconnected memory storing program instructions and a processor for retrieving the program instructions from the memory to implement any of the NVDIMM upgrading methods described above.

In order to solve the above technical problem, a sixth technical solution provided by the present invention is: an NVDIMM upgrade system is provided, comprising: the NVDIMM upgrading apparatus according to claim 6 and the NVDIMM upgrading apparatus according to claim 11, connected therebetween.

The NVDIMM upgrading method has the advantages that when upgrading is needed, the data packet needed by upgrading is obtained from the first memory, upgrading is conducted through the data packet, and the first memory is a volatile memory because the data packet is stored in the first memory in advance. The upgrade speed can be improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic diagram of a prior art CPU to NVDIMM connection;

fig. 2 is a schematic flowchart of a first embodiment of the NVDIMM upgrading method of the present application;

fig. 3 is a schematic flowchart of a second embodiment of the NVDIMM upgrading method of the present application;

FIG. 4 is a schematic diagram of the connection between the CPU and the NVDIMM according to the present application;

fig. 5 is a schematic structural diagram of a first embodiment of an NVDIMM upgrading apparatus of the present application;

fig. 6 is a schematic flowchart of a third embodiment of the NVDIMM upgrading method of the present application;

fig. 7 is a schematic flowchart of a fourth embodiment of the NVDIMM upgrading method of the present application;

fig. 8 is a schematic structural diagram of a second embodiment of the NVDIMM upgrading apparatus of the present application;

FIG. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of an embodiment of a computer-readable storage medium according to the present invention;

fig. 11 is a schematic structural diagram of an NVDIMM upgrading system according to an embodiment of the present invention.

Detailed Description

As shown in fig. 1, when the NVDIMM is upgraded online in the prior art, a CPU (central processing unit) uses an SMBUS (DSM) interface to send upgraded firmware data to an NVDIMM controller, and then the upgraded firmware data is stored on a non-volatile memory, such as FLASH or EEPROM, of the NVDIMM by the NVDIMM controller. The nonvolatile memory and the controller are connected by an I2C bus, QSPI interface, parallel port, etc. However, the maximum frequency of SMBUS is only 100KHZ, and when the upgrade package is slightly larger, the upgrade process is very slow.

The application provides an NVDIMM upgrading method which can greatly improve upgrading efficiency. The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 2, a schematic flow chart of a first embodiment of the NVDIMM upgrading method of the present invention specifically includes:

step S11: and receiving an upgrading instruction.

Specifically, when the NVDIMM needs to be upgraded, the CPU sends an upgrade command to the NVDIMM, and the NVDIMM receives the upgrade command. The upgrade command is a command signal for driving the NVDIMM for upgrading. NVDIMM upgrades mean modifications to the underlying software to replace it to add new functionality or better work to the hardware.

In one embodiment, the upgrade order carries at least indication information and address information. Wherein the indication information includes information indicating an upgrade to a non-volatile dual in-line memory module, NVDIMM. The address information includes information of an address where the data packet is stored. Specifically, when the NVDIMM is upgraded, the controller of the NVDIMM needs to obtain the data packet from the corresponding storage address, and therefore, the NVDIMM needs to receive the specifically stored address information of the data packet required for the upgrade while receiving the indication information indicating the upgrade. It should be noted that the information of the address for storing the data packet may include start address information and may also include end address information. Further, the start address information and the end address information can be included at the same time.

Further, in an embodiment, the address information may further include a start address of the packet storage and size information of the packet. Of course, in another embodiment, the address information may also include an end address of the data packet storage and size information of the data packet.

Step S12: and acquiring the data packet from the first memory based on the upgrading instruction.

After receiving the upgrade command, the NVDIMM obtains a data packet required for the upgrade from the first memory based on the upgrade command. The data packet includes firmware that upgrades the NVDIMM. NVDIMM upgrades mean modifications to the underlying software to replace it to add new functionality or better work to the hardware. The data package includes data, such as code, that modifies the underlying software.

In one embodiment, the first memory is a volatile memory. In a preferred embodiment, the first memory is a double data rate synchronous dynamic random access memory (DDR). As can be appreciated, the data packet contains information that modifies the underlying software. The first memory is a volatile memory, e.g., in one embodiment, the first memory is a DDR.

Step S13: and upgrading by using the data packet.

And after the data packet is obtained, upgrading by using the data packet.

According to the upgrading method, the data packet required by upgrading is stored in the first storage in advance, and the data packet is directly acquired from the first storage when the upgrading is required, so that the upgrading speed can be increased.

Referring to fig. 3, a flowchart of a second embodiment of the NVDIMM upgrading method of the present invention is shown, wherein steps S23 to S25 are the same as steps S11 to S13 in the first embodiment shown in fig. 1, except that the present embodiment further includes, before step S23:

step S21: a data packet is received by a first memory interface and stored in the first memory.

Specifically, a first memory interface is used for receiving a data packet and storing the data packet into a first memory. In an embodiment, the method described in this embodiment is applied to NVDIMMs. That is, the NVDIMM establishes a connection with the packet sender through the first memory interface.

In one embodiment, the sender of the data packet is a CPU, and the NVDIMM establishes a connection with the CPU via a double data rate synchronous dynamic random access memory (DDR) interface, as shown in fig. 4. In this manner, the NVDIMM receives the data packet using a double rate synchronous dynamic random access memory (DDR) interface and stores the data packet into a double rate synchronous dynamic random access memory (DDR) of the NVDIMM.

In this embodiment, the data transceiving frequency of the double data rate synchronous dynamic random access memory (DDR) interface is high, and even if the data packet is large, the upgrading process is very fast.

After the data packet is received and stored, in response to receiving an upgrade instruction, the data packet is upgraded based on the upgrade instruction. The upgrade process is very fast since the data packets are received over a double data rate synchronous dynamic random access memory (DDR) interface.

In one embodiment, the NVDIMM receives the upgrade directive and obtains a memory address. It will be appreciated that the memory address is the memory address of the data packet. And when upgrading is carried out, the data packet is obtained based on the storage address, and the data packet is utilized for upgrading.

Step S22: the storage parameter is sent to the first device.

In one embodiment, after the NVDIMM stores the data packet in the first memory, the NVDIMM needs to send further parameters to the first device, for example, the CPU. The storage parameters at least include address information stored in the data packet, and specifically, after the NVDIMM stores the data packet in the first memory, the information of the address of the data packet needs to be further sent to the CPU. The address information of the data packet may include start address information and may also include end address information. Further, the start address information and the end address information may be included at the same time. In an embodiment, the address information may further include a start address of the packet storage and size information of the packet. Of course, in another embodiment, the address information may also include an end address of the data packet storage and size information of the data packet.

In a possible embodiment, the storage parameter may further include a name of the data packet, and when a plurality of data are stored in the storage address, the data packet may be further obtained accurately by using the name of the data packet in cooperation with the storage address of the data packet and the size of the data packet.

In an embodiment of the present application, before receiving the upgrade instruction, the first memory needs to be further divided to obtain a reserved area, where the reserved area includes an area for storing the data packet. Specifically, in an embodiment, the reserved area is a randomly acquired memory address of the double rate synchronous dynamic random access memory. For example, when the upgrade is needed, a block of memory is randomly divided from the double-rate synchronous dynamic random access memory, and the data packet used for the upgrade is stored in the divided memory. However, when there is not enough memory in the DDR, it needs to occupy other already used space, which may result in the original data structure in the DDR being destroyed.

Or in another embodiment, the reserved area is a preset memory address of the double-rate synchronous dynamic random access memory. Specifically, the DDR is preferentially reserved with enough memory, the reserved memory cannot be occupied, and when the upgrading is needed, the data packet is received from the CPU and stored in the reserved space. Since the packet itself is not very large, it is sufficient to reserve only a few M of space. The method can avoid damaging the data structure, only wastes M space, and pays a prize corresponding to dozens of G space of DDR, and the prize can be ignored.

In a possible embodiment, the NVDIMM still receives an upgrade directive based on a first memory interface, such as a double data rate synchronous dynamic random access memory (DDR) interface. In another possible embodiment, the updating instruction may be received based on a SMBUS (DSM) interface, and since the order of magnitude of the updating instruction is small, the frequency of the SMBUS (DSM) interface does not affect the transmission rate, and thus the updating process is not affected.

In one embodiment, in order to avoid the upgrade process from being affected, when the data packet is obtained from the first memory based on the upgrade instruction, the connection between the first memory and an external device is closed, and the external device includes a device connected with the NVDIMM. In one embodiment, the external device may be a CPU.

In one embodiment, after receiving the upgrade command, the NVDIMM needs to switch the control right of the first memory, for example, a double data rate synchronous dynamic random access memory (DDR) to the controller of the NVDIMM, and in this process, the CPU cannot access the memory of the NVDIMM, that is, the CPU cannot access the double data rate synchronous dynamic random access memory (DDR). At this time, the controller of the NVDIMM accesses a double data rate synchronous dynamic random access memory (DDR) and performs upgrading by using a data packet stored in the double data rate synchronous dynamic random access memory (DDR).

In another embodiment, the controller of the NVDIMM accesses a double data rate synchronous dynamic random access memory (DDR), copies and stores the data packets into the nonvolatile memory of the NVDIMM, and then upgrades them.

In one embodiment, when an upgrade is required and an upgrade command is received, the controller of the NVDIMM divides a block of memory from a double data rate synchronous dynamic random access memory (DDR), and then stores the received data packet into the divided memory. However, when there is not enough memory in the DDR, it needs to occupy other used space, which may result in the data structure in the DDR being damaged.

In another embodiment, the DDR can reserve enough memory preferentially, the reserved memory cannot be occupied, and when the upgrade is needed, the packet received from the CPU is stored in the reserved space. Since the packet itself is not very large, it is sufficient to reserve only a few M of space. The method can avoid damaging the data structure, only wastes M space, and pays a prize corresponding to dozens of G space of DDR, and the prize can be ignored.

In an embodiment, after the upgrade is completed, the NVDIMM may also send a feedback command to feedback whether the upgrade is successful. Specifically, the NVDIMM sends a feedback command to the CPU to feed back the upgrade result to the CPU.

The method can optimize the existing upgrading time from a small time unit to a second unit, thereby greatly improving the upgrading speed.

Fig. 5 is a schematic structural diagram of an NVDIMM upgrading apparatus according to a first embodiment of the present invention, which includes: a receiving module 21, an obtaining module 22 and an upgrading module 23.

The receiving module 21 is configured to receive an upgrade instruction. The upgrading instruction at least carries indication information and address information, the indication information comprises information indicating upgrading of a nonvolatile dual in-line memory module (NVDIMM), and the address information comprises information of addresses of stored data packets.

In an embodiment, the obtaining module 22 is configured to obtain the data packet from a first memory based on the upgrade instruction, where the first memory is a volatile memory in the NVDIMM.

The upgrade module 23 is configured to upgrade with the data packet.

In an embodiment, the receiving module 21 is configured to receive a data packet by using a first memory interface, and store the data packet in the first memory. In this embodiment, the receiving module 21 may receive the data packet by using a double-rate synchronous dynamic random access memory interface, and store the data packet in a double-rate synchronous dynamic random access memory of the NVDIMM (non-volatile dual in-line memory module).

In an embodiment, the receiving module 21 is further configured to send a storage parameter to the first device, where the storage parameter at least includes address information for storing the data packet, and the first device includes a device for sending the upgrade instruction.

In an embodiment, the receiving module 21 is further configured to divide the first memory to obtain a reserved area, where the reserved area includes an area for storing the data packet.

In an embodiment, the upgrade module 23 is further configured to close the connection between the first memory and an external device, where the external device includes a device connected to the NVDIMM.

In an embodiment, the upgrade module 23 is further configured to send a feedback instruction to feed back whether the upgrade is successful.

The upgrading device shown in this embodiment may store a data packet required for upgrading in a first memory, for example, a DDR memory in advance, and acquire the data packet from the DDR memory for upgrading when upgrading is required, so as to improve the upgrading speed. Furthermore, the data packet is received through the double-rate synchronous dynamic random access memory interface, the existing upgrading time can be optimized from a small time unit to a second unit, and the upgrading speed is greatly improved.

Referring to fig. 6, a schematic flow chart of a third embodiment of the NVDIMM upgrading method of the present invention specifically includes:

step S31: and sending an upgrade instruction to enable the NVDIMM to acquire a data packet from a first memory, and upgrading the data packet based on the data packet, wherein the first memory is a volatile memory.

Specifically, the method of the embodiment is applied to the CPU side, and when the NVDIMM needs to be upgraded, the CPU sends an upgrade instruction to the CPU side, so that the NVDIMM acquires the data packet from the first memory and upgrades the data packet. The first memory is a volatile memory in the NVDIMM, the upgrade instruction at least carries indication information and address information, the indication information comprises information indicating that the NVDIMM is upgraded, and the address information comprises information of addresses for storing data packets. In one embodiment, the first memory is a DDR.

In this embodiment, since the data packet is stored in the first memory in advance, the upgrade speed can be increased.

Wherein, the upgrade order carries at least indication information and address information. Wherein the indication information includes information indicating that the non-volatile dual in-line memory module NVDIMM is upgraded. The address information includes information of an address where the data packet is stored. Specifically, when the NVDIMM is upgraded, the controller of the NVDIMM needs to obtain the data packet from the corresponding storage address, and therefore, the NVDIMM needs to receive the specifically stored address information of the data packet required for upgrading while receiving the indication information indicating upgrading. It should be noted that the information of the address storing the data packet may include start address information and may also include end address information. Further, the start address information and the end address information can be included at the same time.

Further, in an embodiment, the address information may further include a start address of the packet storage and size information of the packet. Of course, in another embodiment, the address information may also include an end address of the data packet storage and size information of the data packet.

In one possible embodiment, the CPU sends the upgrade instructions based on a first memory interface, such as a double data rate synchronous dynamic random access memory (DDR) interface. In another possible embodiment, the CPU may also send an upgrade instruction based on the SMBUS (DSM) interface, and since the order of magnitude of the upgrade instruction is small, the frequency of the SMBUS (DSM) interface does not affect the transmission rate and thus the upgrade process.

Further, please refer to fig. 7, which is a flowchart illustrating a fourth embodiment of the NVDIMM upgrading method according to the present invention, wherein step S43 is the same as step S31 shown in fig. 6, except that the present embodiment further includes, before step S43:

step S41: the data packet is sent to the NVDIMM using a first memory interface.

Specifically, the method of the embodiment is applied to the CPU side, and when the NVDIMM needs to be upgraded, the CPU sends the data packet to the NVDIMM by using the first memory interface. The NVDIMM, upon receiving the data packet, stores the data packet in the first memory. The first memory interface is a DDR interface.

Step S42: and receiving storage parameters sent by the NVDIMM, wherein the storage parameters at least comprise address information for storing the data packet.

Specifically, the CPU sends the data packet to the NVDIMM using the first memory interface. The NVDIMM, upon receiving the data packet, stores the data packet in the first memory. Further, the NVDIMM sends the address information and/or the packet size of the storage packet to the CPU as a storage parameter, and the CPU receives the storage parameter. When the NVDIMM needs to be upgraded, the CPU sends the address information in the storage parameter, and/or the size of the data packet and upgrading indication information to the NVDIMM as an upgrading instruction, so that the NVDIMM obtains the data packet based on the address information and/or the size of the data packet and upgrades the data packet based on the indication information.

In a particular embodiment, the CPU sends the data packet to the NVDIMM using a double rate synchronous dynamic random access memory interface. The NVDIMM stores the data packet into a double-rate synchronous dynamic random access memory of the NVDIMM after receiving the data packet.

In one embodiment, in response to an NVDIMM needing to be upgraded, sending the data packet to the NVDIMM using the double-rate synchronous dynamic random access memory interface based on a memory address, and storing the data packet into the double-rate synchronous dynamic random access memory of the NVDIMM; and sending the storage address and the parameter information of the data packet to the NVDIMM. Specifically, when the NVDIMM needs to be upgraded, the CPU acquires a DDR memory address in the NVDIMM, sends a data packet to the NVDIMM by using a DDR interface based on the memory address, and stores the data packet into the double-rate synchronous dynamic random access memory. Further, the CPU sends the memory address and parameter information of the data packet to the NVDIMM. Because the memory occupied by the parameter information of the storage address and the data packet is less, the storage address and the parameter information of the data packet can be sent by directly utilizing the SMBUS (DSM) interface, and the frequency of the SMBUS (DSM) interface cannot influence the transmission rate and further cannot influence the upgrading process.

In one embodiment, the first memory of the NVDIMM is divided into a predetermined area, and the predetermined area is used for storing the data packet. Specifically, the preset area is a randomly acquired storage address of the double-rate synchronous dynamic random access memory. For example, when the upgrade is needed, a block of memory is randomly divided from the double-rate synchronous dynamic random access memory, and the data packet used for the upgrade is stored in the divided memory. However, when there is not enough memory in the DDR, it needs to occupy other used space, which may result in the data structure in the DDR being damaged.

Or in another embodiment, the preset area is a preset storage address of the double-rate synchronous dynamic random access memory. Specifically, the DDR is preferentially reserved with enough memory, the reserved memory cannot be occupied, and when the upgrading is needed, the data packet is received from the CPU and stored in the reserved space. Since the packet itself is not very large, it is sufficient to reserve only a few M of space. The method can avoid damaging the data structure, only wastes M space, and pays a prize corresponding to dozens of G space of DDR, and the prize can be ignored.

After the data packet is sent to the NVDIMM by the CPU, an upgrading instruction is sent to the NVDIMM, so that the NVDIMM can be upgraded based on the data packet.

In another embodiment, the CPU further receives a feedback instruction to determine whether the NVDIMM is successfully upgraded. Specifically, if the feedback instruction shows that the upgrade is successful, the upgrade is completed. If the feedback command indicates that the upgrade fails, the upgrade command may be re-sent, so that the NVDIMM may be upgraded again. Or the data packet may also be resent, thereby causing the NVDIMM to be upgraded again. The problem that the data packet is damaged and cannot be upgraded is avoided.

In another embodiment of the present application, the CPU may determine whether the data packet is a big data packet according to a preset condition before sending the data packet. For example, if the size of the data packet is larger than a preset value, the data packet is determined to be a big data packet. In order to guarantee the transmission efficiency and the upgrade speed of the data packet, the data packet is sent to the NVDIMM through the first memory interface, for example, the DDR interface. Due to the high data transceiving frequency of a double data rate synchronous dynamic random access memory (DDR) interface, the upgrading process can be very fast even if the data packet is large. Therefore, the existing upgrading time can be optimized from a small time unit to a second unit, and the upgrading speed is greatly improved. And if the size of the data packet is not larger than the preset value, determining that the size of the data packet is a small data packet. At this time, on one hand, the data packet can be sent to the NVDIMM by using the DDR interface. On the other hand, the data packet may still be sent to the NVDIMM using a non-volatile memory interface such as the SMBUS interface. Because the data packet is smaller, the transmission speed is not influenced, and the upgrading speed is not influenced.

According to the method, the data packet is sent through the double-rate synchronous dynamic random access memory interface, the existing upgrading time can be optimized from a small-time unit to a second unit, and the upgrading speed is greatly improved.

Referring to fig. 8, a schematic structural diagram of a second embodiment of the NVDIMM upgrading apparatus of the present invention specifically includes: the upgrade instruction transmission module 81.

The upgrade instruction sending module 81 sends an upgrade instruction, so that the NVDIMM acquires a data packet from a first memory, and performs upgrade based on the data packet, where the first memory is a volatile memory in the NVDIMM, the upgrade instruction at least carries indication information and address information, the indication information includes information indicating to upgrade the NVDIMM, and the address information includes information of an address where the data packet is stored.

Specifically, in an embodiment, the upgrade order sending module 81 is further configured to send the data packet to the NVDIMM using the first memory interface.

In an embodiment, the upgrade instruction sending module 81 is further configured to receive a storage parameter sent by the NVDIMM, where the storage parameter at least includes address information for storing the data packet.

In an embodiment, the upgrade instruction sending module 81 is further configured to determine whether the data packet is a big data packet according to a preset condition; if the data packet is determined to be a large data packet, the data packet is sent to the NVDIMM through the first memory interface.

In one embodiment, the upgrade instruction sending module 81 sends the upgrade instruction through a first memory interface; or sending the upgrading instruction through an SMBUS interface.

In one embodiment, in response to an NVDIMM needing to be upgraded, the upgrade order sending module 81 sends the data packet to the NVDIMM using the double rate synchronous dynamic random access memory interface based on a memory address; the upgrade order sending module 81 also sends the memory address to the NVDIMM. Wherein, the memory address is the memory address of the double-rate synchronous dynamic random access memory which is randomly acquired; or, the storage address is a preset storage address of the double-rate synchronous dynamic random access memory.

In an embodiment, the upgrade instruction sending module 81 is further configured to receive a feedback instruction to determine whether the NVDIMM is upgraded successfully.

The device of the application sends the data packet through the double-rate synchronous dynamic random access memory interface, can optimize the existing upgrading time from a small time unit to a second unit, and greatly improves the upgrading speed.

Referring to fig. 9, which is a schematic structural diagram of an embodiment of an electronic device according to the present invention, the electronic device includes a memory 202 and a processor 201 that are connected to each other.

The memory 202 is used to store program instructions implementing the method of any of the above.

The processor 201 is used to execute program instructions stored by the memory 202.

The processor 201 may also be referred to as a Central Processing Unit (CPU). The processor 201 may be an integrated circuit chip having signal processing capabilities. The processor 201 may also be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The storage 202 may be a memory bank, a TF card, etc., and may store all information in the electronic device of the device, including the input raw data, the computer program, the intermediate operation results, and the final operation results. It stores and retrieves information based on the location specified by the controller. With the memory, the electronic device can only have the memory function to ensure the normal operation. The memory of the electronic device is classified into a main memory (internal memory) and an auxiliary memory (external memory) according to the use, and also classified into an external memory and an internal memory. The external memory is usually a magnetic medium, an optical disk, or the like, and can store information for a long period of time. The memory is a storage unit on the motherboard, which is used for storing data and programs currently being executed, but is only used for temporarily storing the programs and the data, and the data is lost when the power is turned off or the power is cut off.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a system server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method of the embodiments of the present application.

Please refer to fig. 10, which is a schematic structural diagram of a computer-readable storage medium according to the present invention. The storage medium of the present application stores a program file 203 capable of implementing all the methods described above, wherein the program file 203 may be stored in the storage medium in the form of a software product, and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. The aforementioned storage device includes: various media capable of storing program codes, such as a usb disk, a mobile hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, or terminal devices, such as a computer, a server, a mobile phone, and a tablet.

Fig. 11 is a schematic structural diagram of an NVDIMM upgrading system according to an embodiment of the present invention, which specifically includes a first NVDIMM upgrading apparatus 200 and a second NVDIMM upgrading apparatus 300. The first NVDIMM upgrading apparatus 200 may be, for example, an NVDIMM, and the second NVDIMM upgrading apparatus 300 may be, for example, a CPU. The first NVDIMM upgrading apparatus 200 and the second NVDIMM upgrading apparatus 300 are connected with each other. In an embodiment, a wired connection, such as a bus, may be established between the first NVDIMM upgrading apparatus 200 and the second NVDIMM upgrading apparatus 300. In another embodiment, a wireless connection, such as a supportable network protocol, may be established between the first NVDIMM upgrading apparatus 200 and the second NVDIMM upgrading apparatus 300, which is not limited in particular.

It is understood that, in an embodiment, the first NVDIMM upgrading apparatus 200 may also be, for example, an electronic device including an NVDIMM, the second NVDIMM upgrading apparatus 300 may also be, for example, an electronic device including a CPU, a wireless connection may be established between the two electronic devices, for example, and the like.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (13)

1. An NVDIMM upgrading method, comprising:

receiving an upgrading instruction, wherein the upgrading instruction at least carries indication information and address information, the indication information comprises information indicating upgrading of a nonvolatile dual in-line memory module (NVDIMM), and the address information comprises information of an address of a storage data packet;

obtaining a data packet from a first memory based on the upgrade instruction, wherein the first memory is a volatile memory in the NVDIMM;

and upgrading by using the data packet.

2. The upgrade method according to claim 1, wherein the step of receiving an upgrade instruction is preceded by:

receiving the data packet by using a first memory interface, and storing the data packet into the first memory;

and sending storage parameters to first equipment, wherein the storage parameters at least comprise address information for storing the data packet, and the first equipment comprises equipment for sending the upgrading instruction.

3. The upgrade method according to claim 2, wherein before receiving the upgrade instruction, the method further comprises:

and dividing the first memory to obtain a reserved area, wherein the reserved area comprises an area for storing the data packet.

4. The upgrading method according to claim 1, wherein the step of obtaining the data package from the first memory based on the upgrading instruction further comprises:

closing the connection of the first memory to external devices, including devices connected to the NVDIMM.

5. The upgrade method according to claim 1, wherein the step of receiving an upgrade instruction comprises:

receiving the upgrade instruction through a first memory interface; or

And receiving the upgrading instruction through an SMBUS interface.

6. An NVDIMM upgrading apparatus, comprising:

the system comprises a receiving module and a processing module, wherein the receiving module is used for receiving an upgrading instruction, the upgrading instruction at least carries indication information and address information, the indication information comprises information for indicating upgrading of a nonvolatile dual in-line memory module (NVDIMM), and the address information comprises information for storing the address of a data packet;

the obtaining module is used for obtaining a data packet from a first memory based on the upgrading instruction, wherein the first memory is a volatile memory in the NVDIMM;

and the upgrading module is used for upgrading by utilizing the data packet.

7. An NVDIMM upgrading method, comprising:

sending an upgrade instruction to enable an NVDIMM to acquire a data packet from a first memory and upgrade based on the data packet, wherein the first memory is a volatile memory in the NVDIMM, the upgrade instruction at least carries indication information and address information, the indication information comprises information indicating that the NVDIMM is upgraded, and the address information comprises information of an address for storing the data packet.

8. The method of claim 7, wherein the step of sending upgrade instructions is preceded by:

sending the data packet to the NVDIMM using a first memory interface;

and receiving storage parameters sent by the NVDIMM, wherein the storage parameters at least comprise address information for storing the data packet.

9. The method of claim 8, wherein the step of sending the data packet to the NVDIMM using the first memory interface is preceded by the step of:

determining whether the data packet is a big data packet or not according to a preset condition;

the sending of the upgrade instruction includes:

if the data packet is determined to be a large data packet, the data packet is sent to the NVDIMM through the first memory interface.

10. The method of claim 7, wherein the step of sending upgrade instructions comprises:

sending the upgrade instruction through a first memory interface; or

And sending the upgrading instruction through an SMBUS interface.

11. An NVDIMM upgrading apparatus, comprising:

the system comprises an upgrade instruction sending module and an upgrade instruction updating module, wherein the upgrade instruction sending module is used for sending an upgrade instruction so that the NVDIMM can obtain a data packet from a first memory and upgrade the data packet based on the data packet, the first memory is a volatile memory in the NVDIMM, the upgrade instruction at least carries indication information and address information, the indication information comprises information indicating that the NVDIMM is upgraded, and the address information comprises information of an address of a storage data packet.

12. An electronic device, comprising an interconnected memory and a processor, wherein the memory stores program instructions, and the processor is configured to retrieve the program instructions from the memory to implement the NVDIMM upgrading method of any one of claims 1-5 and/or 7-10.

13. An NVDIMM upgrade system, comprising: the NVDIMM upgrading apparatus according to claim 6 and the NVDIMM upgrading apparatus according to claim 11, connected therebetween.

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