CN115714705B - IQ balance calibration method and device for radio frequency transmitting chip and storage medium - Google Patents
IQ balance calibration method and device for radio frequency transmitting chip and storage medium Download PDFInfo
- Publication number
- CN115714705B CN115714705B CN202211336707.0A CN202211336707A CN115714705B CN 115714705 B CN115714705 B CN 115714705B CN 202211336707 A CN202211336707 A CN 202211336707A CN 115714705 B CN115714705 B CN 115714705B
- Authority
- CN
- China
- Prior art keywords
- calibration parameter
- target
- value
- path
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000012360 testing method Methods 0.000 claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000004590 computer program Methods 0.000 claims description 16
- 230000010355 oscillation Effects 0.000 description 54
- 230000006870 function Effects 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses an IQ balance calibration method and device of a radio frequency transmitting chip and a storage medium, wherein the IQ balance calibration method of the radio frequency transmitting chip comprises the following steps: acquiring a first reference calibration parameter set corresponding to a target chip, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path; obtaining the local oscillator signal leakage value of the target chip by using the first reference calibration parameter set test; comparing the local oscillator signal leakage value with a leakage value threshold to obtain a first comparison result; and determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set is used for balancing signals of an I path and signals of a Q path of the target chip. By using the technical scheme, the IQ balance calibration efficiency of the radio frequency emission chip can be improved, so that the production cost of the chip is reduced.
Description
Technical Field
The invention relates to the technical field of chip manufacturing, in particular to an IQ balance calibration method and device of a radio frequency transmitting chip and a storage medium.
Background
The IQ balance of the radio frequency transmitting chip has great influence on the performance of the chip, and when the IQ is unbalanced, local oscillation leakage phenomenon can be generated. The local oscillation leakage phenomenon can lead the output signal of the chip not only to comprise the needed useful signal, but also to be mixed with the local oscillation signal, thereby causing the performance of the chip to be reduced. It is therefore necessary to calibrate the IQ balance of the chip.
In the prior art, when IQ balance calibration is performed on chips, all parameter sets of each chip need to be tested to obtain an optimal parameter set with optimal performance.
However, in the prior art, all parameter groups of each chip are tested, so that a lot of time is required, the testing efficiency is low, and the production cost of the chip is greatly increased.
Disclosure of Invention
The invention solves the technical problem of improving the efficiency of IQ balance calibration on the chip so as to reduce the production cost of the chip.
In order to solve the above technical problems, the present invention provides an IQ balance calibration method for a radio frequency transmitting chip, where the IQ balance calibration method for the radio frequency transmitting chip includes: acquiring a first reference calibration parameter set corresponding to a target chip, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path; obtaining the local oscillator signal leakage value of the target chip by using the first reference calibration parameter set test; comparing the local oscillator signal leakage value with a leakage value threshold to obtain a first comparison result; and determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set is used for balancing signals of an I path and signals of a Q path of the target chip.
Optionally, the determining the target calibration parameter set using the first comparison result includes: and when the first comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, taking the first reference calibration parameter set as the target calibration parameter set.
Optionally, the determining the target calibration parameter set using the first comparison result further includes: when the first comparison result indicates that the local oscillator signal leakage value reaches the leakage value threshold, selecting a plurality of calibration parameter values of an I path and a plurality of calibration parameter values of a Q path from adjacent values of the calibration parameter values of the I path and the calibration parameter values of the Q path in the first reference calibration parameter set respectively so as to obtain a plurality of second reference calibration parameter sets; obtaining local oscillator signal leakage values of the target chip by testing the plurality of second reference calibration parameter sets; comparing the local oscillator signal leakage value with the minimum value with a leakage value threshold to obtain a second comparison result; and when the second comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, taking the second reference calibration parameter set corresponding to the local oscillator signal leakage value with the minimum value as the target calibration parameter set.
Optionally, the obtaining the plurality of second reference calibration parameter sets includes: obtaining a compensation value; respectively adding and subtracting the calibration parameter value of the I path and the calibration parameter value of the Q path in the first reference calibration parameter set by utilizing the compensation value to determine a preset value range; and selecting a plurality of I-path calibration parameter values and a plurality of Q-path calibration parameter values within the preset value range to obtain a plurality of second reference calibration parameter sets.
Optionally, the IQ balance calibration method further comprises: when the first comparison result or the second comparison result indicates that the local oscillator signal leakage value reaches the leakage value threshold, determining a plurality of candidate calibration parameter values of a first path to obtain a plurality of first test calibration parameter sets, wherein the calibration parameter values of a second path in the first test calibration parameter sets are fixed values, the first path is one path of I paths and Q paths, and the second path is the other path of the I paths and the Q paths; testing by using the plurality of first test calibration parameter sets to obtain local oscillator signal leakage values of the target chip, and determining first target calibration parameter values of a first path corresponding to the local oscillator signal leakage values with the minimum values; determining a plurality of candidate calibration parameter values of a second path to obtain a plurality of second test calibration parameter sets, wherein the calibration parameter values of a first path in the second test calibration parameter sets are the first target calibration parameter values; testing by using the plurality of second test calibration parameter sets to obtain local oscillator signal leakage values of the target chip; comparing the local oscillator signal leakage value with the leakage value threshold with the minimum value to obtain a third comparison result, and determining a second target calibration parameter value of a second path corresponding to the local oscillator signal leakage value with the minimum value; and when the third comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, determining a target calibration parameter set of the target chip, wherein the target calibration parameter set comprises the first target calibration parameter value and the second target calibration parameter value.
Optionally, the IQ balance calibration method further comprises: when the third comparison result shows that the local oscillator signal leakage value reaches the leakage value threshold, determining a plurality of candidate calibration parameter values of a first path to obtain a plurality of third test calibration parameter sets, wherein the calibration parameter value of a second path in the third test calibration parameter sets is the second target calibration parameter value; testing by using the plurality of third test calibration parameter sets to obtain local oscillator signal leakage values of the target chip, and determining a third target calibration parameter value of a first path corresponding to the local oscillator signal leakage value with the minimum value; determining a plurality of candidate calibration parameter values of a second path to obtain a plurality of fourth test calibration parameter sets, wherein the calibration parameter values of the first path in the fourth test calibration parameter sets are the third target calibration parameter values; testing by using the fourth test calibration parameter sets to obtain local oscillator signal leakage values of the target chip; comparing the local oscillator signal leakage value with the leakage value threshold with the minimum value to obtain a fourth comparison result, and determining a fourth target calibration parameter value of a second path corresponding to the local oscillator signal leakage value with the minimum value; and when the fourth comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, determining a target calibration parameter set of the target chip, wherein the target calibration parameter set comprises the third target calibration parameter value and the fourth target calibration parameter value.
Optionally, the obtaining the first reference calibration parameter set corresponding to the target chip includes: and acquiring a target calibration parameter set of the calibrated target chip, and taking the target calibration parameter set of the calibrated target chip as a first reference calibration parameter set corresponding to the target chip.
Optionally, the IQ balance calibration method further comprises: and burning the target calibration parameter set to the firmware of the target chip.
The invention also discloses an IQ balance calibration device of the radio frequency transmitting chip, which comprises: the acquisition module is used for acquiring a first reference calibration parameter set corresponding to a target chip, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path; the test module is used for obtaining the local oscillator signal leakage value of the target chip by using the first reference calibration parameter set; the comparison module is used for comparing the local oscillator signal leakage value with a leakage value threshold to obtain a first comparison result; and the determining module is used for determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set is used for balancing signals of an I path and signals of a Q path of the target chip.
The invention also discloses a terminal device which comprises a memory and a processor, wherein the memory stores a computer program which can be run on the processor, and the computer program executes the steps of the IQ balance calibration method of any radio frequency transmitting chip when being run by the processor.
The invention also discloses a computer readable storage medium, which stores a computer program, wherein the computer readable storage medium is a nonvolatile storage medium or a non-transient storage medium, and the computer program executes the steps of the IQ balance calibration method of any radio frequency transmitting chip when being run by a processor.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
The invention provides an IQ balance calibration method of a radio frequency transmitting chip, which comprises the steps of obtaining a first reference calibration parameter set corresponding to a target chip to be calibrated, and obtaining a local oscillator signal leakage value of the target chip by utilizing the first reference calibration parameter set to test, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path; after the local oscillation signal leakage value is obtained, comparing the local oscillation signal leakage value with a leakage value threshold to obtain a first comparison result; and determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set can be used for balancing the I-path signal and the Q-path signal of the target chip. The invention directly obtains the calibration parameter sets adopted by other chips and tests the local oscillation signal leakage value by utilizing the characteristic that the calibration parameter values in the calibration parameter sets between chips of the same manufacturing process are similar. And comparing the local oscillation signal leakage value with a leakage value threshold, and performing IQ calibration by using the target calibration parameter set when the local oscillation signal leakage value meets the requirement. According to the invention, each calibration parameter set of the target chip is not required to be tested one by one, so that the IQ balance calibration time of the chip can be greatly shortened, and the generation cost of the chip is saved.
Further, when the local oscillator signal leakage value obtained by testing the first reference calibration parameter set does not meet the requirement, a plurality of second reference calibration parameter sets are determined from adjacent values of the calibration parameter values of the I path and the calibration parameter values of the Q path in the first reference calibration parameter set. When the local oscillator signal leakage value obtained by the second reference calibration parameter set test meets the requirement, the second reference calibration parameter set corresponding to the local oscillator signal leakage value with the minimum value can be used as the target calibration parameter set. By determining the second reference calibration parameter set in the adjacent values, the situation that the first reference calibration parameter set cannot meet the calibration requirement can be made up, the test times are greatly reduced compared with all tests, and the IQ balance calibration time of the chip can be shortened.
Further, when the local oscillator signal leakage value obtained by the second reference calibration parameter set test does not meet the requirement, the calibration parameter value of one of the I path or the Q path is fixed, and the optimal calibration parameter value of the other path is determined. By respectively determining the calibration parameter values of the I path and the Q path, the target calibration parameter set of the chip can be determined under a small number of test times, the IQ balance calibration time of the chip is shortened, and the problem that the second reference calibration parameter set cannot meet the calibration requirement is solved.
Drawings
Fig. 1 is an overall flowchart of an IQ balance calibration method of a radio frequency transmitting chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a method for testing a local oscillator signal leakage value according to an embodiment of the present invention;
fig. 3 is a specific flowchart of an IQ balance calibration method of a radio frequency transmitting chip according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram of an IQ balance calibration apparatus for a radio frequency transmitting chip according to an embodiment of the present invention.
Detailed Description
As described in the background art, IQ balance of a radio frequency transmitting chip has a great influence on the performance of the chip, and when IQ is unbalanced, the performance of the chip is reduced. In the prior art, when IQ balance calibration is performed on chips, all parameter sets of each chip need to be tested to obtain an optimal parameter set with optimal performance. However, in the prior art, all parameter groups of each chip are tested, so that a lot of time is required, the testing efficiency is low, and the production cost of the chip is greatly increased.
In the invention, a local oscillator signal leakage value of a target chip is obtained by obtaining a first reference calibration parameter set corresponding to the target chip to be calibrated and utilizing a first reference calibration parameter set to test, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path; after the local oscillation signal leakage value is obtained, comparing the local oscillation signal leakage value with a leakage value threshold to obtain a first comparison result; and determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set can be used for balancing the I-path signal and the Q-path signal of the target chip. The invention directly obtains the calibration parameter sets adopted by other chips and tests the local oscillation signal leakage value by utilizing the characteristic that the calibration parameter values in the calibration parameter sets between chips of the same manufacturing process are similar. And comparing the local oscillation signal leakage value with a leakage value threshold, and performing IQ calibration by using the target calibration parameter set when the local oscillation signal leakage value meets the requirement. According to the invention, each calibration parameter set of the target chip is not required to be tested one by one, so that the IQ balance calibration time of the chip can be greatly shortened, and the generation cost of the chip is saved.
Further, when the local oscillator signal leakage value obtained by testing the first reference calibration parameter set does not meet the requirement, a plurality of second reference calibration parameter sets are determined from adjacent values of the calibration parameter values of the I path and the calibration parameter values of the Q path in the first reference calibration parameter set. When the local oscillator signal leakage value obtained by the second reference calibration parameter set test meets the requirement, the second reference calibration parameter set corresponding to the local oscillator signal leakage value with the minimum value can be used as the target calibration parameter set. By determining the second reference calibration parameter set in the adjacent values, the situation that the first reference calibration parameter set cannot meet the calibration requirement can be made up, the test times are greatly reduced compared with all tests, and the IQ balance calibration time of the chip can be shortened.
Further, when the local oscillator signal leakage value obtained by the second reference calibration parameter set test does not meet the requirement, the calibration parameter value of one of the I path or the Q path is fixed, and the optimal calibration parameter value of the other path is determined. By respectively determining the calibration parameter values of the I path and the Q path, the target calibration parameter set of the chip can be determined under a small number of test times, the IQ balance calibration time of the chip is shortened, and the problem that the second reference calibration parameter set cannot meet the calibration requirement is solved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In a specific embodiment, due to the influence of factors such as a manufacturing process, IQ imbalance may exist in the I-path and the Q-path of the chip, for example, the phase difference between the phase of the signal passing through the I-path and the phase of the signal passing through the Q-path is not 90 °, or the amplitude of the signal passing through the I-path is different from the amplitude of the signal passing through the Q-path. In order to balance the signals of the I and Q paths, the low pass filter circuits of the I and Q paths may be respectively adjusted by using the calibration parameter values of the I and Q paths. Specifically, the resistance value of the feedback resistor of the operational amplifier in the low-pass filter may be configured by using the calibration parameter value, so as to change the amplification factor of the signal, and/or the capacitance value of the feedback capacitor in the low-pass filter may be configured by using the calibration parameter value, so that the phase of the signal is changed by adjusting the time delay, and the signal in the I path and the signal in the Q path reach balance. That is, the phase difference between the phase of the signal passing through the I path and the phase of the signal passing through the Q path is 90 °, and the amplitude of the signal passing through the I path is the same as the amplitude of the signal passing through the Q path.
Fig. 1 is an overall flowchart of an IQ balance calibration method for a radio frequency transmitting chip according to an embodiment of the present invention.
In a specific implementation, the IQ balance calibration method of the radio frequency transmitting chip described in the following steps 101 to 104 may be used in the terminal device. The steps described above may be specifically performed by the terminal device, or may be performed by a chip having a data processing function in the terminal device, or may be performed by a chip module of the chip having the data processing function in the terminal device.
Specifically, as shown in fig. 1, the IQ balance calibration method of the radio frequency transmitting chip may include the following steps:
in step 101, a first reference calibration parameter set corresponding to a target chip is obtained;
In step 102, a local oscillator signal leakage value of a target chip is obtained by testing a first reference calibration parameter set;
in step 103, comparing the local oscillation signal leakage value with a leakage value threshold to obtain a first comparison result;
in step 104, a target set of calibration parameters for the target chip is determined using the first comparison result.
It should be noted that, in the embodiment of the present invention, the target chip is a radio frequency transmitting chip.
In a specific embodiment, for a target chip for performing balance calibration of a first target chip to be calibrated, all candidate calibration parameter sets corresponding to the first target chip for performing balance calibration may be obtained, and the local oscillation signal leakage values are tested one by using each candidate calibration parameter set of the target chip, so as to obtain a plurality of local oscillation signal leakage values. And taking the candidate calibration parameter set corresponding to the local oscillator signal leakage value with the minimum value as a target calibration parameter set of the target chip, so as to perform IQ balance calibration of the target chip by utilizing the target calibration parameter set. The candidate calibration parameter sets are determined from values stored in the registers of the I-way and Q-way. For example, if the register sizes on the I and Q paths are 5 bits, the I and Q paths each have 2 5 candidate calibration parameter values, the candidate calibration parameter values on the I path may have a value range of [0,31], and the candidate calibration parameter values on the Q path may have a value range of [0,31].
In another embodiment, for a target chip for performing balance calibration of a first target chip to be calibrated, a preset calibration parameter set corresponding to the first target chip for performing balance calibration may be obtained, where the preset calibration parameter set may be set by a user. The preset calibration parameter set is used as a first reference calibration parameter set of the target chip, and the target calibration parameter set of the first calibrated target chip is determined according to steps 101 to 104 provided by the invention.
In a specific embodiment of step 101, the terminal device obtains a first reference calibration parameter set of a target chip currently requiring IQ balance calibration. The first reference calibration parameter set may be any calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and the calibration parameter set adopted by the chip is a target calibration parameter set obtained after the chip finishes balance calibration, and each calibration parameter set includes a calibration parameter value of an I path and a calibration parameter value of a Q path. For example, for a target chip that performs balance calibration for a second target chip of the plurality of target chips to be calibrated, a calibration parameter set adopted by a first target chip that completes balance calibration may be used as a first reference calibration parameter set of the target chip; for a third target chip to be calibrated, which performs balance calibration, a calibration parameter set adopted by the first or second target chip which completes balance calibration may be used as a first reference calibration parameter set of the target chip. Specifically, the target chips for IQ balance calibration may be fabricated from the same wafer.
In a specific embodiment of step 102, the corresponding parameters in the target chip are adjusted by using the calibration parameter value of the I path and the calibration parameter value of the Q path in the first reference calibration parameter set, and the target chip is tested under the current parameters to obtain the local oscillator signal leakage value of the target chip. The process of testing the local oscillator signal leakage value will now be described in detail with reference to fig. 2.
In a specific embodiment, the resistance value of the feedback resistor of the operational amplifier in the I-path low-pass filter may be configured by using the first reference calibration parameter value of the I-path in the first reference calibration parameter set, and the resistance value of the feedback resistor of the operational amplifier in the Q-path low-pass filter may be configured by using the second reference calibration parameter value of the Q-path, and/or the capacitance value of the feedback capacitor in the low-pass filter may be configured by using the first reference calibration parameter value of the I-path, and the capacitance value of the feedback capacitor in the low-pass filter may be configured by using the second reference calibration parameter value of the Q-path to the candidate calibration parameter value of the Q-path. And after the configuration of each parameter is completed, obtaining the local oscillator signal leakage value output by the target chip.
In a specific embodiment of step 103, the local oscillator signal leakage value obtained by the test is compared with a leakage value threshold to obtain a first comparison result. The first comparison result may indicate that the local oscillation leakage value reaches the leakage value threshold, or that the local oscillation leakage value does not reach the leakage value threshold.
It should be noted that, the leakage value threshold may be set according to the performance requirement of the chip, for example, when the local oscillator signal leakage value does not reach the set leakage value threshold, the chip may have better performance; when the local oscillation signal leakage value reaches the set leakage value threshold, the performance of the chip may be greatly affected. The leakage value threshold may be set according to practical situations, which is not limited by the present application.
It should be further noted that, when the local oscillation signal leakage value reaches the leakage value threshold, it may indicate that the local oscillation signal leakage value is greater than the leakage value threshold, and correspondingly, when the local oscillation signal leakage value does not reach the leakage value threshold, it indicates that the local oscillation signal leakage value is less than or equal to the leakage value threshold; or the local oscillation signal leakage value reaching the leakage value threshold may indicate that the local oscillation signal leakage value is greater than or equal to the leakage value threshold, and correspondingly, a local oscillation signal leakage value not reaching the leakage value threshold indicates that the local oscillation signal leakage value is less than the leakage value threshold, which is not limited in the present application.
In the embodiment of step 104, if the first comparison result indicates that the local oscillator signal leakage value does not reach the leakage value threshold, it is indicated that the target chip can control the local oscillator signal leakage value within the range meeting the requirement by using the first reference calibration parameter set, so as to meet the production requirement of the target chip, and the first reference calibration parameter set can be used as the target calibration parameter set. If the first comparison result indicates that the local oscillator signal leakage value reaches the leakage value threshold, it is indicated that the target chip cannot control the local oscillator signal leakage value within a range meeting the requirement by using the first reference calibration parameter set, and the local oscillator leakage phenomenon still has a larger influence on the performance of the target chip, so that the first reference calibration parameter set cannot be used as the target calibration parameter set.
It should be noted that, after the target calibration parameter set is obtained, a specific process of adjusting the I-path signal and the Q-path signal of the chip by using the target calibration parameter set may refer to the prior art, which is not described herein.
Further, after determining the target calibration parameter set of the target chip, the calibration parameter values of the I path and the calibration parameter values of the Q path in the target calibration parameter set may be burned into the storage firmware of the target chip. In particular, the parameter value in the storage firmware that controls the resistance value of the feedback resistor of the operational amplifier in the low-pass filter may be modified to the calibration parameter value in the target calibration parameter set and/or the parameter value that controls the capacitance value of the feedback capacitor in the low-pass filter may be modified to the calibration parameter value in the target calibration parameter set.
In the embodiment of the invention, the calibration parameter set adopted by the chip with IQ balance calibration is used as the first reference calibration parameter set of the target chip with IQ balance calibration currently carried out. By utilizing the characteristic that the calibration parameter values of a plurality of chips manufactured by the same wafer and the same manufacturing process are similar, the target calibration parameter set of the target chip can be rapidly determined, the time spent by the target chip in determining the calibration parameter set is greatly shortened, and the time cost for manufacturing the chips is reduced.
Fig. 3 is a specific flowchart of an IQ balance calibration method of a radio frequency transmitting chip according to an embodiment of the present invention.
In a specific embodiment of step 301, a first reference calibration parameter set of a target chip currently performing IQ balance calibration is obtained, a local oscillator signal leakage value of the target chip is obtained by testing the first reference calibration parameter set, and the local oscillator signal leakage value is compared with a leakage value threshold to obtain a first comparison result. The first reference calibration parameter set may be any calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and the determination of the first reference calibration parameter set may refer to the related description in step 101, which is not repeated herein.
In a specific embodiment of step 302, it is determined whether the local oscillation leakage value in the first comparison result reaches a leakage value threshold. If the local oscillation signal leakage value does not reach the leakage value threshold, step 303 is executed; otherwise, step 304 is performed.
In a specific embodiment of step 303, the calibration parameter values in the first reference calibration parameter set are burned. Specifically, the first reference calibration parameter set is used as a target calibration parameter set of the target chip, and the calibration parameter values of the I path and the Q path in the target calibration parameter set are burnt into the storage firmware of the target chip.
In the specific embodiment of step 304, a second reference calibration parameter set of the target chip currently performing IQ balance calibration is obtained, a plurality of local oscillation signal leakage values of the target chip are obtained by testing the plurality of second reference calibration parameter sets, and the local oscillation signal leakage value with the smallest value is compared with a leakage value threshold to obtain a second comparison result. Specifically, a plurality of calibration parameter values of the I-way and a plurality of calibration parameter values of the Q-way may be selected from adjacent values of the calibration parameter values of the I-way and the calibration parameter values of the Q-way in the first reference calibration parameter set, respectively, so as to obtain a plurality of second reference calibration parameter sets.
In one non-limiting embodiment, compensation values may be obtained, and the compensation values may be used to add and subtract the calibration parameter values of the I-way and the calibration parameter values of the Q-way, respectively, of the first reference calibration parameter set to determine the preset value range. Specifically, the preset value range of the I path may be [ x-n, x+n ], the preset value range of the Q path may be [ y-n, y+n ], where x represents the calibration parameter value of the I path in the first reference calibration parameter set, y represents the calibration parameter value of the Q path in the first reference calibration parameter set, n represents the compensation value, and n, x, y are positive integers. For example, the calibration parameter value of the I-way in the first reference calibration parameter set is 6, the calibration parameter value of the Q-way in the first reference calibration parameter set is 7, and the compensation value is 2. The preset value range of the I path is [6-2,6+2], namely (4, 5,6,7, 8); the preset value range of the Q path is [7-2,7+2], namely (5, 6,7,8, 9). A plurality of second reference calibration parameter sets may be determined using a combination of the respective calibration parameter values in the preset value range for the I-way and the respective calibration parameter values for the preset value range for the Q-way.
It should be noted that, a compensation value may be set to determine the preset value ranges of the I-path and the Q-path at the same time, or different compensation values may be set to the I-path and the Q-path respectively to determine the preset value ranges of the I-path and the Q-path respectively, which is not limited in the present application.
In the embodiment of step 305, it is determined whether the local oscillation leakage value in the second comparison result reaches the leakage value threshold. If the local oscillator signal leakage value with the minimum value does not reach the leakage value threshold, executing step 306; otherwise, step 307 is performed.
In a specific embodiment of step 306, the calibration parameter values in the second reference calibration parameter set corresponding to the local oscillator signal leakage value with the smallest value are burned. Specifically, a second reference calibration parameter set corresponding to the local oscillator signal leakage value with the smallest value is used as a target calibration parameter set of the target chip, and the calibration parameter values of the I path and the Q path in the target calibration parameter set are burnt into the storage firmware of the target chip.
In a specific embodiment of step 307, a first test calibration parameter set and a second test calibration parameter set of the target chip currently performing IQ balance calibration are obtained, local oscillation signal leakage values of the target chip are obtained by testing with a plurality of second test calibration parameter sets, and local oscillation signal leakage values with the smallest values are compared with a leakage value threshold to obtain a third comparison result.
In a specific embodiment, one of the I-path and the Q-path is taken as a first path, and a plurality of candidate calibration parameter values of the first path are determined to obtain a plurality of first test calibration parameter sets. In the first test calibration parameter set, the calibration parameter value of the second path is a fixed value, and the second path is the other path of the I path and the Q path.
Further, a plurality of first test calibration parameter sets are used for testing to obtain local oscillation signal leakage values of the target chip, and first target calibration parameter values of a first path corresponding to the local oscillation signal leakage values with the minimum values are determined. And determining a plurality of candidate calibration parameter values of the second path to obtain a plurality of second test calibration parameter sets, wherein the calibration parameter values of the first path in the second test calibration parameter sets are first target calibration parameter values.
Further, a plurality of second test calibration parameter sets are used for testing to obtain local oscillation signal leakage values of the target chip, and the local oscillation signal leakage value with the smallest value is compared with a leakage value threshold to obtain a third comparison result.
In the specific embodiment of step 308, it is determined whether the local oscillation leakage value in the third comparison result reaches the leakage value threshold. If the local oscillator signal leakage value with the minimum value does not reach the leakage value threshold, step 309 is executed; otherwise, step 310 is performed.
In a specific embodiment of step 309, the first target calibration parameter value and the second target calibration parameter value are burned. Specifically, a target calibration parameter set of the target chip is determined, the target calibration parameter set includes a first target calibration parameter value and a second target calibration parameter value, and the calibration parameter values of the I-path and the calibration parameter values of the Q-path in the target calibration parameter set are burned into a storage firmware of the target chip.
In a specific embodiment, the register sizes on the I and Q paths are 5 bits, so that the I and Q paths each have 2 5 candidate calibration parameter values, the candidate calibration parameter values on the I path are in the range of [0,31], and the candidate calibration parameter values on the Q path are in the range of [0,31]. The plurality of candidate calibration parameters can be determined from the range of values of the calibration parameter values of the I-path, and the calibration parameter value of the Q-path is determined to be 0, so that 32 first test calibration parameter sets can be obtained. And testing by using a plurality of first test calibration parameter groups to obtain local oscillation signal leakage values of the target chip, and taking the candidate calibration parameter value of the I path corresponding to the local oscillation signal leakage value with the smallest value as a first target calibration parameter value of the I path, for example, taking 5 as the first target calibration parameter value of the I path.
Further, a plurality of candidate calibration parameter values are determined from the value range of the calibration parameter values of the Q paths, and the calibration parameter value of the I path is determined to be the first target calibration parameter value to be 5, so that 32 second test calibration parameter sets can be obtained. And testing by using a plurality of second test calibration parameter sets to obtain local oscillation signal leakage values of the target chip, and taking the candidate calibration parameter value of the Q path corresponding to the local oscillation signal leakage value with the smallest value as a second target calibration parameter value of the Q path, for example, taking 6 as the second target calibration parameter value of the Q path. And comparing the local oscillator signal leakage value with the minimum value with a leakage value threshold to obtain a third comparison result. If the third comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, determining a target calibration parameter set of the target chip, wherein the target calibration parameter set comprises a first target calibration parameter value 5 of an I path and a second target calibration parameter value 6 of a Q path. According to the method, the target calibration parameter set of the target chip can be determined by only testing the local oscillator signal leakage values of the 64 calibration parameter sets, and compared with the method for testing the local oscillator signal leakage values of all 1024 calibration parameter sets, the IQ balance calibration time can be greatly shortened.
Since a random value is used as the calibration parameter value of the second path in step 307, the first target calibration parameter value of the first path and the second target calibration parameter value of the second path determined later may not be the optimal calibration parameter values. Steps 310 and 311 may thus determine a more accurate set of target calibration parameters using the first target calibration parameter value and the second target calibration parameter value obtained by the preliminary screening.
In the specific embodiment of step 310, a third test calibration parameter set and a fourth test calibration parameter set of the target chip currently performing IQ balance calibration are obtained, local oscillation signal leakage values of the target chip are obtained by testing with a plurality of fourth test calibration parameter sets, and local oscillation signal leakage values with the smallest values are compared with a leakage value threshold to obtain a fourth comparison result.
In particular embodiments, a plurality of candidate calibration parameter values for the first path may be determined to obtain a plurality of third test calibration parameter sets. In the third test calibration parameter set, the calibration parameter value of the second path is the second target calibration parameter value.
Further, a plurality of third test calibration parameter sets are used for testing to obtain local oscillation signal leakage values of the target chip, and third target calibration parameter values of the first path corresponding to the local oscillation signal leakage values with the minimum values are determined. And determining a plurality of candidate calibration parameter values of the second path to obtain a plurality of fourth test calibration parameter sets, wherein the calibration parameter values of the first path in the fourth test calibration parameter sets are third target calibration parameter values.
Further, a plurality of fourth test calibration parameter sets are used for testing to obtain local oscillation signal leakage values of the target chip, the local oscillation signal leakage value with the smallest value is compared with a leakage value threshold to obtain a fourth comparison result, and a fourth target calibration parameter value of a second path corresponding to the local oscillation signal leakage value with the smallest value is determined.
In the specific embodiment of step 311, it is determined whether the local oscillation leakage value in the fourth comparison result reaches the leakage value threshold. If the local oscillator signal leakage value with the minimum value does not reach the leakage value threshold, executing step 312; otherwise, step 313 is performed.
In a specific embodiment of step 312, the third target calibration parameter value and the fourth target calibration parameter value are burned. Specifically, a target calibration parameter set of the target chip is determined, the target calibration parameter set includes a third target calibration parameter value and a fourth target calibration parameter value, and the calibration parameter values of the I-path and the calibration parameter values of the Q-path in the target calibration parameter set are burned into a storage firmware of the target chip.
In a specific embodiment of step 313, all candidate calibration parameter sets are traversed, and candidate calibration parameter values in the candidate calibration parameter sets corresponding to the local oscillator signal leakage value with the smallest value are burned. Specifically, all candidate calibration parameter sets are traversed, all candidate calibration parameter sets of the target chip are utilized to test to obtain a plurality of local oscillation signal leakage values of the target chip, the candidate calibration parameter set corresponding to the local oscillation signal leakage value with the smallest value is used as the target calibration parameter set, and the calibration parameter values of the I path and the calibration parameter values of the Q path in the target calibration parameter set are burnt into storage firmware of the target chip.
In the embodiment of the invention, the calibration steps are perfected under the condition that the first reference calibration parameter set does not meet the requirement, and the selection range of the calibration parameter values is gradually enlarged when the comparison result shows that the local oscillator signal leakage value does not meet the requirement. The target calibration parameter set of the target chip can be reasonably determined under the condition of less testing times.
As shown in fig. 4, the embodiment of the invention also discloses an IQ balance calibration device of the radio frequency transmitting chip. The IQ balance calibration apparatus 40 of the radio frequency transmitting chip comprises:
An obtaining module 401, configured to obtain a first reference calibration parameter set corresponding to a target chip, where the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set includes a calibration parameter value of an I path and a calibration parameter value of a Q path;
a test module 402, configured to test to obtain a local oscillator signal leakage value of the target chip by using the first reference calibration parameter set;
A comparing module 403, configured to compare the local oscillation signal leakage value with a leakage value threshold to obtain a first comparison result;
A determining module 404, configured to determine, using the first comparison result, a target calibration parameter set of the target chip, where the target calibration parameter set is used to balance an I-path signal and a Q-path signal of the target chip.
In a specific implementation, the IQ balance calibration apparatus of the radio frequency transmitting Chip may correspond to a Chip with a data processing function in a terminal device, for example, an SOC (System-On-a-Chip), a baseband Chip, etc.; or the terminal equipment comprises a chip module with a data processing function; or corresponds to a chip module having a chip with a data processing function or corresponds to a terminal device.
For more details of the working principle and the working manner of the IQ balance calibration apparatus 40 of the radio frequency transmitting chip, reference may be made to the related descriptions in fig. 1 to 3, which are not repeated here.
With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least some modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) part of modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented in hardware such as a circuit, where different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least some modules/units may be implemented in a software program, where the software program runs on a processor integrated within the terminal, and the remaining (if any) some modules/units may be implemented in hardware such as a circuit.
The embodiment of the invention also discloses a storage medium, which is a nonvolatile storage medium or a non-transient storage medium, and is a computer readable storage medium, and a computer program is stored on the storage medium, and the computer program can execute the steps of the methods shown in fig. 1 to 3 when running. The storage medium may include ROM, RAM, magnetic or optical disks, and the like. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory (non-transitory) or the like.
The embodiment of the invention also discloses a terminal device, which can comprise a memory and a processor, wherein the memory stores a computer program which can be run on the processor, and the processor can execute the steps of the methods shown in fig. 1 to 3 when running the computer program.
The term "plurality" as used in the embodiments of the present application means two or more.
The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present application limited, and no limitation on the embodiments of the present application should be construed.
It should be appreciated that in the embodiment of the present application, the processor may be a central processing unit (central processing unit, abbreviated as CPU), and the processor may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, abbreviated as DSP), application Specific Integrated Circuits (ASIC), off-the-shelf programmable gate arrays (field programmable GATE ARRAY, abbreviated as FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It should also be appreciated that the memory in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM EPROM), an electrically erasable programmable ROM (ELECTRICALLY EPROM, EEPROM), or a flash memory. The volatile memory may be a random access memory (random access memory, RAM for short) which acts as an external cache. By way of example, and not limitation, many forms of random access memory (random access memory, RAM) are available, such as static random access memory (STATIC RAM, SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM).
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more sets of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.
It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may be physically included separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk, or an optical disk, etc., which can store program codes.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. The IQ balance calibration method of the radio frequency transmitting chip is characterized by comprising the following steps of:
Acquiring a first reference calibration parameter set corresponding to a target chip, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path;
obtaining the local oscillator signal leakage value of the target chip by using the first reference calibration parameter set test;
Comparing the local oscillator signal leakage value with a leakage value threshold to obtain a first comparison result;
and determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set is used for balancing signals of an I path and signals of a Q path of the target chip.
2. The IQ balance calibration method of a radio frequency transmit chip according to claim 1 wherein said determining a set of target calibration parameters using said first comparison result comprises:
and when the first comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, taking the first reference calibration parameter set as the target calibration parameter set.
3. The IQ balance calibration method of a radio frequency transmit chip according to claim 1 wherein said determining a set of target calibration parameters using said first comparison result further comprises:
When the first comparison result indicates that the local oscillator signal leakage value reaches the leakage value threshold, selecting a plurality of calibration parameter values of an I path and a plurality of calibration parameter values of a Q path from adjacent values of the calibration parameter values of the I path and the calibration parameter values of the Q path in the first reference calibration parameter set respectively so as to obtain a plurality of second reference calibration parameter sets;
obtaining local oscillator signal leakage values of the target chip by testing the plurality of second reference calibration parameter sets;
comparing the local oscillator signal leakage value with the minimum value with a leakage value threshold to obtain a second comparison result;
And when the second comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, taking the second reference calibration parameter set corresponding to the local oscillator signal leakage value with the minimum value as the target calibration parameter set.
4. The IQ balance calibration method of the radio frequency transmit chip according to claim 3 wherein the obtaining a plurality of second reference calibration parameter sets comprises:
Obtaining a compensation value;
Respectively adding and subtracting the calibration parameter value of the I path and the calibration parameter value of the Q path in the first reference calibration parameter set by utilizing the compensation value to determine a preset value range;
And selecting a plurality of I-path calibration parameter values and a plurality of Q-path calibration parameter values within the preset value range to obtain a plurality of second reference calibration parameter sets.
5. The IQ balance calibration method of a radio frequency transmit chip according to claim 3 further comprising:
When the first comparison result or the second comparison result indicates that the local oscillator signal leakage value reaches the leakage value threshold, determining a plurality of candidate calibration parameter values of a first path to obtain a plurality of first test calibration parameter sets, wherein the calibration parameter values of a second path in the first test calibration parameter sets are fixed values, the first path is one path of I paths and Q paths, and the second path is the other path of the I paths and the Q paths; testing by using the plurality of first test calibration parameter sets to obtain local oscillator signal leakage values of the target chip, and determining first target calibration parameter values of a first path corresponding to the local oscillator signal leakage values with the minimum values; determining a plurality of candidate calibration parameter values of a second path to obtain a plurality of second test calibration parameter sets, wherein the calibration parameter values of a first path in the second test calibration parameter sets are the first target calibration parameter values;
Testing by using the plurality of second test calibration parameter sets to obtain local oscillator signal leakage values of the target chip;
comparing the local oscillator signal leakage value with the leakage value threshold with the minimum value to obtain a third comparison result, and determining a second target calibration parameter value of a second path corresponding to the local oscillator signal leakage value with the minimum value;
And when the third comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, determining a target calibration parameter set of the target chip, wherein the target calibration parameter set comprises the first target calibration parameter value and the second target calibration parameter value.
6. The IQ balance calibration method of a radio frequency transmit chip according to claim 5 further comprising:
when the third comparison result shows that the local oscillator signal leakage value reaches the leakage value threshold, determining a plurality of candidate calibration parameter values of a first path to obtain a plurality of third test calibration parameter sets, wherein the calibration parameter value of a second path in the third test calibration parameter sets is the second target calibration parameter value;
testing by using the plurality of third test calibration parameter sets to obtain local oscillator signal leakage values of the target chip, and determining a third target calibration parameter value of a first path corresponding to the local oscillator signal leakage value with the minimum value; determining a plurality of candidate calibration parameter values of a second path to obtain a plurality of fourth test calibration parameter sets, wherein the calibration parameter values of the first path in the fourth test calibration parameter sets are the third target calibration parameter values;
Testing by using the fourth test calibration parameter sets to obtain local oscillator signal leakage values of the target chip;
Comparing the local oscillator signal leakage value with the leakage value threshold with the minimum value to obtain a fourth comparison result, and determining a fourth target calibration parameter value of a second path corresponding to the local oscillator signal leakage value with the minimum value;
and when the fourth comparison result shows that the local oscillator signal leakage value does not reach the leakage value threshold, determining a target calibration parameter set of the target chip, wherein the target calibration parameter set comprises the third target calibration parameter value and the fourth target calibration parameter value.
7. The IQ balance calibration method for a radio frequency transmit chip according to claim 1 wherein the obtaining the first set of reference calibration parameters corresponding to the target chip comprises:
And acquiring a target calibration parameter set of the calibrated target chip, and taking the target calibration parameter set of the calibrated target chip as a first reference calibration parameter set corresponding to the target chip.
8. The IQ balance calibration method of a radio frequency transmit chip according to claim 1 further comprising:
and burning the target calibration parameter set to the firmware of the target chip.
9. An IQ balance calibration apparatus for a radio frequency transmit chip, comprising:
the acquisition module is used for acquiring a first reference calibration parameter set corresponding to a target chip, wherein the first reference calibration parameter set is a calibration parameter set adopted by a chip adopting the same manufacturing process as the target chip, and each calibration parameter set comprises a calibration parameter value of an I path and a calibration parameter value of a Q path;
the test module is used for obtaining the local oscillator signal leakage value of the target chip by using the first reference calibration parameter set;
the comparison module is used for comparing the local oscillator signal leakage value with a leakage value threshold to obtain a first comparison result;
and the determining module is used for determining a target calibration parameter set of the target chip by using the first comparison result, wherein the target calibration parameter set is used for balancing signals of an I path and signals of a Q path of the target chip.
10. A terminal device comprising a memory and a processor, said memory having stored thereon a computer program executable on said processor, characterized in that said processor, when executing said computer program, performs the steps of the IQ balance calibration method of a radio frequency transmit chip according to any of claims 1 to 8.
11. A computer readable storage medium having stored thereon a computer program, characterized in that the computer readable storage medium is a non-volatile storage medium or a non-transitory storage medium, which computer program when being executed by a processor performs the steps of the IQ balance calibration method of a radio frequency transmit chip according to any of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211336707.0A CN115714705B (en) | 2022-10-28 | 2022-10-28 | IQ balance calibration method and device for radio frequency transmitting chip and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211336707.0A CN115714705B (en) | 2022-10-28 | 2022-10-28 | IQ balance calibration method and device for radio frequency transmitting chip and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115714705A CN115714705A (en) | 2023-02-24 |
| CN115714705B true CN115714705B (en) | 2024-07-09 |
Family
ID=85231595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211336707.0A Active CN115714705B (en) | 2022-10-28 | 2022-10-28 | IQ balance calibration method and device for radio frequency transmitting chip and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115714705B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109150231A (en) * | 2018-10-24 | 2019-01-04 | 广东博威尔电子科技有限公司 | Local oscillator leakage correction device and method |
| CN111200467A (en) * | 2019-12-17 | 2020-05-26 | 翱捷科技(深圳)有限公司 | Calibration method and device for wireless parameters of chip and electronic equipment |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201027953A (en) * | 2009-01-09 | 2010-07-16 | Ralink Technology Corp | Method and circuit for calibrating analog circuit components |
| US9413294B2 (en) * | 2011-07-03 | 2016-08-09 | Dsp Group Ltd. | Apparatus and method for correcting IQ imbalance |
| CN204967811U (en) * | 2015-09-22 | 2016-01-13 | 广东博威尔电子科技有限公司 | Digital interface radio frequency transceiving machine and correcting unit is revealed to local oscillator of using thereof |
| CN109120265B (en) * | 2018-08-06 | 2021-09-14 | 张家港康得新光电材料有限公司 | Signal correction method, device, chip and storage medium |
| CN112557876A (en) * | 2020-12-10 | 2021-03-26 | 苏州英嘉通半导体有限公司 | Device for calibrating chip simulation parameters and test method thereof |
| US11843361B2 (en) * | 2021-01-15 | 2023-12-12 | International Business Machines Corporation | LO leakage suppression in frequency conversion circuits |
| CN114866107A (en) * | 2022-03-23 | 2022-08-05 | 北京中科晶上科技股份有限公司 | Transmitter local oscillator leakage precompensation calibration device and method of wireless communication system |
-
2022
- 2022-10-28 CN CN202211336707.0A patent/CN115714705B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109150231A (en) * | 2018-10-24 | 2019-01-04 | 广东博威尔电子科技有限公司 | Local oscillator leakage correction device and method |
| CN111200467A (en) * | 2019-12-17 | 2020-05-26 | 翱捷科技(深圳)有限公司 | Calibration method and device for wireless parameters of chip and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115714705A (en) | 2023-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110286345B (en) | Method, system and equipment for calibrating on-chip S parameters of vector network analyzer | |
| US10374838B2 (en) | Image distortion correction in a wireless terminal | |
| CN113395122B (en) | Production test circuit board, radio frequency parameter calibration system, method and computer equipment | |
| CN107786287B (en) | Flatness calibration method and system | |
| US10103825B2 (en) | Transceiver system supporting receiver self calibration and methods of performing the same | |
| US9736790B1 (en) | Transceiver system supporting transmitter self calibration and methods of performing the same | |
| WO2022116670A1 (en) | Sata chip signal test method and system, and related components | |
| CN108650034A (en) | A kind of gain calibration methods thereof and device of radio-frequency apparatus | |
| CN111257788B (en) | Dynamic test method, system, equipment and medium of power supply | |
| JP2022516977A (en) | Measurement method and equipment | |
| CN115714705B (en) | IQ balance calibration method and device for radio frequency transmitting chip and storage medium | |
| CN111880201B (en) | Beidou terminal testing system, testing method and testing device | |
| CN115809203B (en) | Dynamic nesting method and device for software test cases and application of dynamic nesting method and device | |
| US6898746B2 (en) | Method of and apparatus for testing a serial differential/mixed signal device | |
| CN117033251B (en) | Regression testing method and device for multi-version system of mobile electronic equipment | |
| KR20210145819A (en) | Compensation circuit and chip, method, device, storage medium, electronics | |
| CN113949393B (en) | Transmitter, calibration method and device thereof, and storage medium | |
| WO2022179439A1 (en) | Agc calibration preprocessing method and device, and storage medium and terminal | |
| CN114113974B (en) | Chip system level test method and device | |
| US11280871B2 (en) | Method of absolute phase calibration as well as calibration system | |
| CN112019317B (en) | Frequency calibration method and device, storage medium and electronic device | |
| CN112881992B (en) | Channel amplitude and phase consistency self-checking method and device and computer equipment | |
| JP2024086599A (en) | Radio frequency device calibration method | |
| CN112946551B (en) | Method and device for measuring path delay, electronic device and storage medium | |
| WO2023206751A1 (en) | Calibration control circuit, electronic device, and calibration control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |