CN115691088B - Control signal transmission unit, system and method - Google Patents
Control signal transmission unit, system and method Download PDFInfo
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Abstract
The invention discloses a control signal transmission unit, a control signal transmission system and a control signal transmission method, wherein the control signal transmission unit enables the high-level retention time of the write permission of an internal register of a subsystem and the low-level retention time of the system when a control signal is in a low-level entering a turn-off mode by setting the preset pulse number entering a control mode of the system, and ensures that the control signal needs to strictly meet the condition to enable the subsystem to correctly enter the control mode and perform correct control register setting and normal operation; the application is simple, the system resources are saved, and the system cost is reduced.
Description
Technical Field
The present invention relates to the field of signal transmission, and in particular, to a control signal transmission unit, system and method.
Background
For complex systems, various control signals and data are often required to be transmitted, and more common transmission modes include an IIC control protocol or an SPI control protocol, and other modes, but these modes need to occupy 2-3 interfaces of each system to transmit clock signals, control signals or data signals and chip select signals, and these transmission modes occupy too many interface resources, and the control modes are very complex, so that the communication cost is increased.
Disclosure of Invention
The invention aims to provide a system and a method for transmitting control signals between systems, which are simple, flexible, convenient and reliable, can greatly save resources and reduce communication cost.
In order to achieve the above object, the present invention provides a control signal transmission unit including: the device comprises a high-level detection and pulse counting module, a high-level delay detection module, a pulse counting module, a control register and a control register setting completion judging module;
the high level detection and pulse counting module is used for detecting and counting high level pulses of the control pins and comparing the high level pulses with the number of the pulses entering a control mode preset by the system;
the high-level delay detection module is used for detecting the high-level duration time of the control signal and comparing the high-level duration time with the write permission time of the enable control register set by the system;
the pulse counting module is used for counting the number of pulses sent after the high level time of the control signal exceeds the write permission time of the enable control register set by the system, and setting the number as the value of the control register;
the control register setting completion judging module is used for generating a high-level setting completion signal and shielding the counting function of the pulse counting module.
Optionally, the method further comprises: the low-level delay detection module is used for detecting the level change of a control signal of the control pin during the normal operation of the system.
The invention also provides a control signal transmission method, which adopts the control signal transmission unit, and comprises the following steps:
the subsystem detects and controls the high level pulse of the pin, count, and compare with the pulse number that presets; if the number of the detected high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the subsystem detects again;
the pin of an enabling control register of the subsystem entering the control mode is connected with a fixed high level, and the duration of the high level of a control signal is detected by the subsystem and compared with the preset time of the write permission of the control register in the enabling subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, repeating the steps; and after the setting is finished, a setting finishing signal generating a high level is connected to the control state latch pin, the subsystem control register value is locked, and the system enters a normal operation mode.
The invention also provides a control signal transmission system, which adopts the control signal transmission unit as described above, and comprises: the control pins of the N subsystems receive the same control signal, the enable control register pin of the 1 st subsystem is connected with high level, the setting completion signal output by the ith subsystem is connected with the enable control register pin of the next subsystem, and the setting completion signal of the Nth subsystem is connected with the control state latch pins of all the subsystems, wherein i is more than or equal to 1 and less than N.
Optionally, the control signals of the N subsystems are shared.
The invention also provides a control signal transmission method, which adopts the control signal transmission system as described above, and comprises the following steps:
the subsystem detects and controls the high level pulse of the pin, count, and compare with the pulse number that presets; if the number of the detected high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the subsystem detects again;
in the subsystem entering the control mode, the pin of the enabling control register of the 1 st subsystem is connected with a fixed high level, and the subsystem detects the duration of the high level of the control signal and compares the duration with the preset time of the write permission of the control register in the enabling subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, repeating the steps; setting completion signals which generate high level after the 1 st subsystem is set are connected to the input pins of the enable control register of the 2 nd subsystem, and meanwhile, the counting function of the pulse counting module of the 1 st subsystem is shielded;
the setting completion signal of the high level of the 1 st subsystem enables the control register of the 2 nd subsystem, and the 2 nd subsystem detects the duration of the high level of the control signal and compares the duration with the preset time for enabling the write permission of the control register in the subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, continuously detecting the duration of the high level of the control signal by the subsystem; generating a high-level setting completion signal after the setting of the 2 nd subsystem is completed, connecting the high-level setting completion signal to an input pin of an enable control register of the next subsystem, and shielding the counting function of a pulse counting module of the 2 nd subsystem; and so on, generating a high-level setting completion signal until the Nth subsystem is set;
the setting completion signal of the Nth subsystem output high level is input to the control state latch pins of all subsystems, all subsystem control register values are locked, and the system enters a normal operation mode.
Optionally, the method further comprises: and when the duration exceeds the preset time, the subsystem counts the number of subsequent high-level pulses, and the value of an internal control register of the subsystem is set according to the number of the subsequent high-level pulses.
Optionally, the method further comprises: after normal operation, the subsystem continuously detects the control signal level of the control pin, when the control signal level is low, the subsystem detects low-level duration, if the low-level duration is smaller than the preset turn-off time of the system, the normal operation mode is continued, and if the low-level duration reaches the preset turn-off time, the subsystem resets an internal control register and enters the turn-off mode.
Optionally, the method further comprises: after the subsystem enters the off mode, the subsystem continues to detect the control pin high pulse and continues to enter the control mode.
Compared with the prior art, the control signal of the invention controls a plurality of subsystems, the control pins of the subsystems are connected and receive the same control signal, the fixed high-level VDD signal enables the control register of the 1 st subsystem, the high-level setting completion signal output by the last subsystem enables the control register of the next subsystem, and the high-level setting completion signal of the last subsystem is connected back to the control state latch pins of all subsystems, the control register values of all subsystems are locked, and the system enters a normal running mode.
The method is characterized in that the method is limited by setting a strict judgment mechanism, the number of pulses entering a system control mode is preset, and the high-level retention time of write permission of an internal register of a subsystem is ensured, so that the subsystem can enter the control mode correctly and perform correct control register setting only by ensuring that a control signal strictly meets the conditions; the transmission of various complex control signals between the systems can be conveniently and reliably realized by only one control pin, the system can comprise at least one subsystem or a plurality of subsystems, the application is very simple and flexible, the system resources are saved, and the system cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a control signal transmission unit according to an embodiment of the present invention;
fig. 2 is a flowchart of a control signal transmission method according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a control signal transmission system according to an embodiment of the present invention;
FIG. 4 is a second flow chart of a control signal transmission method according to an embodiment of the invention;
fig. 5 is a logic flow diagram of a control signal transmission method according to an embodiment of the invention.
Detailed Description
A control signal transmission unit, system and method of the present invention will be described in more detail below with reference to the drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a control signal transmission unit, please refer to fig. 1, comprising: the device comprises a high-level detection and pulse counting module, a high-level delay detection module, a pulse counting module, a control register and a control register setting completion judging module;
specifically, the high level detection and pulse counting module is used for detecting and counting high level pulses of the control pin and comparing the high level pulses with the number of pulses entering a control mode preset by the system; in particular for limiting the conditions under which the subsystem enters the control mode.
The high-level delay detection module is used for detecting the high-level duration time of the control signal and comparing the high-level duration time with the write permission time of the enable control register set by the system; in particular for limiting the conditions for entering the control mode, preventing the subsystem from erroneously setting the internal control registers.
The pulse counting module is used for counting the number of pulses sent after the high level time of the control signal exceeds the write permission time of the enable control register set by the system, and setting the value of the control register.
The control register setting completion judging module is used for generating a high-level setting completion signal and shielding the counting function of the pulse counting module.
In other embodiments, the control signal transmission unit further includes: the low-level delay detection module is used for detecting the level change of a control signal of the control pin during the normal operation of the system; in particular for monitoring level changes during normal operation of the system.
In addition, the subsystem entering the normal operation mode performs data transmission with other modules.
The embodiment of the invention also provides a control signal transmission method, which only comprises a subsystem, please refer to fig. 2, and comprises the following steps:
the subsystem detects and controls the high level pulse of the pin, count, and compare with the pulse number that presets; if the number of the detected high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the subsystem detects again;
the pin of an enabling system control register of the subsystem entering the control mode is high level, the duration of the high level of the control signal is detected, and the duration is compared with the preset time of the write permission of the control register in the enabling subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, repeating the steps; and after the setting is finished, a setting finishing signal generating a high level is connected to the control state latch pin, the subsystem control register value is locked, and the system enters a normal operation mode.
The embodiment of the invention also provides a control signal transmission system, which comprises: the control pins of the N subsystems receive the same control signal, the enable control register pin of the 1 st subsystem is connected with a fixed high-level signal, the setting completion signal output by the ith subsystem is connected with the enable control register pin of the next subsystem, and the setting completion signal of the Nth subsystem is connected with the control state latch pins of all the subsystems, wherein i is more than or equal to 1 and less than N.
Referring to fig. 3, the control pins of the multiple subsystems are connected to each other and receive the same control signal, the fixed high VDD signal enables the control register of the 1 st subsystem, the high setting completion signal output from the last subsystem enables the control register of the next subsystem, and the high setting completion signal of the last subsystem is connected back to the control state latch pins of all the subsystems.
The embodiment of the invention also provides a control signal transmission method, referring to fig. 4-5, comprising the following steps:
s1, detecting high-level pulses of a control pin by a subsystem, counting and comparing the high-level pulses with the preset pulse number; if the number of the detected high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the subsystem detects again;
s2, in the subsystem entering the control mode, the pin of an enabling control register of the 1 st subsystem is connected with a fixed high level, the subsystem detects the duration of the high level of a control signal and compares the duration with the preset time of the write permission of the control register in the enabling subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, repeating the steps;
s3, after the setting of the 1 st subsystem is finished, a setting finishing signal of high level is generated and is connected to an input pin of an enabling control register of the 2 nd subsystem, and meanwhile, the counting function of a pulse counting module of the 1 st subsystem is shielded;
s4, enabling a control register of a 2 nd subsystem by a high-level setting completion signal of the 1 st subsystem, detecting the duration of the high level of the control signal by the 2 nd subsystem, and comparing the duration with the preset time for enabling the write permission of the control register in the subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, continuously detecting the duration of the high level of the control signal by the subsystem;
s5, generating a high-level setting completion signal after the setting of the 2 nd subsystem is completed, connecting the high-level setting completion signal to an input pin of an enable control register of the next subsystem, and shielding the counting function of a pulse counting module of the 2 nd subsystem;
s6, repeating the steps S4-S5 until the setting completion signal of the high level is generated after the setting of the Nth subsystem is completed;
s7, inputting a setting completion signal of the Nth subsystem for outputting a high level to control state latch pins of all subsystems, locking all subsystem control register values, and enabling the system to enter a normal operation mode.
In S1, specifically, if the set number of pulses entering the control mode is 16 high-level pulses, the control pin is required to transmit 16 high-level pulses, and the subsystem enters the control mode. If the interference or noise causes the control pin to generate sporadic high-level burr signals, the pulse number of the burr signals is difficult to meet the requirement of 16 pulse numbers, so that the high-level burr pulses generated by the interference or noise are difficult to enable the subsystem to enter the control mode by mistake, and in addition, if the pulse number is less than 16 error pulse signals, the subsystem cannot enter the control mode, so that the high-level burr signals or the mistaken high-level pulse signals are avoided to a great extent, and the subsystem is prevented from entering the control mode by mistake.
Specifically, in S2, by comparing the duration of the high level of the control signal with the preset time for enabling the write permission of the control register in the subsystem, it is possible to limit the condition for entering the set mode, and prevent the disturbance signal or the erroneous pulse from causing the subsystem to set the internal control register erroneously.
In S2, the setting the subsystem internal control register further includes step S201: after the high level time of the control signal exceeds the preset time for enabling the write permission of the control register in the subsystem, the pulse counting module of the 1 st subsystem continues to count the high level pulse number of the subsequent control signal, and the value of the control register in the 1 st subsystem is set according to the pulse number.
Specifically, in S4, the setting the internal control register of the subsystem further includes step S401: after the high level time of the control signal exceeds the preset time, the pulse counting module of the 2 nd subsystem continues to count the high level pulse number of the subsequent control signal, and the value of the control register inside the pulse counting module is set according to the pulse number.
In addition, step S8 is further included, the subsystem after normal operation continuously detects the control signal level of the control pin, when the control signal level becomes low, the subsystem detects the duration of low level, if the duration of low level is less than the preset turn-off time of the system, the subsystem considers the interference signal, continues the normal operation mode, if the duration of low level reaches the preset turn-off time, the subsystem resets all control registers in the interior, each subsystem enters the turn-off mode, and the system entering the turn-off mode returns to S1.
In summary, in the technical scheme of the present invention, a control signal controls a plurality of subsystems, control pins of the plurality of subsystems are connected and receive the same control signal, a fixed high level VDD signal enables a control register of a 1 st subsystem, a high level setting completion signal output by a previous subsystem enables a control register of a next subsystem, and a high level setting completion signal of a last subsystem is connected back to control status latch pins of all subsystems, values of control registers of all subsystems are locked, and the system enters a normal operation mode.
The method is characterized in that the method comprises the steps of limiting by setting a strict judging mechanism, presetting the number of pulses entering a system control mode, enabling high-level retention time of write permission of an internal register of a subsystem and low-level retention time of the system entering a turn-off mode when a control signal becomes low, ensuring that the control signal needs to strictly meet the condition to enable the subsystem to correctly enter the control mode and perform correct control register setting and normal operation; the transmission of various complex control signals between the systems can be conveniently and reliably realized by only one control pin, the system can comprise at least one subsystem or a plurality of subsystems, the application is very simple and flexible, the system resources are saved, and the system cost is reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. A control signal transmission unit, characterized by comprising: the device comprises a high-level detection and pulse counting module, a high-level delay detection module, a pulse counting module, a control register and a control register setting completion judging module;
the high level detection and pulse counting module is used for detecting and counting high level pulses of the control pins and comparing the high level pulses with the number of the pulses entering a control mode preset by the system;
the high-level delay detection module is used for detecting the high-level duration time of the control signal and comparing the high-level duration time with the write permission time of the enable control register set by the system;
the pulse counting module is used for counting the number of pulses sent after the high level time of the control signal exceeds the write permission time of the enable control register set by the system, and setting the number as the value of the control register;
the control register setting completion judging module is used for generating a high-level setting completion signal and shielding the counting function of the pulse counting module;
the control signal transmission units are configured to receive the same control signal when N control signal transmission units are matched for use, the enable control register pin of the 1 st control signal transmission unit is connected with high level, the setting completion signal output by the ith control signal transmission unit is connected with the enable control register pin of the next control signal transmission unit, and the setting completion signal of the Nth control signal transmission unit is connected with the control state latch pins of all control signal transmission units, wherein i is more than or equal to 1 and less than N.
2. The control signal transmission unit according to claim 1, further comprising: the low-level delay detection module is used for detecting the level change of a control signal of the control pin during the normal operation of the system.
3. A control signal transmission method, characterized by employing the control signal transmission unit according to claim 1 or 2, comprising the steps of:
the subsystem detects and controls the high level pulse of the pin, count, and compare with the pulse number that presets; if the number of the detected high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the subsystem detects again;
the control register pin of the enabling system of the subsystem entering the control mode is in a high level, and the subsystem detects the duration of the high level of the control signal and compares the duration with the preset time of the write permission of the control register in the enabling subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, repeating the steps; and after the setting is finished, a setting finishing signal generating a high level is connected to the control state latch pin, the subsystem control register value is locked, and the system enters a normal operation mode.
4. A control signal transmission system employing the control signal transmission unit according to claim 1 or 2, comprising: the control pins of the N subsystems receive the same control signal, the enable control register pin of the 1 st subsystem is connected with high level, the setting completion signal output by the ith subsystem is connected with the enable control register pin of the next subsystem, and the setting completion signal of the Nth subsystem is connected with the control state latch pins of all the subsystems, wherein i is more than or equal to 1 and less than N.
5. The control signal transmission system of claim 4, wherein the control signals of the N subsystems are one shared.
6. A control signal transmission method, characterized by employing the control signal transmission system according to claim 4 or 5, comprising the steps of:
the subsystem detects and controls the high level pulse of the pin, count, and compare with the pulse number that presets; if the number of the detected high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the subsystem detects again;
in the subsystem entering the control mode, the pin of the enabling control register of the 1 st subsystem is connected with a fixed high level, and the subsystem detects the duration of the high level of the control signal and compares the duration with the preset time of the write permission of the control register in the enabling subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, repeating the steps; setting completion signals which generate high level after the 1 st subsystem is set are connected to the input pins of the enable control register of the 2 nd subsystem, and meanwhile, the counting function of the pulse counting module of the 1 st subsystem is shielded;
the setting completion signal of the high level of the 1 st subsystem enables the control register of the 2 nd subsystem, and the 2 nd subsystem detects the duration of the high level of the control signal and compares the duration with the preset time for enabling the write permission of the control register in the subsystem; setting an internal control register of the subsystem when the duration exceeds the preset time, otherwise, continuously detecting the duration of the high level of the control signal by the subsystem; generating a high-level setting completion signal after the setting of the 2 nd subsystem is completed, connecting the high-level setting completion signal to an input pin of an enable control register of the next subsystem, and shielding the counting function of a pulse counting module of the 2 nd subsystem; and so on, generating a high-level setting completion signal until the Nth subsystem is set;
the setting completion signal of the Nth subsystem output high level is input to the control state latch pins of all subsystems, all subsystem control register values are locked, and the system enters a normal operation mode.
7. The control signal transmission method of claim 6, further comprising: and when the duration exceeds the preset time, the subsystem counts the number of subsequent high-level pulses, and the value of an internal control register of the subsystem is set according to the number of the subsequent high-level pulses.
8. The control signal transmission method of claim 6, further comprising: after normal operation, the subsystem continuously detects the control signal level of the control pin, when the control signal level is low, the subsystem detects low-level duration, if the low-level duration is smaller than the preset turn-off time of the system, the normal operation mode is continued, and if the low-level duration reaches the preset turn-off time, the subsystem resets an internal control register and enters the turn-off mode.
9. The control signal transmission method of claim 8, further comprising: after the subsystem enters the off mode, the subsystem continues to detect the control pin high pulse and continues to enter the control mode.
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