CN115668092A

CN115668092A - Transient boost circuit, chip system and equipment for LDO (low dropout regulator)

Info

Publication number: CN115668092A
Application number: CN202080101677.8A
Authority: CN
Inventors: 石玉楠; 熊付荣; 屈熹
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-08-26
Filing date: 2020-08-26
Publication date: 2023-01-31
Also published as: WO2022041011A1; EP4194991A4; EP4194991A1

Abstract

A transient boost circuit, a chip system and a device for LDO are used for increasing the transient state of the LDO and reducing the chip area occupied by a capacitor. The circuit includes: the LDO is used for outputting a first voltage; at least one detection circuit (2) coupled with the LDO, each detection circuit (2) of the at least one detection circuit (2) comprising a first capacitance, an amplifier (21), and a second capacitance; wherein the first capacitor is used for generating a coupling voltage according to the change of the first voltage and coupling the coupling voltage to the amplifier (21); the amplifier (21) is used for amplifying the coupling voltage to obtain a second voltage; the second capacitor is used for coupling the second voltage to the LDO, and the second voltage is used for regulating the first voltage to maintain the first voltage to be constant.

Description

Transient boost circuit, chip system and equipment for LDO (low dropout regulator)

Technical Field

The application relates to the technical field of electronics, especially, relate to a be used for LDO transient state to promote circuit, chip system and equipment.

Background

With the rapid development of internet of things (IOT) systems, IOT chips such as wearable chips and implantable chips are applied more and more. In an IOT system, highly sensitive subsystems such as Radio Frequency (RF) transceivers, digital-to-analog converters, high-speed digital circuits, and phase-locked loops (PLLs) have high transient demands on the power supply. Therefore, these subsystems are usually powered by some low dropout regulators (LDOs) with high transient performance.

In the prior art, these subsystems are usually powered by LDOs with large on-chip capacitors or LDOs with off-chip capacitors (the capacitance value of the off-chip capacitor is generally in the uF class), and the on-chip capacitors or the off-chip capacitors can reduce the voltage ripple caused by load transient, thereby ensuring the transient response of the LDO. However, if an LDO with an on-chip capacitor is used, the on-chip capacitor occupies a large chip area; if an LDO with an off-chip capacitor is used, the off-chip capacitor occupies additional PCB area.

Disclosure of Invention

The application provides a transient boost circuit, chip system and equipment for LDO for when improving the transient state of LDO, reduce the chip area that the electric capacity occupy.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, a transient boost circuit for a low dropout linear regulator (LDO) is provided, the transient boost circuit comprising: the LDO is used for outputting a first voltage, the first voltage can be used for supplying power to various subsystems or systems, and the first voltage can also be referred to as the output voltage of the LDO; at least one detection circuit coupled with the LDO, each detection circuit of the at least one detection circuit comprising a first capacitor, an amplifier, and a second capacitor; the first capacitor is used for generating a coupling voltage according to the change of the first voltage and coupling the coupling voltage to the amplifier, and the first capacitor couples the first voltage into the amplifier in an alternating current coupling (AC coupling) mode; an amplifier for amplifying the coupled voltage to obtain a second voltage, for example, the amplifier may be a non-inverting amplifier or an inverting amplifier; and the second capacitor is used for coupling the second voltage to the LDO, namely the second capacitor couples the second voltage into the LDO by means of alternating current coupling to form negative feedback, and the second voltage is used for regulating the first voltage to maintain the first voltage to be constant.

In the technical scheme, the first voltage output by the LDO is coupled to the amplifier through the first capacitor and is amplified by the amplifier, so that the coupling of the first voltage can be realized by using the smaller first capacitor while the transient state of the LDO is improved, and the chip area occupied by the first capacitor is reduced; meanwhile, the second voltage output by the amplifier is coupled to the LDO through the second capacitor, so that the second voltage does not directly act on the inherent loop of the LDO, the direct current characteristic of the LDO cannot be damaged, and the stability of the LDO loop is ensured. In addition, the amplifier is coupled with the LDO through the first capacitor and the second capacitor, so that the bias of the amplifier and the direct-current component of the first voltage can be separated, the bias difficulty and the complexity of the amplifier are effectively reduced, namely the requirements of disorder, matching and the like are not needed to be considered in the design of the amplifier, the area of a chip is further reduced, and low power consumption and high energy efficiency are realized.

In one possible implementation form of the first aspect, the amplifier comprises: a first transistor, a second transistor, a third transistor, and a first resistor; one electrode of the first transistor, one electrode of the second transistor and one end of the first resistor are coupled to be used as an output end of the amplifier, a control end of the first transistor, a control end of the second transistor and the other end of the first resistor are coupled to be used as an input end of the amplifier, the other electrode of the second transistor is coupled to one electrode of the third transistor, one of the other electrode of the first transistor and the other electrode of the third transistor is coupled to a power supply end, the other electrode of the first transistor and the other electrode of the third transistor is coupled to a ground end, and the control end of the third transistor is coupled to a bias voltage end. Optionally, the first transistor is an NMOS transistor, the second transistor and the third transistor are both PMOS transistors, one of the transistors is a drain, the other of the transistors is a source, and the control terminal is a gate. In the possible implementation manner, the amplifier is an inverter-based amplifier, transconductance of the amplifier is the sum of transconductance of the first transistor and transconductance of the second transistor, and transconductance of the amplifier is twice that of a common amplifier under the condition of the same power consumption, so that energy efficiency is effectively improved; the third transistor is used for providing bias current for the amplifier, and the power consumption of the amplifier is prevented from changing along with the change of the voltage of the power supply and the process corner. In addition, the amplifier is coupled with the LDO through the first capacitor and the second capacitor, so that the direct-current working point of the amplifier can be biased independently only by using the first resistor, and the matching requirement of the amplifier is effectively reduced.

In one possible implementation manner of the first aspect, the at least one detection circuit includes a first detection circuit, and the first detection circuit further includes: a compensation circuit coupled between the second capacitor and the LDO; the compensation circuit is used for adjusting the first voltage according to the second voltage so as to maintain the first voltage constant. In the possible implementation manner, the compensation circuit can quickly and effectively compensate the first voltage output by the LDO based on the second voltage, so that the transient performance of the LDO is improved.

In one possible implementation manner of the first aspect, the compensation circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, and a third resistor; one electrode of the fourth transistor, one end of the third resistor and one electrode of the sixth transistor are coupled to the first node, the other electrode of the fourth transistor, the control end of the fifth transistor and one end of the second resistor are coupled to form an input end of the compensation circuit, one electrode of the fifth transistor and the other end of the second resistor are coupled to the second node, the other electrode of the fifth transistor, the control end of the sixth transistor and the other end of the third resistor are coupled, and the other electrode of the sixth transistor is used as an output end of the compensation circuit; one of the first node and the second node is coupled to a power supply terminal and the other is coupled to a ground terminal. Optionally, the fifth transistor is an NMOS transistor, and the fourth transistor and the sixth transistor are both PMOS transistors; or the fifth transistor is a PMOS tube, and the fourth transistor and the sixth transistor are NMOS tubes; the electrode is a drain electrode, the other electrode is a source electrode, and the control end is a grid electrode. In the possible implementation manner, the provided compensation circuit is simple and effective, so that the transient performance of the LDO can be improved, and the area of a chip can be further reduced.

In a possible implementation form of the first aspect, the LDO has an output, and the output of the compensation circuit is coupled to the output of the LDO. In the above possible implementation manner, the compensation circuit is fed back to the output end of the LDO to compensate the first voltage output by the LDO, so that the transient performance of the LDO is improved.

In one possible implementation manner of the first aspect, the compensation circuit includes: a fourth transistor, a fifth transistor, and a second resistor; one pole of the fourth transistor is coupled to the first node, the other pole of the fourth transistor, the control end of the fifth transistor and one end of the second resistor are coupled to serve as an input end of the compensation circuit, one pole of the fifth transistor and the other end of the second resistor are coupled to the second node, and the other pole of the fifth transistor serves as an output end of the compensation circuit; one of the first node and the second node is coupled to a power supply terminal and the other is coupled to a ground terminal. Optionally, the fourth transistor is a PMOS transistor, the fifth transistor is an NMOS transistor, the first electrode is a drain electrode, the other electrode is a source electrode, and the control terminal is a gate electrode. In the possible implementation manner, the provided compensation circuit is simple and effective, so that the transient performance of the LDO can be improved, and the area of a chip can be further reduced.

In one possible implementation manner of the first aspect, the LDO includes an operational amplifier, a regulating transistor, and a sampling circuit, an output terminal of the operational amplifier is coupled to a control terminal of the regulating transistor, one terminal of the regulating transistor is coupled to a power supply terminal, the other terminal of the regulating transistor is coupled to an input terminal of the sampling circuit as an output terminal of the LDO, an output terminal of the sampling circuit is coupled to a positive-phase input terminal of the operational amplifier, and a negative-phase input terminal of the operational amplifier is configured to receive a reference voltage; wherein the output terminal of the compensation circuit is coupled with the control terminal of the voltage regulating transistor. In the possible implementation manner, the compensation circuit is fed back to the control end of the voltage regulating transistor to realize compensation of the first voltage output by the LDO, so that the transient performance of the LDO is improved.

In one possible implementation manner of the first aspect, the LDO includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a fourth resistor; one electrode of the seventh transistor and one electrode of the eighth transistor are both coupled with a power supply terminal, the other electrode of the seventh transistor is coupled with one electrode of the ninth transistor to serve as an output terminal of the LDO, the other electrode of the eighth transistor, one electrode of the tenth transistor and a control terminal of the seventh transistor are coupled, the other electrode of the ninth transistor, the other electrode of the tenth transistor and one electrode of the eleventh transistor are coupled, the other electrode of the eleventh transistor is coupled with a ground terminal, the control terminal of the eleventh transistor is coupled with one end of the fourth resistor, and the other end of the fourth resistor is connected with a bias voltage terminal. Optionally, the seventh transistor, the eighth transistor, and the ninth transistor are all PMOS transistors, the tenth transistor and the eleventh transistor are all NMOS transistors, the first electrode of the seventh transistor to the ninth transistor is a source electrode, the other electrode of the seventh transistor to the ninth transistor is a drain electrode, the first electrode of the tenth transistor and the eleventh transistor is a drain electrode, the other electrode of the tenth transistor and the eleventh transistor is a source electrode, and the control terminal is a gate electrode. In the above possible implementation, a FVF LDO is provided, so that a chip area occupied by a capacitor can be reduced while a transient of the LDO is improved by at least one detection circuit coupled to the FVF LDO.

In a possible implementation manner of the first aspect, the at least one detection circuit further includes a second detection circuit, and a second capacitor in the second detection circuit is coupled between the output terminal of the amplifier and the control terminal of the eighth transistor. In the above possible implementation manner, the detection circuit is fed back to the control end of the eighth transistor to compensate the first voltage output by the LDO, so that the transient performance of the LDO is improved.

In a possible implementation manner of the first aspect, the at least one detection circuit further includes a third detection circuit, and a second capacitor in the third detection circuit is coupled between the output terminal of the amplifier and the control terminal of the tenth transistor. In the above possible implementation manner, the detection circuit is fed back to the control terminal of the tenth transistor to compensate the first voltage output by the LDO, so that the transient performance of the LDO is improved.

In one possible implementation manner of the first aspect, the at least one detection circuit further includes a fourth detection circuit, and a second capacitor in the fourth detection circuit is coupled between the output terminal of the amplifier and the control terminal of the eleventh transistor. In the above possible implementation manner, the detection circuit is fed back to the control end of the eleventh transistor to compensate the first voltage output by the LDO, so that the transient performance of the LDO is improved.

In a second aspect, a chip system is provided, where the chip system includes a load circuit and a transient boost circuit for a low dropout regulator LDO as provided in the first aspect or any one of the possible implementations of the first aspect; wherein, this transient boost circuit includes LDO and at least one detection circuitry with this LDO coupling, and this LDO is used for supplying power for this load circuit, and this at least one detection circuitry is used for improving the transient state of this LDO.

In a third aspect, there is provided a device comprising a load circuit and a circuit board, the circuit board comprising a transient boost circuit for a low dropout linear regulator LDO as provided in the first aspect or any one of the possible implementations of the first aspect; wherein, this transient boost circuit includes LDO and with this LDO coupled at least one detection circuitry, this LDO is used for supplying power for this load circuit, this at least one detection circuitry is used for improving this LDO's transient state.

It can be understood that any one of the chip systems and the devices provided above includes the transient boost circuit for LDO, and therefore, the advantageous effects achieved by the transient boost circuit for LDO can refer to the advantageous effects provided above, and are not described herein again.

Drawings

Fig. 1 is a schematic structural diagram of an LDO according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a transient boost circuit for an LDO according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an amplifier according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another transient boost circuit for an LDO according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a transient boost circuit for an LDO according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an operational amplifier according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of an FVF LDO according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another transient boost circuit for an LDO according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a transient boost circuit for an LDO according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of another transient boost circuit for an LDO according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of another transient boost circuit for an LDO according to an embodiment of the present application.

Detailed Description

The making and using of the various embodiments are discussed in detail below. It should be appreciated that many of the applicable inventive concepts provided herein may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the description and the technology, and do not limit the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Circuits or other components may be described or referred to as "performing" one or more tasks. In this case, "for" is used to connote structure by indicating that the circuit/component includes structure (e.g., circuitry) that performs one or more tasks during operation. Thus, a given circuit/component may be said to be performing that task even when the circuit/component is not currently operational (e.g., not open). Circuits/components used with the term "for" include hardware, such as circuits that perform operations, and the like.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and order.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In addition, the transistor according to the embodiment of the present application may be a Metal Oxide Semiconductor (MOS) field effect transistor (which may be simply referred to as a MOS transistor). The control terminal of the transistor in the embodiment of the present application may refer to a gate of the transistor; in one possible embodiment, one pole of the transistor may be referred to as a source, and the other pole may be referred to as a drain; in another possible embodiment, one pole of the transistor may be referred to as a drain and the other pole may be referred to as a source.

The technical scheme of the application can be applied to various subsystems or systems powered by low dropout regulators (LDOs). For example, the technical solution of the present application may be applied to a Radio Frequency (RF) transceiver, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a high-speed digital circuit (e.g., soC), a phase-locked loop (PLL), and the like, which are powered by an LDO.

Fig. 1 is a circuit schematic diagram of a general LDO provided in an embodiment of the present application, where the LDO may include: operational amplifier A0, regulating transistor M0, sampling circuit and load capacitance C0, the sampling circuit can include resistance Ra and resistance Rb. Taking the regulator transistor M0 as a PMOS transistor, for example, the output terminal of the operational amplifier A0 is coupled to the control terminal of the regulator transistor M0 (i.e., the gate of the PMOS), one terminal of the regulator transistor M0 (i.e., the source of the PMOS) is coupled to the voltage input terminal (VDD), the other terminal of the regulator transistor M0 (i.e., the drain of the PMOS) is coupled to the input terminal of the sampling circuit as the output terminal of the LDO, the output terminal of the sampling circuit is coupled to the positive input terminal of the operational amplifier A0, and the negative input terminal of the operational amplifier A0 is used for receiving the reference voltage V _REF One end of the load capacitor C0 is coupled to the output end of the LDO, and the other end is coupled to a Ground (GND).

When the LDO works, the sampling circuit outputs a voltage V through a resistor Ra and a resistor Rb _OUT Sampling and feeding back the acquired voltage to a positive phase input end of the operational amplifier; the collected voltage and reference voltage V received by negative phase input end of operational amplifier _REF And comparing and amplifying, feeding back the amplified voltage to an input end through a grid electrode of the voltage regulating transistor M0, and performing dynamic voltage stabilization output through the conduction voltage drop of the voltage regulating transistor M0.

When the LDO is powered on or the rear-stage load is suddenly changed, the output voltage V of the LDO is increased _OUT Overshoot or undershoot may occur, resulting in poor transient performance of the LDO. The overshoot may mean that the peak or the valley of the actual output voltage is larger than the set output voltage rangeThe overshoot may mean that the peak or the valley of the actual output voltage is smaller than the set output voltage range. Currently, to ensure a good transient response of the LDO, an LDO with a large on-chip capacitor or an LDO with an off-chip capacitor is generally used. However, if an LDO with an on-chip capacitor is used, the on-chip capacitor occupies a large chip area; if an LDO with an off-chip capacitor is used, the off-chip capacitor occupies additional PCB area. Based on this, the present application provides a transient boost circuit for an LDO, which is based on the principle that transient performance of the LDO is boosted by at least one detection circuit coupled with the LDO, and the at least one detection circuit can feed back to any node (e.g., an output node or an internal node of the LDO, etc.) in the LDO, and only negative feedback needs to be formed. The circuit can be used for improving the transient performance of the LDO, and simultaneously reducing the occupied area of the capacitor in the LDO, thereby reducing the area of a chip where the LDO is located.

Fig. 2 is a schematic structural diagram of a transient boost circuit for an LDO according to an embodiment of the present application, and referring to fig. 2, the transient boost circuit includes: LDO1, and at least one detection circuit 2 coupled with LDO1, at least one detection circuit 2 may include one or more detection circuits.

The LDO1 is configured to output a first voltage V1, where the first voltage V1 may be a voltage for supplying power to various subsystems or systems, and the first voltage V1 may also be referred to as an output voltage of the LDO 1. For example, the LDO1 is the LDO shown in fig. 1, and the first voltage V1 is the output voltage V shown in fig. 1 _OUT 。

In addition, each of the at least one detection circuit 2 includes: a first capacitor C1, an amplifier 21 and a second capacitor C2. The first capacitor C1 is configured to generate a coupling voltage according to a change of the first voltage V1 and couple the coupling voltage to the inverting amplifier 21, that is, the first capacitor C1 couples the first voltage V1 into the amplifier 21 by means of alternating current coupling (AC coupling), and a direct current component in the first voltage V1 can be filtered by the first capacitor. The amplifier 21 is configured to amplify the coupling voltage to obtain a second voltage V2, i.e. the second voltage V2 is the amplified voltage of the coupling voltage, for example, the amplifier 21 may be a positive-phase amplifier or an inverting amplifier, and is configured to amplify the coupling voltage to obtain the second voltage V2. The second capacitor C2 is used for coupling the second voltage V2 to the LDO1, that is, the second capacitor C2 couples the second voltage V2 to the LDO1 by means of ac coupling, and the second voltage V2 is used for regulating the first voltage V1 to maintain the first voltage V1 constant.

It is understood that the second capacitor C2 for coupling the second voltage V2 to the LDO1 may include: the second capacitor C2 directly couples the second voltage V2 to the LDO1 to maintain the first voltage V1 constant by internally regulating the first voltage V1 by the LDO 1; alternatively, the second capacitor C2 indirectly couples the second voltage V2 to the LDO1, for example, the second capacitor C2 couples the second voltage V2 to the LDO1 through an intermediate circuit, which may be used to regulate the first voltage V1 to maintain the first voltage V1 constant, for example, the intermediate circuit is the compensation circuit 22 in the following. In addition, maintaining the first voltage V1 constant can be understood as: the first voltage V1 is maintained to be equal to the predetermined voltage value, or the first voltage V1 is maintained to fluctuate within a small range around the predetermined voltage value, for example, the predetermined voltage value is 5V, and if the first voltage V1 fluctuates within a range of [4.9v,5.1v ], the first voltage V1 is considered to be constant.

Optionally, the amplifier 21 may adopt an integrated amplifier module, for example, the amplifier 21 may adopt an Operational Transconductance Amplifier (OTA) module; alternatively, the amplifier 21 may be an amplifier built with an electronic component. Illustratively, as shown in fig. 3, the amplifier 21 may include: a first transistor M1, a second transistor M2, a third transistor M3, and a first resistor R1. One pole of the first transistor M1, one pole of the second transistor M2, and one end of the first resistor R1 are coupled to serve as an output terminal of the amplifier 21, a control terminal of the first transistor M1, a control terminal of the second transistor M2, and the other end of the first resistor R1 are coupled to serve as an input terminal of the amplifier 21, the other pole of the second transistor M2 is coupled to one pole of the third transistor M3, one of the other pole of the first transistor M1 and the other pole of the third transistor M3 is coupled to a power supply terminal, and the other is coupled to a ground terminal, and the control terminal of the third transistor M3 is coupled to the bias voltage terminal VBP.

The bias voltage terminal VBP is used to provide a bias voltage for the third transistor M3, and the third transistor M3 serves as a current source to provide a bias current for the amplifier 21. The first transistor M1 and the second transistor M2 form a common source amplifier (common source amplifier), and the first resistor R1 provides a static dc bias voltage through direct coupling, so that both the first transistor M1 and the second transistor M2 are in a saturation region or a sub-threshold region. Specifically, after the first voltage V1 is coupled to the input terminal of the amplifier 21 through the first capacitor C1, the first voltage V1 is inversely amplified by the first transistor M1 and the second transistor M2, and the second voltage V2 is output from the output terminal of the amplifier 21.

It should be noted that, in fig. 3, the first transistor M1 is taken as an NMOS transistor, the second transistor M2 and the third transistor M3 are both taken as PMOS transistors, the one electrode is a drain electrode, the other electrode is a source electrode, and the control terminal is taken as a gate electrode for illustration; in practical applications, the first transistor M1, the second transistor M2, and the third transistor M3 may also be replaced by other transistors having similar functions, and the above-mentioned fig. 3 does not limit the embodiments of the present application.

The amplifier 21 is an inverter-based amplifier, the transconductance of the amplifier 21 is the sum of the transconductance of the first transistor M1 and the transconductance of the second transistor M2, and the transconductance is twice that of a common amplifier under the condition of the same power consumption. The third transistor M3 is used to provide a bias current to the amplifier 21, and to prevent the power consumption of the amplifier 21 from varying with the voltage at the power supply and the process corner. The amplifier 21 is coupled with the LDO1 through the first capacitor C1 and the second capacitor C2, so that the dc operating point of the amplifier 21 can be biased solely by using the first resistor R1, thereby effectively reducing the matching requirement of the amplifier 21.

In the embodiment of the application, the first voltage V1 output by the LDO1 is coupled to the amplifier 21 through the first capacitor C1, and the amplifier 21 amplifies the first voltage V1, so that the transient state of the LDO is improved, and meanwhile, the coupling of the first voltage V1 can be realized by using the smaller first capacitor C1, and the chip area occupied by the first capacitor C1 is reduced; meanwhile, a second voltage V2 output by the amplifier 21 is coupled to the LDO1 through a second capacitor C2, so that the second voltage V2 does not directly act on an inherent loop of the LDO1, thereby not damaging a direct current characteristic of the LDO1 and ensuring stability of the loop of the LDO 1. In addition, the amplifier 21 is coupled to the LDO1 through the first capacitor C1 and the second capacitor C2, so that the bias of the amplifier 21 and the dc component of the first voltage V1 can be separated, and the difficulty and complexity of the bias (bias) of the amplifier 21 are effectively reduced, that is, the design of the amplifier 21 does not need to consider the requirements of offset (offset), matching and the like, thereby further reducing the chip area and achieving low power consumption and high energy efficiency.

Further, the detection circuit can be divided into two types according to whether the second capacitor C2 directly couples the second voltage V2 into the LDO 1: the first is a detection circuit comprising a compensation circuit, i.e. the second capacitor C2 indirectly couples the second voltage V2 into the LDO 1; the second is a detection circuit that does not include a compensation circuit, i.e. the second capacitor C2 directly couples the second voltage V2 into the LDO 1. The at least one detection circuit 2 may comprise at least one of the two detection circuits described above. These two detection circuits will be described separately below.

The first detection circuit, which includes a compensation circuit, i.e. the second capacitor C2, indirectly couples the second voltage V2 into the LDO 1.

Specifically, the at least one detection circuit 2 includes a first detection circuit 2a, and the first detection circuit 2a includes: a compensation circuit 22 coupled between the second capacitor C2 and the LDO1, the compensation circuit 22 being configured to adjust the first voltage V1 according to the second voltage V2 to maintain the first voltage V1 constant. The first detection circuit 2a may refer to a detection circuit including the compensation circuit 22 herein.

In one possible embodiment, as shown in fig. 4, the compensation circuit 22 comprises: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second resistor R2, and a third resistor R3. Wherein, one pole of the fourth transistor M4, one end of the third resistor R3 and one pole of the sixth transistor M6 are coupled to the first node (1), the other pole of the fourth transistor M4, the control end of the fifth transistor M5 and one end of the second resistor R2 are coupled to be an input end of the compensation circuit 22, one pole of the fifth transistor M5 and the other end of the second resistor R2 are coupled to the second node (2), the other pole of the fifth transistor M5, the control end of the sixth transistor M6 and the other end of the third resistor R3 are coupled, and the other pole of the sixth transistor M6 is used as an output end of the compensation circuit 22; one of the first node (1) and the second node (2) is coupled to a supply terminal and the other is coupled to ground.

Optionally, the at least one detection circuit 2 may include one or more first detection circuits, and outputs of the one or more first detection circuits may be coupled to different nodes or the same node of the LDO1, that is, a plurality of first detection circuits are fed back to different nodes or the same node of the LDO 1. Illustratively, as shown in fig. 4, it is assumed that at least one of the detection circuits 2 includes two first detection circuits, wherein the first node (1) of the compensation circuit 22 of one of the first detection circuits (denoted as 2a-1 in fig. 4) is coupled to the power supply terminal, the second node (2) is coupled to the ground terminal, and the first node (1) of the compensation circuit 22 of the other first detection circuit (denoted as 2a-2 in fig. 4) is coupled to the ground terminal, and the second node (2) is coupled to the power supply terminal. Fig. 4 illustrates that the output terminals of the two first detection circuits are both coupled to the output terminal of the LDO1 (i.e. both of the two first detection circuits are fed back to the output terminal of the LDO 1), and the LDO is the LDO shown in fig. 1, and VBP and VBN respectively represent different bias voltage terminals.

It should be noted that, in the first detection circuit 2a-1, the fifth transistor M5 is an NMOS transistor, the fourth transistor M4 and the sixth transistor M6 are PMOS transistors, in the first detection circuit 2a-2, the fifth transistor M5 is a PMOS transistor, the fourth transistor M4 and the sixth transistor M6 are NMOS transistors, the first electrode is a drain electrode, the other electrode is a source electrode, and the control terminal is a gate electrode. In practical applications, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may also be replaced by other transistors with similar functions, and the above-mentioned fig. 4 does not limit the embodiments of the present application.

In addition, the second resistor R2 and the third resistor R3 in fig. 4 may also be replaced by other devices having similar functions, for example, the second resistor R2 may be replaced by an NMOS transistor, the third resistor R3 may be replaced by a PMOS transistor, and the gates of the NMOS transistor and the PMOS transistor may be connected to the bias voltage terminal.

In fig. 4, the first detection circuit 2a-1 may be referred to as an undershoot (undershoot) detection circuit, and is configured to implement boost compensation for the first voltage V1 when the first voltage V1 output by the LDO1 undershoots. Specifically, when the first voltage V1 output by the LDO1 undershoots, the first detection circuit 2a-1 detects undershoot burrs of the first voltage V1 (i.e., a coupling voltage is generated according to a change of the first voltage V1) through the first capacitor C1, and the undershoot burrs are amplified by the amplifier 21 formed by M1, M2, M3, and R1 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the fifth transistor M5 in the compensation circuit 22 through the second capacitor C2, at this time, the fifth transistor M5 is turned on, the gate voltage of the sixth transistor M6 is pulled low, so that the sixth transistor M6 is turned on, and the drain voltage of the sixth transistor M6 is used for compensating the first voltage V1 output by the LDO1, so as to implement boost compensation of the first voltage V1, that is, implement transient compensation when the first voltage V1 undershoots.

During the operation of the first detection circuit 2a-1, the transient compensation is triggered only if the second voltage V2 output via the amplifier 21 exceeds the threshold voltage of the fifth transistor M5. The drain of the fourth transistor M4 forms a bias voltage after passing through the second resistor R2, which can lower the threshold voltage of the fifth transistor M5, so that the signal coupled through the second capacitor C2 can immediately turn on the fifth transistor M5. In addition, when the first voltage V1 output by the LDO1 does not undershoot or the undershoot is smaller than the threshold voltage of the fifth transistor M5, the fifth transistor M5 in the compensation circuit 22 is turned off, and the third resistor R3 pulls up to turn off the sixth transistor M6, so that the first detection circuit 2a-1 has no influence on the LDO 1.

In fig. 4, the first detection circuit 2a-2 may be referred to as an overshoot (overshoot) detection circuit, and is configured to implement a step-down adjustment of the first voltage V1 when the first voltage V1 output by the LDO1 overshoots. Specifically, when the first voltage V1 output by the LDO1 overshoots, the first detection circuit 2a-2 detects an overshoot of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to a change of the first voltage V1), and the overshoot is amplified by the amplifier 21 formed by M1, M2, M3, and R1 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the fifth transistor M5 in the compensation circuit 22 through the second capacitor C2, at this time, the fifth transistor M5 is turned on, the gate voltage of the sixth transistor M6 is pulled down, so that the sixth transistor M6 is turned on, and the drain voltage of the sixth transistor M6 is used for pulling down the first voltage V1 output by the LDO1, thereby realizing the buck adjustment of the first voltage V1, i.e., realizing the transient compensation when the first voltage V1 is pulled up.

During operation of the first detection circuit 2a-2, transient compensation is triggered only if the second voltage V2 output via the amplifier 21 exceeds the threshold voltage of the fifth transistor M5. The drain of the fourth transistor M4 forms a bias voltage after passing through the second resistor R2, which can lower the threshold voltage of the fifth transistor M5, so that the signal coupled through the second capacitor C2 can immediately turn on the fifth transistor M5. In addition, when the first voltage V1 output by the LDO1 does not overshoot or the overshoot is smaller than the threshold voltage of the fifth transistor M5, the fifth transistor M5 in the compensation circuit 22 is turned off, and the third resistor R3 pulls down to turn off the sixth transistor M6, so that the first detection circuit 2a-2 has no influence on the LDO 1.

In another possible embodiment, as shown in fig. 5, the compensation circuit 22 comprises: a fourth transistor M4, a fifth transistor M5, and a second resistor R2. Wherein, one pole of the fourth transistor M4 is coupled to the first node (1), the other pole of the fourth transistor M4, the control terminal of the fifth transistor M5 and one end of the second resistor R2 are coupled to serve as the input terminal of the compensation circuit 22, one pole of the fifth transistor M5 and the other end of the second resistor R2 are coupled to the second node (2), and the other pole of the fifth transistor M5 serves as the output terminal of the compensation circuit 22; one of the first node (1) and the second node (2) is coupled to a supply terminal and the other is coupled to ground.

Optionally, the at least one detection circuit 2 may comprise one or more first detection circuits, and outputs of the one or more first detection circuits may be coupled to different nodes or the same node of the LDO1, i.e. the plurality of first detection circuits feed back to the plurality of first detection circuits. For example, as shown in fig. 5, it is assumed that at least one detection circuit 2 includes a first detection circuit 2a, a first node (1) of a compensation circuit 22 of the first detection circuit 2a is coupled to a power supply terminal, and a second node (2) is coupled to a ground terminal; the LDO is the LDO shown in fig. 1, and the output end of the first detection circuit 2a is coupled to the gate of the regulator transistor M0 in the LDO1, i.e., the first detection circuit 2a feeds back to the gate of the regulator transistor M0 in the LDO 1). The working principle of the first detection circuit 2a is similar to that of the first detection circuit 2a-1, and the description of the embodiment of the present application is omitted here.

It should be noted that, in fig. 5, the fourth transistor M4 is a PMOS transistor, the fifth transistor M5 is an NMOS transistor, the first electrode is a drain electrode, the second electrode is a source electrode, and the control terminal is a gate electrode; in practical applications, the fourth transistor M4 and the fifth transistor M5 may also be replaced by other transistors having similar functions. In fig. 5, at least one detection circuit 2 including a first detection circuit 2a will be described as an example. Fig. 5 described above does not limit the embodiments of the present application.

Further, the first detection circuit shown in fig. 4 and fig. 5 can be applied to other LDOs besides the LDO1 shown in fig. 1. For example, the operational amplifier A0 in the LDO1 may be an operational amplifier built by a plurality of transistors, or the LDO may be a Flipped Voltage Follower (FVF) LDO, that is, an FVF LDO.

For example, as shown in fig. 6, the operational amplifier A0 in the LDO1 may include 12 transistors T1 to T12, the connection relationship of the transistors T1 to T12 is specifically shown, and VBP and VBN respectively represent bias voltages. At least one detection circuit 2 may be fed back to any node in the operational amplifier A0 to form negative feedback, for example, at least one detection circuit 2 is fed back to the gate of the transistor T2 (also referred to as the gate of the transistor T3), or at least one detection circuit 2 is fed back to the gate of the transistor T5 (also referred to as the gate of the transistor T6). It should be noted that, in fig. 6, transistors T1, T4, T8, T9, T10, T11, and T12 are all PMOS transistors, and transistors T2, T3, T5, T6, and T7 are all NMOS transistors, and the transistors T1 to T12 may be replaced by other transistors having similar functions, or the operational amplifier A0 includes more or less transistors, and the foregoing fig. 6 does not limit the embodiment of the present application.

For example, as shown in fig. 7, when the LDO1 is an FVF LDO, the LDO1 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a fourth resistor R4. Wherein, a pole of the seventh transistor M7 and a pole of the eighth transistor M8 are both coupled to the power source terminal, the other pole of the seventh transistor M7 is coupled to a pole of the ninth transistor M9 as the output terminal of the LDO1, the other pole of the eighth transistor M8, a pole of the tenth transistor M10 and the control terminal of the seventh transistor M7 are coupled (the voltage at the coupling point is represented as V) _FB2 ) The other pole of the ninth transistor M9, the other pole of the tenth transistor M10 and the one pole of the eleventh transistor M11 are coupled (the voltage of the coupling point is denoted by V _FB1 ) The other pole of the eleventh transistor M11 is coupled to the ground terminal, the control terminal of the eleventh transistor M11 is coupled to one terminal of the fourth resistor R4, and the other terminal of the fourth resistor R4 is connected to the bias voltage terminal VBN 1.

It should be noted that, in fig. 7, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are all PMOS transistors, the tenth transistor M10 and the eleventh transistor M11 are all NMOS transistors, the first electrode of the seventh transistor M7 to the ninth transistor is a source electrode, the other electrode of the seventh transistor M7 to the ninth transistor is a drain electrode, the first electrode of the tenth transistor M10 and the eleventh transistor M11 is a drain electrode, the other electrode of the tenth transistor M11 is a source electrode, and the control end is a gate electrode for example; in practical applications, the seventh transistor M7 to the eleventh transistor M11 may also be replaced by other transistors having similar functions, and the foregoing fig. 7 does not limit the embodiment of the present application.

The output end of the first detection circuit shown in fig. 4 or fig. 5 may also be coupled to the output end of the FVF LDO or another node inside the FVF LDO, for example, the output end of the first detection circuit is coupled to the control end of the seventh transistor M7 in the FVF LDO, or the output end of the first detection circuit is coupled to the control end of the eighth transistor M8 in the FVF LDO, or the output end of the first detection circuit is coupled to the control end of the tenth transistor M10 in the FVF LDO, or the output end of the first detection circuit is coupled to the control end of the eleventh transistor M11 in the FVF LDO, and so on.

A second detection circuit without a compensation circuit, i.e. the second capacitor C2 directly couples the second voltage V2 into the LDO 1. The following will exemplify the configuration of the FVF LDO shown in fig. 7.

In one possible embodiment, as shown in fig. 8, the at least one detection circuit 2 includes a second detection circuit 2b, and a second capacitor C2 in the second detection circuit 2b is coupled between the output terminal of the amplifier 21 and the control terminal (i.e., the gate) of the eighth transistor M8, i.e., the second detection circuit 2b is fed back to the gate of the eighth transistor M8 in the FVF LDO.

Specifically, when the first voltage V1 output by the FVF LDO is normal, the second detection circuit 2b is not operated, and assuming that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, the current flowing through the tenth transistor M10 is I10, and the current flowing through the ninth transistor M9 is I9, I11= I9+ I8, and I8= I10.

When the FVF LDO undershoots, the second detection circuit 2b detects undershoot burrs of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to a change of the first voltage V1), and the undershoot burrs are amplified by the amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the eighth transistor M8 in the FVF LDO through the second capacitor C2, the voltage of the gate-source (i.e., vgs) of the eighth transistor M8 is decreased to control the current I8 flowing through the eighth transistor M8 to be decreased, and at the same time, since the current I10 flowing through the tenth transistor M10 remains unchanged, I10 is greater than I8, so that the gate voltage V of the seventh transistor is increased _BF2 Will be pulled down, the gate-source voltage (i.e. Vgs) of the seventh transistor M7 increases rapidly, and then the output current of the FVF LDO is increased, i.e. the transient compensation when the first voltage V1 undershoots is realized.

When the FVF LDO is overshot, the second detection circuit 2b detects the overshoot of the first voltage V1 through the first capacitor C1 (i.e. the coupling voltage is generated according to the change of the first voltage V1), and the overshoot is amplified by the amplifier 21 to obtain the second voltageV2; the second voltage V2 is coupled to the gate of the eighth transistor M8 in the FVF LDO through the second capacitor C2, at which time the gate-source voltage (i.e., vgs) of the eighth transistor M8 is increased to control the current I8 flowing through the eighth transistor M8 to be increased, and at the same time, since the current I10 flowing through the tenth transistor M10 is kept unchanged, at which time I10 is smaller than I8, so that the gate voltage V of the seventh transistor is _BF2 Will be pulled high, the gate-source voltage (i.e. Vgs) of the seventh transistor M7 is decreased, and then the output current of the FVF LDO is decreased, i.e. transient compensation when the first voltage V1 is pulled up is realized.

In another possible embodiment, as shown in fig. 9, the at least one detection circuit 2 includes a third detection circuit 2C, and a second capacitor C2 in the third detection circuit 2C is coupled between the output terminal of the inverting amplifier 21 and the control terminal (i.e. the gate) of the tenth transistor M10, i.e. the third detection circuit 2C feeds back to the gate of the tenth transistor M10 in the FVF LDO.

When the FVF LDO undershoots, the third detection circuit 2C detects undershoot burrs of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to a change of the first voltage V1), and the undershoot burrs are amplified by the inverting amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the tenth transistor M10 of the FVF LDO through the second capacitor C2, at which time the gate-source voltage (i.e., vgs) of the tenth transistor M10 increases to control the current I10 flowing through the tenth transistor M10 to increase, and at the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, at which time I10 is greater than I8, the gate voltage V of the seventh transistor is thereby increased _BF2 Will be pulled down, the gate-source voltage (i.e. Vgs) of the seventh transistor M7 increases rapidly, and then the output current of the FVF LDO is increased, i.e. the transient compensation when the first voltage V1 undershoots is realized.

When the FVF LDO is rushed up, the third detection circuitThe circuit 2C detects an overshoot of the first voltage V1 (i.e., a coupling voltage is generated according to a change of the first voltage V1) through the first capacitor C1, and the overshoot is amplified by the inverting amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the tenth transistor M10 in the FVF LDO through the second capacitor C2, at which time the gate-source voltage (i.e., vgs) of the tenth transistor M10 is reduced to control the current I10 flowing through the tenth transistor M10 to be reduced, and at the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, at which time I10 is smaller than I8, so that the gate voltage V of the seventh transistor is _BF2 Will be pulled high, the gate-source voltage (i.e. Vgs) of the seventh transistor M7 is decreased, and then the output current of the FVF LDO is decreased, i.e. transient compensation when the first voltage V1 is pulled up is realized.

In yet another possible embodiment, as shown in fig. 10, the at least one detection circuit 2 includes a fourth detection circuit 2d, and the second capacitor C2 in the fourth detection circuit 2d is coupled between the output terminal of the inverting amplifier 21 and the control terminal (i.e. the gate) of the eleventh transistor M11, i.e. the fourth detection circuit 2d is fed back to the gate of the eleventh transistor M11 in the FVF LDO.

Specifically, when the first voltage V1 output by the FVF LDO is normal, the second detection circuit 2b is not operated, and it is assumed that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, the current flowing through the tenth transistor M10 is I10, and the current flowing through the ninth transistor M9 is I9, I11= I9+ I8, and I8= I10.

When the FVF LDO undershoots, the fourth detection circuit 2d detects undershoot burrs of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to a change of the first voltage V1), and the undershoot burrs are amplified by the inverting amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the eleventh transistor M11 in the FVF LDO through the second capacitor C2, when the gate-source voltage (i.e., vgs) of the eleventh transistor M11 increases to control the current I10 flowing through the eleventh transistor M10 to increase, and simultaneously, since the current I8 flowing through the eighth transistor M8 remains unchanged, the current I9 flowing through the ninth transistor M9 decreases, the current I10 flowing through the tenth transistor M10 increases, when I10 is greater than I8, so that the tenth transistor M10 increases, thereby increasing the voltage of the eighth transistor M8Gate voltage V of seven transistors _BF2 Will be pulled down, the gate-source voltage (i.e. Vgs) of the seventh transistor M7 increases rapidly, and then the output current of the FVF LDO is increased, i.e. the transient compensation when the first voltage V1 undershoots is realized.

When the FVF LDO overshoots, the fourth detection circuit 2d detects an overshoot glitch of the first voltage V1 (i.e., a coupling voltage is generated according to a change of the first voltage V1) through the first capacitor C1, and the overshoot glitch is amplified by the amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the eleventh transistor M11 in the FVF LDO through the second capacitor C2, at which time the gate-source voltage (i.e., vgs) of the eleventh transistor M11 is decreased to control the current I11 flowing through the eleventh transistor M11 to decrease, while the current I9 flowing through the ninth transistor M9 is increased and the current I10 flowing through the tenth transistor M10 is decreased because the current I8 flowing through the eighth transistor M8 remains unchanged, at which time I10 is less than I8, so that the gate voltage V of the seventh transistor is V8 _BF2 Will be pulled high, the gate-source voltage (i.e. Vgs) of the seventh transistor M7 is decreased, and then the output current of the FVF LDO is decreased, i.e. transient compensation when the first voltage V1 is pulled up is realized.

Further, for overshoot compensation or undershoot compensation of LDO1, transient compensation of LDO1 can be realized by using a plurality of detection circuits, and the output ends of the plurality of detection circuits can be coupled with different nodes in LDO1, and it is only necessary to ensure that each detection circuit forms negative feedback with the coupling of LDO 1.

For example, as shown in fig. 11, taking undershoot compensation of the FVF LDO as an example, the at least one detection circuit 2 may include four detection circuits, which are respectively denoted as 201 to 204, wherein an output terminal of the detection circuit 201 is coupled to an output terminal of the FVF LDO, an output terminal of the detection circuit 202 is coupled to a gate of the seventh transistor M7 in the FVF LDO, an output terminal of the detection circuit 203 is coupled to a gate of the eighth transistor M8 in the FVF LDO, and an output terminal of the detection circuit 204 is coupled to a gate of the eleventh transistor M11 in the FVF LDO.

The working principle of the detection circuit 201 is similar to that of the first detection circuit 2a-1 shown in fig. 4, the working principle of the detection circuit 202 is similar to that of the first detection circuit 2a shown in fig. 5, the working principle of the detection circuit 203 is similar to that of the second detection circuit 2b shown in fig. 8, and the working principle of the detection circuit 204 is similar to that of the fourth detection circuit 2d shown in fig. 10, which is specifically referred to the above description, and the embodiments of the present application are not repeated herein.

In the embodiment of the application, transient compensation is performed on the overshoot or undershoot of the LDO1 through a plurality of detection circuits, so that the transient compensation of the LDO1 can be realized more quickly, and the transient performance of the LDO1 is improved; in addition, when the first voltage V1 output by the LDO1 is normal or has a small change, the plurality of detection circuits may be in an off state, so that the dc characteristic of the LDO1 is not affected, and the stability of the loop of the LDO1 is ensured.

Based on this, embodiments of the present application also provide a chip system, which includes a load circuit, and any one of the transient boost circuits provided above for an LDO, the transient boost circuit including an LDO for supplying power to the load circuit, and at least one detection circuit coupled with the LDO for boosting a transient of the LDO. Optionally, the load circuit may comprise at least one of: RF transceivers, DACs, ADCs, high-speed digital circuits (e.g., system-on-a-chip SoC), PLLs.

An embodiment of the present application also provides an apparatus, including a load circuit and a circuit board, the circuit board including any one of the transient boost circuits provided above for an LDO, the transient boost circuit including an LDO and at least one detection circuit coupled with the LDO, the LDO to power the load circuit, the at least one detection circuit to improve a transient of the LDO. Optionally, the load circuit may comprise at least one of: RF transceivers, DACs, ADCs, high-speed digital circuits (e.g., system-on-a-chip socs), PLLs; in addition, the device may be a communication device or a voltage stabilization device, or the like. This is not particularly limited by the examples of the present application.

It should be noted that, the descriptions provided above for the transient boost circuit of the LDO can be incorporated into the chip system or the device, and the detailed description of the embodiments of the present application is omitted here.

In another aspect of the present application, there is also provided a non-transitory computer readable storage medium for use with a computer having software for creating an integrated circuit, the computer readable storage medium having stored thereon one or more computer readable data structures having photomask data for manufacturing a transient boost circuit for an LDO as provided in any of the illustrations provided above.

Finally, it should be noted that: the above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A transient boost circuit for a low dropout linear regulator (LDO), comprising:

the LDO is used for outputting a first voltage;

at least one detection circuit coupled with the LDO, each detection circuit of the at least one detection circuit comprising a first capacitance, an amplifier, and a second capacitance;

the first capacitor is used for generating a coupling voltage according to the change of the first voltage and coupling the coupling voltage to the amplifier;

the amplifier is used for amplifying the coupling voltage to obtain a second voltage;

the second capacitor is used for coupling the second voltage to the LDO, and the second voltage is used for regulating the first voltage to maintain the first voltage to be constant.
The circuit of claim 1, wherein the amplifier comprises: a first transistor, a second transistor, a third transistor, and a first resistor;

wherein one pole of the first transistor, one pole of the second transistor and one end of the first resistor are coupled as an output terminal of the amplifier, a control terminal of the first transistor, a control terminal of the second transistor and the other end of the first resistor are coupled as an input terminal of the amplifier, the other pole of the second transistor is coupled with one pole of the third transistor, one of the other pole of the first transistor and the other pole of the third transistor is coupled with a power supply terminal, the other is coupled with a ground terminal, and the control terminal of the third transistor is coupled with a bias voltage terminal.
The circuit of claim 1 or 2, wherein the at least one detection circuit comprises a first detection circuit, the first detection circuit further comprising: a compensation circuit coupled between the second capacitance and the LDO;

the compensation circuit is used for adjusting the first voltage according to the second voltage so as to maintain the first voltage to be constant.
The circuit of claim 3, wherein the compensation circuit comprises: a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, and a third resistor;

wherein one pole of the fourth transistor, one end of the third resistor and one pole of the sixth transistor are coupled to a first node, the other pole of the fourth transistor, the control terminal of the fifth transistor and one end of the second resistor are coupled to serve as the input terminal of the compensation circuit, one pole of the fifth transistor and the other end of the second resistor are coupled to a second node, the other pole of the fifth transistor, the control terminal of the sixth transistor and the other end of the third resistor are coupled, and the other pole of the sixth transistor serves as the output terminal of the compensation circuit;

one of the first node and the second node is coupled to a power supply terminal and the other is coupled to a ground terminal.
The circuit of claim 4, wherein the LDO has an output, and wherein the output of the compensation circuit is coupled to the output of the LDO.
The circuit of claim 3, wherein the compensation circuit comprises: a fourth transistor, a fifth transistor, and a second resistor;

wherein one pole of the fourth transistor is coupled to the first node, the other pole of the fourth transistor, the control terminal of the fifth transistor and one end of the second resistor are coupled to be the input terminal of the compensation circuit, one pole of the fifth transistor and the other end of the second resistor are coupled to the second node, and the other pole of the fifth transistor is used as the output terminal of the compensation circuit; one of the first node and the second node is coupled to a power supply terminal and the other is coupled to a ground terminal.
The circuit of claim 6, wherein the LDO comprises an operational amplifier, a regulating transistor and a sampling circuit, an output terminal of the operational amplifier is coupled to a control terminal of the regulating transistor, one terminal of the regulating transistor is coupled to a power supply terminal, the other terminal of the regulating transistor is coupled to an input terminal of the sampling circuit as an output terminal of the LDO, an output terminal of the sampling circuit is coupled to a positive input terminal of the operational amplifier, and a negative input terminal of the operational amplifier is configured to receive a reference voltage;

wherein an output terminal of the compensation circuit is coupled to a control terminal of the voltage regulating transistor.
The circuit of any of claims 1-5, wherein the LDO comprises: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a fourth resistor;

one electrode of the seventh transistor and one electrode of the eighth transistor are both coupled to a power supply terminal, the other electrode of the seventh transistor is coupled to one electrode of the ninth transistor to serve as an output terminal of the LDO, the other electrode of the eighth transistor, one electrode of the tenth transistor and the control terminal of the seventh transistor are coupled, the other electrode of the ninth transistor, the other electrode of the tenth transistor and one electrode of the eleventh transistor are coupled, the other electrode of the eleventh transistor is coupled to a ground terminal, the control terminal of the eleventh transistor is coupled to one end of the fourth resistor, and the other end of the fourth resistor is connected to a bias voltage terminal.
The circuit of claim 8, wherein the at least one detection circuit further comprises a second detection circuit, and wherein the second capacitor of the second detection circuit is coupled between the output of the amplifier and the control terminal of an eighth transistor.
The circuit of claim 8 or 9, wherein the at least one detection circuit further comprises a third detection circuit, wherein the second capacitor of the third detection circuit is coupled between the output of the amplifier and a control terminal of a tenth transistor.
The circuit of any of claims 8-10, wherein the at least one detection circuit further comprises a fourth detection circuit, and wherein the second capacitor of the fourth detection circuit is coupled between the output of the amplifier and a control terminal of an eleventh transistor.
A chip system, comprising a load circuit and the transient boost circuit of any one of claims 1 to 11 for a low dropout regulator LDO; wherein the transient boost circuit comprises an LDO for powering the load circuit, and at least one detection circuit coupled with the LDO for boosting a transient of the LDO.
An apparatus comprising a load circuit and a circuit board, the circuit board comprising the transient boost circuit for a low dropout linear regulator (LDO) of any of claims 1-11; wherein the transient boost circuit comprises an LDO for powering the load circuit, and at least one detection circuit coupled with the LDO for boosting a transient of the LDO.