CN115664418B - SAR ADC precision calibration method and device based on nonlinear error - Google Patents
SAR ADC precision calibration method and device based on nonlinear error Download PDFInfo
- Publication number
- CN115664418B CN115664418B CN202211690383.0A CN202211690383A CN115664418B CN 115664418 B CN115664418 B CN 115664418B CN 202211690383 A CN202211690383 A CN 202211690383A CN 115664418 B CN115664418 B CN 115664418B
- Authority
- CN
- China
- Prior art keywords
- signal
- error
- sar adc
- calibration
- nonlinear
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000005070 sampling Methods 0.000 claims abstract description 118
- 230000000737 periodic effect Effects 0.000 claims abstract description 114
- 238000001514 detection method Methods 0.000 claims abstract description 63
- 230000010355 oscillation Effects 0.000 claims abstract description 51
- 230000009194 climbing Effects 0.000 claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims description 45
- 230000000875 corresponding effect Effects 0.000 claims description 17
- 238000004364 calculation method Methods 0.000 claims description 8
- 238000012360 testing method Methods 0.000 claims description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 230000002596 correlated effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 13
- 238000010998 test method Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000012952 Resampling Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000007619 statistical method Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The application provides a method and a device for calibrating precision of SAR ADC based on nonlinear error, wherein the method for calibrating the precision comprises the following steps: generating a step climbing signal and generating a periodic oscillation signal; superposing the periodic oscillation signal and the step climbing signal to obtain a superposed signal, wherein the superposed signal consists of a plurality of periodic oscillator sub-signals; the SAR ADC receives a first periodic oscillator sub-signal in the periodic oscillator sub-signals, samples the first periodic oscillator sub-signal at a plurality of sampling signal points to obtain a first sampling signal capacitance value, and sends the first sampling signal capacitance value to the nonlinear error detection calibration module; the nonlinear error detection calibration module calculates a first nonlinear error according to the step climbing signal and the capacitance value of the first sampling signal, and compares the first nonlinear error with a preset nonlinear error threshold value. The application also provides a device for calibrating the precision of the SAR ADC based on the nonlinear error.
Description
Technical Field
The application relates to the technical field of successive approximation type analog-to-digital converters, in particular to a method and a device for calibrating SAR ADC precision based on nonlinear errors.
Background
Non-linear errors, including Integral Non-linear (INL) and Differential Non-linear (DNL) errors, are present in SAR-type ADCs. The non-linearity error is a non-ideal error due to the manufacturing materials and processes of the SAR-type ADC. DNL error (hereinafter abbreviated DNL) refers to the degree of nonlinearity of the ADC locally, and INL error (hereinafter abbreviated INL) refers to the degree of nonlinearity of the ADC as a whole, that is, the DNL is accumulated.
In the conventional technology, in order to measure the non-linear error of the SAR ADC, a high-precision ramp signal test method or a sine wave code density test method is generally used for measurement.
Disclosure of Invention
The exemplary embodiments of the present application provide a method for calibrating the accuracy of a SAR ADC based on a nonlinear error, where the number of bits of a capacitor to be calibrated of the SAR ADC is N, where N is a natural number greater than or equal to 2, and the method includes: step S100, a nonlinear error detection calibration module generates a step climbing signal, wherein the number of steps of the step climbing signal is the same as the number N of the capacitance bits to be calibrated of the SAR ADC, and the width of the steps of the step climbing signal is related to the sampling rate of the SAR ADC; step S200, generating a periodic oscillation signal, wherein the SAR ADC has an input offset error, an input noise and an input direct current level error, and the amplitude of the periodic oscillation signal is greater than or equal to the sum of the input offset error, the input noise and the input direct current level error; step S300, superposing the periodic oscillation signal and the step climbing signal to obtain a superposed signal, wherein the superposed signal is composed of a plurality of periodic oscillation sub-signals respectively corresponding to the capacitance number to be calibrated of the SAR ADC, and the amplitudes of the plurality of periodic oscillation sub-signals are respectively greater than or equal to the amplitudes of the periodic oscillation signals; step S400, the SAR ADC receives a first periodic oscillator sub-signal of a plurality of periodic oscillator sub-signals of the superimposed signal, samples the first periodic oscillator sub-signal at a plurality of sampling signal points to obtain a first sampling signal capacitance value, and sends the first sampling signal capacitance value to the nonlinear error detection calibration module connected to the SAR ADC; step S500, the nonlinear error detection calibration module calculates a corresponding first nonlinear error of the first periodic oscillator sub-signal according to the step climbing signal and the capacitance value of the first sampling signal, and compares the first nonlinear error with a preset nonlinear error threshold to obtain a comparison result, wherein the preset nonlinear error threshold is inversely related to the number of sampling points of the SAR ADC; step S600, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends a calibration signal to the SAR ADC to calibrate the capacitance value of the first sampling signal, so that the first nonlinear error is smaller than the preset nonlinear error threshold; and step S700, when the comparison result indicates that the first non-linear error is less than or equal to the preset non-linear error threshold, repeating steps S400, S500, and S600 for a next periodic oscillator sub-signal of the first periodic oscillator sub-signal until all the periodic oscillator sub-signals are calibrated.
In an embodiment, the periodic oscillation signal is a sine wave signal, and the plurality of periodic oscillation sub-signals are a plurality of sine wave sub-signals.
In one embodiment, the SAR ADC is disposed within a chip, and the nonlinear error detection calibration module is disposed outside the chip.
In an embodiment, the nonlinear error detection calibration module further has an output end connected to a digital-to-analog converter disposed outside the chip, and the output end outputs an N-bit digital signal to the digital-to-analog converter to sequentially generate the step climbing signal.
In one embodiment, the calibration signal includes offset error calibration step values, the offset error calibration step values are:
wherein, in the process,E NL for the pre-set non-linear error threshold,S trim calibrating a step value for the misalignment error; the step S600 includes: step S610, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends the calibration signal to the SAR ADC, so as to calibrate the first nonlinear error by reducing the offset error calibration step value for the absolute value of the capacitance value of the first sampling signal.
In an embodiment, the calibration signal includes an offset error calibration step value, and the step S600 includes: step S620, setting the offset error calibration stepping value to be 0.5 LSB; step S630, when the comparison result is that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends the calibration signal to the SAR ADC, so as to obtain a calibrated sampling signal capacitance value by decreasing the offset error calibration step value by the absolute value of the first sampling signal capacitance value, wherein when the absolute value of the calibrated sampling signal capacitance value is less than the offset error calibration step value and is greater than or equal to the preset nonlinear error threshold, the offset error calibration step value is halved, and the step S630 is repeated.
In an embodiment, the calibration signal comprises an offset error calibration step value, the offset error calibration step value being a fixed value, the fixed value being one of 0.1 LSB, 0.2 LSB, 0.3 LSB.
In an embodiment, the step of calculating the first nonlinear error of the first periodic oscillator sub-signal according to the step climbing signal and the first sampling signal capacitance value by the nonlinear error detection calibration module is based on a sine wave histogram code density test method to calculate the first nonlinear error.
In an embodiment, the non-linear error is an integral non-linear error or a derivative non-linear error.
In an embodiment, the predetermined non-linear error threshold is calculated by the following formula:
wherein, E NL For the pre-set non-linear error threshold,kis a constant of proportionality that is,S N the number of sampling points of the SAR ADC.
In an embodiment, the number of sampling points of the SAR ADC is positively correlated with the number of capacitance bits to be calibrated of the SAR ADC; the calculation formula of the sampling points of the SAR ADC is as follows:
whereinS N and N is the number of the sampling points of the SAR ADC, and N is the number of the capacitance bits to be calibrated of the SAR ADC.
In one embodiment, the number of bits N of the capacitor to be calibrated ranges from 2 to 16.
In another aspect of the present application, a device for calibrating the accuracy of a SAR ADC based on a nonlinear error is provided, where the number of bits of a capacitor to be calibrated of the SAR ADC is N, where N is a natural number greater than or equal to 2. The precision calibration device includes: a signal generation module configured to generate a periodic oscillating signal, wherein the SAR ADC has an input offset error, an input noise, and an input DC level error, and an amplitude of the periodic oscillating signal is greater than or equal to a sum of the input offset error, the input noise, and the input DC level error; a nonlinear error detection calibration module configured to generate a step climbing signal, wherein the number of steps of the step climbing signal is the same as the number of bits N of the capacitor to be calibrated of the SAR ADC, and the width of the steps of the step climbing signal is related to the sampling rate of the SAR ADC; a signal superposition module configured to superpose the periodic oscillation signal and the step climbing signal to obtain a superposed signal, wherein the superposed signal is composed of a plurality of periodic oscillation sub-signals respectively corresponding to the number of bits of the capacitor to be calibrated of the SAR ADC, and amplitudes of the plurality of periodic oscillation sub-signals are respectively greater than or equal to the amplitude of the periodic oscillation signal; and the SAR ADC configured to receive a first periodic oscillator sub-signal of a plurality of periodic oscillator sub-signals of the superimposed signal, the first periodic oscillator sub-signal sampled at a plurality of sampling signal points to obtain a first sampled signal capacitance value; wherein the non-linear error detection calibration module is further configured to receive the first sampled signal capacitance value from the SAR ADC, calculate a corresponding first non-linear error of the first periodic oscillator sub-signal according to the step ramp signal and the first sampled signal capacitance value, and compare the first non-linear error with a preset non-linear error threshold value to obtain a comparison result, wherein the preset non-linear error threshold value is inversely related to the number of sampling points of the SAR ADC; when the comparison result is that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends a calibration signal to the SAR ADC to calibrate the capacitance value of the first sampling signal so that the first nonlinear error is less than the preset nonlinear error threshold; and when the comparison result is that the first nonlinear error is less than or equal to the preset nonlinear error threshold, repeatedly executing a calibration step for a next periodic oscillator sub-signal of the first periodic oscillator sub-signal.
In one embodiment, the SAR ADC is disposed within a chip, and the nonlinear error detection calibration module is disposed outside the chip.
As described above, in the conventional technique, a high-precision ramp signal test method or a sine wave code density test method is generally used for measurement. However, the signal generator for generating the high-precision ramp signal is generally expensive, and the low-precision ramp signal generator cannot meet the precision requirement of the high-precision SAR ADC. Although the sine wave signal generator is low in price and can also generate sine wave signals meeting the precision requirement, the data volume required to be measured and analyzed is far larger than the data volume of the output codes of the SAR type ADC, the measurement time of the nonlinear errors is too long, and the nonlinear error calibration efficiency is low.
Based on this, in the conventional technology, other characteristic parameters of the SAR ADC are usually measured, and then the nonlinear error is obtained through corresponding calculation, which often results in inaccurate obtained nonlinear error.
Aiming at the defects of the traditional technology, the superposed signal generated by superposing the periodic oscillation signal and the step climbing signal is utilized to detect the capacitor to be calibrated of the high-precision SAR type ADC so as to detect and calibrate the nonlinear error, the precision requirement of the climbing signal is reduced, meanwhile, the small-amplitude periodic oscillation signal superposed on each step compensates the precision loss of the step climbing signal, the data volume of DNL sampling is reduced, and therefore, the detection and calibration efficiency is improved while the detection and calibration precision is maintained.
Drawings
Fig. 1 is a circuit diagram of an application of a method for calibrating the accuracy of a SAR ADC based on a nonlinear error according to an embodiment of the present application.
Fig. 2 is a block diagram of the SAR ADC of the embodiment of fig. 1.
Fig. 3 is a flowchart of a method for calibrating the accuracy of a SAR ADC based on a nonlinear error according to an embodiment of the present application.
Fig. 4 is a diagram of a superimposed signal according to an embodiment of the present application.
Fig. 5 is a schematic diagram of the periodic oscillator sub-signals of the superimposed signal of the embodiment of fig. 4.
Fig. 6 is a flowchart of a method for calibrating sar adc accuracy based on non-linearity error according to another embodiment of the present application.
Fig. 7 is a flowchart of a method for calibrating the accuracy of a SAR ADC based on a nonlinear error according to another embodiment of the present application.
Fig. 8 is a logic control diagram of a method for calibrating the precision of sar adc based on non-linearity error according to an embodiment of the present application.
Fig. 9 is a block diagram of a precision calibration apparatus of a SAR ADC based on a non-linear error according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
In this application, use of ordinal terms such as "first" and "second" to modify an element does not denote any priority, order, or sequence of one element relative to another or the temporal order in which acts in a method are performed. Unless otherwise specifically stated, such ordinal words are used merely as labels to distinguish one element having a particular name from another element having the same name (except for the ordinal word).
Herein, unless the context defines otherwise, the term "connected" means electrically connected. The terms "comprising," "including," and "containing" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
It should be noted that, for convenience of understanding and explanation, only schematic circuit element diagrams, equivalent circuit diagrams, and the like for explaining the present application are given in the exemplary embodiments and the circuit drawings herein, but simplification of the circuit drawings is not intended to exclude other electronic elements that may be required, nor is it intended to limit the present application to the exemplary embodiments.
Herein, unless the context defines otherwise, the term "non-linearity error" includes DNL and INL.
As shown in fig. 1, fig. 1 is a circuit diagram illustrating an application of a method for calibrating the accuracy of a SAR ADC based on a non-linear error according to an embodiment of the present application.
In this embodiment, the periodic oscillation signal 120 and the step-slope signal 110 generated by the non-linear error detection calibration module 500 are respectively input to the positive and negative input terminals of the operational amplifier OPA of the signal superposition module 600, and gain is superposed to obtain the superposed signal 300. For example, the periodic oscillation signal 120 may be an a · sin (ω t) sine wave signal, where a is the amplitude of the sine wave signal, ω is the angular velocity of the sine wave signal 120, and the step climbing signal 110 may be V dac . Thus, the superimposed signal may be 2 · V dac + A·sin(ωt)。
With reference to fig. 1, the superimposed signal 300 is input into the SAR ADC 400, and after analog-to-digital conversion is performed on the sampling signals of the multiple sampling points, M-bit digital signals are obtained through conversion, and each bit of digital signal is transmitted to the nonlinear error detection and calibration module 500, so as to implement nonlinear error (for example, DNL) calculation of the SAR ADC 400. Since the non-linear error detection calibration module generates the step-climbing signal 110 and receives the output signal fed back by the SAR ADC 400 at the same time, the non-linear error caused by the SAR ADC 400 can be calculated more accurately.
Therefore, it is noted that the non-linear error detection calibration module 500 is configured to have a detection portion and a calibration portion. The detection part comprises the steps that digital codes represented by direct current signals are generated in the first step, output to a digital-to-analog converter and converted into analog direct current signals, and the analog direct current signals are superposed with periodic oscillation signals 120 through a signal superposition module 600; and the second step is to perform code density statistics on the digital signals output by the SAR ADC 400 and calculate DNL and/or INL of the ADC 400. The calibration portion includes adjusting the ADC 400 internal calibration parameters based on DNL and/or INL errors.
It is understood that for the superimposed signal generated by the N-bit staircase ramp signal, N M-bit digital signals may be output to the non-linear error detection calibration module 500 during the calibration process.
With continued reference to fig. 1, the non-linear error detection calibration module 500 is configured to perform a test analysis on the non-linear error of the SAR ADC 400, i.e., detect the digital signal, and calculate that the calibration signal is sent to the SAR ADC 400 to perform calibration of the capacitance mismatch. In addition, the non-linear error detection calibration module 500 is further configured to generate dc data for the step ramp signal 110 and transmit the dc data to the DAC 200 to generate a step analog dc level signal of the step ramp signal 110 to participate in the superposition to generate the next bit-period oscillator sub-signal. The periodic oscillation signal 120, the step-climbing signal 110, and the superimposed signal 300 will be described in detail in the following embodiments.
As shown in fig. 2, fig. 2 illustrates a SAR ADC 400 of the embodiment of fig. 1. In the illustration, SAR ADC 400 includes a low-order sampling capacitor C 0 ~C L And a high-order sampling capacitor C n0 ~C N . High-order sampling capacitor C n0 ~C N Are respectively connected with a compensation capacitor C n0_trim ~C N_trim . High-order sampling capacitor C n0 ~C N And a compensation capacitor C n0_trim ~C N_trim Is connected to the positive input of the comparator. The negative input end of the comparator is connected with a reference voltage V CM . The output end of the comparator is connected with the logic control circuit of the SAR ADC. The logic control circuit of the SAR ADC is configured to be the logic control of the circuit and comprises a low-order sampling capacitor C 0 ~C L And a high-order sampling capacitor C n0 ~C N And a compensation capacitor C n0_trim ~C N_trim And e.g. compensating capacitor C n0_trim ~C N_trim The compensation capacitance value of (2). In the drawing, V IN Is the input signal, V, of the SAR ADC 400 REFN Is the low reference voltage, V, of the SAR ADC 400 REFP Is the high reference voltage of SAR ADC 400.
Fig. 3 shows a flowchart of a method for calibrating the accuracy of the SAR ADC based on the nonlinear error according to an embodiment of the present application. In this embodiment, the number of bits of the capacitor to be calibrated of the SAR ADC 400 is N, where N is a natural number greater than or equal to 2.
It should be noted that, in this application, the capacitor to be calibrated may include a high-order capacitor (or may be referred to as a high-order segment capacitor, a high-order sampling capacitor, or an MSB capacitor), which refers to a sampling capacitor with a higher weight in analog-to-digital conversion. In one embodiment, high-side capacitance may refer to capacitance above 9 or 10 bits. Those skilled in the art will appreciate that the capacitance calibration is performed at the position of the second stage in different situations, and the description of the present application is omitted.
It should also be noted that in other embodiments, the capacitor to be calibrated may also include a low-side capacitor (or may be referred to as a low-side segment capacitor, a low-side sampling capacitor, or an LSB capacitor). However, when the capacitor to be calibrated is a high-order capacitor, the calibration speed is fastest and the precision after calibration is higher.
In the present embodiment, the method for calibrating the accuracy of the SAR ADC 400 includes the following steps.
Step S100, a nonlinear error detection calibration module generates a step climbing signal, wherein the number of steps of the step climbing signal is the same as the number N of the capacitance bits to be calibrated of the SAR ADC, and the width of the steps of the step climbing signal is related to the sampling rate of the SAR ADC.
Referring to fig. 4, the step ramp signal 110 is a level signal with step-up level, wherein the number of the step-up steps of the step ramp signal 110 is the same as the number N of the capacitance bits to be calibrated of the SAR ADC. For example, when the number of bits of the capacitor to be calibrated of the SAR ADC is 12, the number of rising steps of the step ramp signal 110 is also 12.
It is further noted that the width of each step of the stair-step ramp signal 110 should theoretically be the same, and the width W of each step may be proportional to the sampling rate of the SAR ADC 400, i.e., the larger the sampling rate of the SAR ADC 400, the larger the width W of each step. The sampling rate may be any normal value for SAR ADC 400. In some embodiments, the sampling rate may be the maximum sampling rate of the SAR ADC 400, thereby saving calibration time of the SAR ADC 400.
Step S200, generating a periodic oscillation signal, wherein the SAR ADC has an input offset error, an input noise and an input direct current level error, and the amplitude of the periodic oscillation signal is greater than or equal to the sum of the input offset error, the input noise and the input direct current level error.
The periodic oscillation signal may be any signal that oscillates back and forth periodically. In some embodiments, a sine wave signal may be selected because the generation of the sine wave signal is simple and stable. It is understood that the periodic oscillation signal may be other signals, such as a sawtooth signal and a triangular wave signal, as long as the detection range of the reciprocating oscillation thereof covers the full amplitude range.
The input offset error refers to an error of an input offset voltage of the SAR ADC 400. The input noise is the sum of the noise of the SAR ADC 400 and the noise of the preamplifier and DAC. The input DC level error refers to the sum of errors of output offset voltages of the amplifier and the DAC.
Step S300, the periodic oscillation signal and the step climbing signal are superposed to obtain a superposed signal, wherein the superposed signal is composed of a plurality of periodic oscillation sub-signals respectively corresponding to the number of the to-be-calibrated capacitance bits of the SAR ADC, and the amplitudes of the plurality of periodic oscillation sub-signals are respectively greater than or equal to the amplitudes of the periodic oscillation signal.
In conjunction with fig. 4, fig. 4 shows a waveform diagram of the superimposed signal 300. It is understood that the superimposed signal 300 is formed by superimposing the stair-step climbing signal 110 and the periodic oscillating signal 120. In the waveform diagram, the ordinate is the number of bits of the capacitor to be calibrated, and the abscissa is the sampling rate of the SAR ADC 400. As previously described, the width W of each step is directly proportional to the sampling rate of the SAR ADC 400, i.e., the greater the sampling rate of the SAR ADC 400, the greater the width W of each step. Periodic oscillation signals 120 are respectively superimposed on the steps of the stepped ramp signal 110 to form a ramp signal having a plurality of sinusoidal sub-signal steps, as shown.
Specifically, as shown, SAR ADC 400 is a resolution of 4 bits of capacitance to be calibrated. Accordingly, the superimposed signal 300 is at the capacitance bit number to be calibrated 2 5 、2 6 、2 7 And 2 8 Each having a sine wave sub-signal.
It is to be understood that the embodiment of fig. 4 is for convenience of explanation, and only an example of a 4-bit ADC is illustrated, but the number of bits of the capacitor to be calibrated may be more, for example, 8 bits, 12 bits, or 16 bits.
It should be understood that in the present embodiment, the amplitudes of the sinusoidal sub-signals are the same, but in other embodiments, the amplitudes of the sinusoidal sub-signals may be different as long as the amplitudes of the sinusoidal sub-signals are greater than or equal to the amplitude of the periodic oscillation signal 120, that is, greater than or equal to the amplitude of the periodic oscillation signal.
In step S400, the SAR ADC receives a first periodic oscillator sub-signal of a plurality of periodic oscillator sub-signals of the superimposed signal, samples the first periodic oscillator sub-signal at a plurality of sampling signal points to obtain a first sampling signal capacitance value, and sends the first sampling signal capacitance value to a non-linear error detection calibration module connected to the SAR ADC.
In conjunction with fig. 5, fig. 5 shows a schematic diagram of a first periodic oscillator sub-signal of a sine wave signal 120 as a periodic oscillator signal. In this embodiment it can be seen that the periodic oscillator sub-signal is not in the 2-bit number due to the presence of non-linearity errors, input offset errors, input noise and input dc level errors 5 But rather oscillates at the off-set position D, i.e. the measured actual capacitance value to be calibrated. Based on the deviation position and the number of bits 2 5 The non-linear error of the SAR ADC can be calculated by the Offset value Offset.
Specifically, sampling is performed on a plurality of sampling signal points on the first periodic oscillator sub-signal to obtain a first sampling signal capacitance value corresponding to the first periodic oscillator sub-signal, and the sampling signal capacitance value is sent to the nonlinear error detection calibration module for test analysis.
Step S500, the nonlinear error detection calibration module calculates a corresponding first nonlinear error of the first periodic oscillator sub-signal according to the step climbing signal and the first sampling signal capacitance value, and compares the first nonlinear error with a preset nonlinear error threshold to obtain a comparison result, wherein the preset nonlinear error threshold is inversely related to the number of sampling points of the SAR ADC.
The first periodic oscillator sub-signal corresponds to the number of bits of the capacitor to be calibrated and also corresponds to the first nonlinear error, i.e. the first nonlinear error. For example, 2 5 The number of the capacitor bits to be calibrated corresponds to the first cycleThe periodic oscillator sub-signal also corresponds to the first non-linear error. It will be appreciated that each capacitance bit to be calibrated corresponds to a non-linear error.
It is understood that the method for calculating the non-linear error is a common method in the art, for example, DNL or INL calculation performed by an analysis program of Matlab based on a sine wave Histogram code density Test (for linear), and those skilled in the art should know how to calculate the non-linear error, and the description of the method is omitted here.
Step S600, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends a calibration signal to the SAR ADC to calibrate the capacitance of the first sampling signal, so that the first nonlinear error is less than the preset nonlinear error threshold.
Specifically, when the first nonlinear error is greater than the preset nonlinear error threshold, that is, when the actual nonlinear error (for example, the actual DNL) exceeds the undesired range, the nonlinear error detection calibration module 500 controls the compensation capacitance value, and finally, the actual nonlinear error falls into the desired range, so as to achieve the calibration purpose.
Step S700, when the comparison result indicates that the first non-linear error is less than or equal to the preset non-linear error threshold, repeating steps S400, S500, and S600 for a next periodic oscillator sub-signal of the first periodic oscillator sub-signal until all the periodic oscillator sub-signals are calibrated.
After the nonlinear error calibration of the first capacitor bit number to be calibrated is completed, the subsequent nonlinear error calibration of the capacitor bit number to be calibrated is sequentially executed until the nonlinear error calibration of all the capacitor bit numbers to be calibrated is completed.
With the above-described embodiment of the present application, in combination with the step climbing signal 110 and the periodic oscillation signal 120, a small-amplitude periodic oscillation signal is superimposed at the level on the common-mode signal of each step (step climbing signal), for each 2 1 To 2 N +1 And a non-linear error test (for example, a DNL test) is carried out near each code (for example, in the amplitude of a sine wave signal), so that high-precision test is realized, the test speed is ensured, and an expensive high-precision ramp signal generator is not required to be used, so that the cost is reduced.
In one embodiment, the SAR ADC 400 is disposed on-chip and the non-linear error detection calibration module 500 is disposed outside of the chip. The non-linear error detection calibration module 500 is disposed outside the SAR ADC 400 to detect and calculate the non-linear error of the ADC 400, which can be configured by higher performance software and/or hardware (e.g., histogram statistical analysis by Matlab analysis software or hardware circuits such as a single chip, FGPA, or ACSC), so as to improve the monitoring and calculation accuracy of the non-linear error detection calibration module 500, and can reduce hardware on chip and chip area.
Fig. 6 shows a flowchart of a method for calibrating the accuracy of sar adc based on non-linear error according to another embodiment of the present application. In this embodiment, the calibration signal includes an offset error calibration step value, and the offset error calibration step value is:
whereinE NL for the pre-set non-linear error threshold,S trim step values are calibrated for the misalignment error.
The step of sending the calibration signal to the SAR ADC by the nonlinear error detection calibration module 500 to adjust the capacitance of the first sampling signal so that the first nonlinear error is smaller than the preset nonlinear error threshold specifically includes the following steps.
Step S610, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends the calibration signal to the SAR ADC, so as to calibrate the first nonlinear error by reducing the offset error calibration step value for the absolute value of the capacitance value of the first sampling signal.
In this embodiment, the non-linear error detection calibration module 500 determines the value of the offset error calibration step value according to the value range of the preset non-linear error threshold, so as to adjust (or compensate) the capacitance value of the first sampling signal by using the offset error calibration step value, that is, the actual capacitance value of the capacitor to be calibrated, thereby achieving the purpose of reducing the non-linear error.
For example, when the predetermined non-linear error threshold is 0.4 LSB, the offset error calibration step value is 0.8 LSB. When the capacitance value of the first sampling signal is 0.5 LSB, the non-linear error detection calibration module 500 sends out a calibration signal, so that the offset error calibration step value is subtracted from the capacitance value of the first sampling signal, i.e. 0.5 LSB to 0.8 LSB, and a new capacitance value of the first sampling signal is-0.3 LSB, at this time, the absolute value of the capacitance value of the first sampling signal is 0.3 LSB, which is smaller than the preset non-linear error threshold, and the calibration is completed.
Due to the arrangement of the method, the offset error calibration stepping value is kept to be maximum under any condition, and the calibration stepping times are reduced, so that the calibration speed is greatly improved.
Fig. 7 shows a flowchart of a method for precision calibration of sar adc based on non-linearity error according to another embodiment of the present application. In this embodiment, the step of sending the calibration signal to the SAR ADC by the calibration module 500 for adjusting the capacitance of the first sampling signal so that the first non-linear error is smaller than the preset non-linear error threshold specifically includes the following steps.
Step S620, set the offset error calibration step value to 0.5 LSB.
The offset error calibration step value is initially 0.5 LSB.
Step S630, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends the calibration signal to the SAR ADC, so as to obtain a calibrated sampling signal capacitance value by reducing the offset error calibration step value by the absolute value of the first sampling signal capacitance value, wherein when the absolute value of the calibrated sampling signal capacitance value is less than the offset error calibration step value and is greater than or equal to the preset nonlinear error threshold, the offset error calibration step value is halved, and the step S630 is repeated.
Specifically, for example, the offset error calibration step value is initially 0.5 LSB, the preset non-linear error threshold is 0.2 LSB, and the first sampling signal capacitance value is 0.9 LSB, and since the absolute value of the first sampling signal capacitance value is greater than the preset non-linear error threshold, the first calibration is performed, that is, the offset error calibration step value 0.5 LSB is subtracted from the absolute value of the first sampling signal capacitance value 0.9 LSB, so as to obtain the first sampling signal capacitance value 0.4 LSB after the first calibration. Because the capacitance value of the first sampling signal after the first calibration is greater than the preset non-linear error threshold value, the second calibration is performed, and because the capacitance value of the first sampling signal after the first calibration does not change sign, the offset error calibration step value is still 0.5 LSB, the capacitance value of the first sampling signal after the first calibration minus the offset error calibration step value is obtained, the capacitance value of the first sampling signal after the second calibration is-0.1 LSB, at this moment, the absolute value of the capacitance value of the first sampling signal is smaller than the preset non-linear error threshold value, and the calibration is finished.
For another example, the offset error calibration step value is initially 0.5 LSB, the preset non-linear error threshold value is 0.2 LSB, and the first sampling signal capacitance value is 0.75 LSB, and since the absolute value of the first sampling signal capacitance value is greater than the preset non-linear error threshold value, the first calibration is performed, that is, the offset error calibration step value 0.5 LSB is subtracted from the absolute value of the first sampling signal capacitance value 0.75 LSB, so as to obtain the first calibrated sampling signal capacitance value 0.25 LSB. The capacitance value of the first sampling signal after the first calibration is larger than the preset non-linear error threshold value, so the second calibration is performed, and since the capacitance value of the first sampling signal after the first calibration does not change sign, the offset error calibration step value is still 0.5 LSB, the absolute value of the capacitance value of the first sampling signal after the first calibration minus the offset error calibration step value obtains the capacitance value of the first sampling signal after the second calibration as-0.25 LSB, at this time, the absolute value of the capacitance value of the first sampling signal is still larger than the preset non-linear error threshold value, the calibration continues, meanwhile, since the sign change occurs after the second calibration of the capacitance of the first sampling signal (positive 0.25 LSB is changed into-0.25 LSB), the offset error calibration step value is halved and is changed from 0.5 LSB to 0.25 LSB, at this time, the absolute value of the capacitance value of the first sampling signal after the first sampling signal capacitance value 0.25 LSB minus the offset error calibration step value 0.25 LSB obtains the first sampling signal after the third calibration, and the calibration is finished.
The step value taking method for offset error calibration in the above embodiment further improves the accuracy by gradually converging the step length, and also ensures a certain convergence rate.
In other embodiments, the offset error calibration step value may also be a fixed value, such as one of 0.1 LSB, 0.2 LSB, 0.3 LSB. The method adopts small steps to calibrate, so that the calibration accuracy is further improved.
In an embodiment, the predetermined non-linear error threshold is calculated by the following formula:
wherein, E NL For the predetermined non-linear error threshold, k is a proportionality constant, S N The number of sampling points of the SAR ADC.
In an embodiment, the number of sampling points is positively correlated with the number of capacitance bits to be calibrated of the SAR ADC; the calculation formula of the sampling point number is as follows:
whereinS N and N is the number of the sampling points of the SAR ADC, and N is the number of the capacitance bits to be calibrated of the SAR ADC.
Referring to fig. 8, fig. 8 shows a logic control diagram of a method for calibrating the accuracy of a SAR ADC based on a non-linearity error according to an embodiment of the present application.
Specifically, when calibration is started, it is determined whether the calibration enable symbol LOCK is 0, and if so, the calibration procedure is started, otherwise, the calibration procedure is exited. Calibration is initiated by SPI (Serial Peripheral Interfa)ce) protocol configures the register so that the calibration step symbol TRIM _ EN is 1, i.e. step calibration is started and the iteration counter i =1 is set. Setting the input AC signal (i.e., periodic oscillation signal) amplitude of the ADC to V ref /[2 x ]. It will be appreciated that V is as previously described ref /[2 x ]The value of x is not particularly limited as long as the condition is satisfied, and the value is equal to or greater than the sum of the input offset error, the input noise, and the input dc level error.
Setting the input DC signal amplitude of ADC to V ref /[2 (N+1-i) ]. Configuring ADC to work normally, and sampling the superposed signal of the capacitance digit to be calibrated, wherein the sampling point is 2 N The non-linear error detection calibration module 500 calculates an actual DNL value (corresponding to the sampled signal capacitance), and adjusts the actual DNL value by adjusting the offset error calibration step value according to the comparison between the sampled signal capacitance and a predetermined non-linear error threshold (here, 0.5 LSB). When the absolute value of the actual DNL is smaller than a preset non-linear error threshold, the counter i = i +1. When the absolute value of the actual DNL is larger than or equal to the preset nonlinear error threshold, inputting a stepping value (Trim value) of the ith bit capacitor through the SPI protocol, and resampling and calculating the DNL until the absolute value of the actual DNL is smaller than the preset nonlinear error threshold.
As shown in fig. 9, exemplary embodiments of the present application also provide a non-linear error based precision calibration apparatus for a SAR ADC, which includes a signal generation module 100, a signal superposition module 600, a SAR ADC 400, and a non-linear error detection calibration module 500.
The signal generation module 100 is configured to generate a periodic oscillating signal, wherein the SAR ADC has an input offset error, an input noise, and an input dc level error, and an amplitude of the periodic oscillating signal is greater than or equal to a sum of the input offset error, the input noise, and the input dc level error.
The non-linear error detection calibration module 500 times is configured to generate a step climbing signal, wherein the number of steps of the step climbing signal is the same as the number N of bits of the capacitor to be calibrated of the SAR ADC 400, and the width of the steps of the step climbing signal is related to the sampling rate of the SAR ADC 400.
The signal superimposing module 600 is configured to superimpose the periodic oscillation signal and the step climbing signal to obtain a superimposed signal, where the superimposed signal is composed of a plurality of periodic oscillation sub-signals respectively corresponding to the number of bits of the capacitor to be calibrated of the SAR ADC, and amplitudes of the plurality of periodic oscillation sub-signals are respectively greater than or equal to the amplitudes of the periodic oscillation signal.
The non-linear error detection calibration module 500 is further configured to receive the first sampled signal capacitance value from the SAR ADC 400, calculate a corresponding first non-linear error of the first periodic oscillator sub-signal according to the step ramp signal and the first sampled signal capacitance value, and compare the first non-linear error with a preset non-linear error threshold value to obtain a comparison result, wherein the preset non-linear error threshold value is inversely related to the number of sampling points of the SAR ADC.
When the comparison result is that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends a calibration signal to the SAR ADC to calibrate the capacitance value of the first sampling signal so that the first nonlinear error is less than the preset nonlinear error threshold; and when the comparison result is that the first nonlinear error is less than or equal to the preset nonlinear error threshold, repeatedly executing a calibration step for a next periodic oscillator sub-signal of the first periodic oscillator sub-signal.
With continued reference to fig. 9, the signal generation module 100 generates the periodic oscillation signal 120 and the stair climbing signal 110 and sends the two signals to the signal superposition module 600. The signal superposition module 600 superposes the periodic oscillation signal 120 and the step climbing signal 110 to generate a periodic oscillator sub-signal oscillating around a corresponding bit number of the SAR ADC. Each periodic oscillator sub-signal is respectively transmitted to the SAR ADC 400, converted and then transmitted to the nonlinear error detection calibration module 500 for DNL calculation, compared with a preset nonlinear error threshold, and fed back to control the compensation capacitor in the SAR ADC 400 according to the comparison result, so as to compensate the capacitor to be calibrated in the SAR ADC 400, thereby achieving the effect of reducing the nonlinear error. The non-linear error detection calibration module 500 is further configured to send the digital signal to the DAC 200, thereby regenerating the next bit analog reference signal to the signal superposition module 600, further performing the non-linear error calibration of the next bit.
In an embodiment, the non-linear error detection calibration module 500 and the digital-to-analog converter 200 connected to the non-linear error detection calibration module 500 may be disposed outside the chip. Therefore, only the chip is required to be externally connected during chip calibration, and the area in the chip is not required to be occupied.
The precision calibration device of the SAR ADC based on the nonlinear error provided by the present application is configured as the precision calibration method provided by each exemplary embodiment of the present application, and therefore all features and limitations of the precision calibration method in the present application are also applicable to the precision calibration device, and are not described herein again.
It should be understood that although the various steps in the flowcharts of fig. 3, 6 and 7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least some of the steps in fig. 3, 6, and 7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternatingly with other steps or at least some of the sub-steps or stages of other steps.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (14)
1. A precision calibration method of a SAR ADC based on nonlinear error is characterized in that the number of capacitance bits to be calibrated of the SAR ADC is N, wherein N is a natural number greater than or equal to 2, and the method comprises the following steps:
step S100, a step climbing signal is generated by a nonlinear error detection calibration module, wherein the number of steps of the step climbing signal is the same as the number N of capacitance bits to be calibrated of the SAR ADC, and the width of the steps of the step climbing signal is related to the sampling rate of the SAR ADC;
step S200, generating a periodic oscillation signal, wherein the SAR ADC has an input offset error, an input noise and an input direct current level error, and the amplitude of the periodic oscillation signal is greater than or equal to the sum of the input offset error, the input noise and the input direct current level error;
step S300, superposing the periodic oscillation signal and the step climbing signal to obtain a superposed signal, wherein the superposed signal is composed of a plurality of periodic oscillation sub-signals respectively corresponding to the capacitance number to be calibrated of the SAR ADC, and the amplitudes of the plurality of periodic oscillation sub-signals are respectively greater than or equal to the amplitudes of the periodic oscillation signals;
step S400, the SAR ADC receives a first periodic oscillator sub-signal of the plurality of periodic oscillator sub-signals of the superimposed signal, samples the first periodic oscillator sub-signal at a plurality of sampling signal points to obtain a first sampling signal capacitance value, and sends the first sampling signal capacitance value to the nonlinear error detection calibration module connected to the SAR ADC;
step S500, the nonlinear error detection calibration module calculates a corresponding first nonlinear error of the first periodic oscillator sub-signal according to the step climbing signal and the capacitance value of the first sampling signal, and compares the first nonlinear error with a preset nonlinear error threshold to obtain a comparison result, wherein the preset nonlinear error threshold is inversely related to the number of sampling points of the SAR ADC;
step S600, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends a calibration signal to the SAR ADC to calibrate the capacitance value of the first sampling signal, so that the first nonlinear error is smaller than the preset nonlinear error threshold; and
step S700, when the comparison result indicates that the first non-linear error is less than or equal to the preset non-linear error threshold, repeating steps S400, S500, and S600 for a next periodic oscillator sub-signal of the first periodic oscillator sub-signal until all the periodic oscillator sub-signals are calibrated.
2. The method for calibrating the accuracy of the SAR ADC based on the non-linear error of claim 1, wherein the periodic oscillating signal is a sine wave signal and the plurality of periodic oscillating sub-signals are a plurality of sine wave sub-signals.
3. The method for calibrating the accuracy of a non-linear error based SAR ADC of claim 2, wherein the SAR ADC is disposed within a chip, and the non-linear error detection calibration module is disposed outside the chip.
4. The method for calibrating the accuracy of a non-linear error-based SAR ADC according to claim 3, wherein the non-linear error detection calibration module further has an output terminal connected to a digital-to-analog converter disposed outside the chip, the output terminal outputting N-bit digital signals to the digital-to-analog converter to sequentially generate the step-ramp signal.
5. The method of claim 3, wherein the calibration signal comprises an offset error calibration step value, and the offset error calibration step value is:
wherein,E NL for the pre-set non-linear error threshold,S trim calibrating a step value for the misalignment error;
the step S600 includes:
step S610, when the comparison result indicates that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends the calibration signal to the SAR ADC, so as to calibrate the first nonlinear error by reducing the offset error calibration step value for the absolute value of the capacitance value of the first sampling signal.
6. The method for calibrating the accuracy of a non-linear error based SAR ADC of claim 3, wherein the calibration signal comprises an offset error calibration step value, the step S600 comprises:
step S620, setting the offset error calibration stepping value to be 0.5 LSB;
step S630, when the comparison result is that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends the calibration signal to the SAR ADC to obtain a calibrated sampling signal capacitance value by reducing the offset error calibration step value by the absolute value of the first sampling signal capacitance value,
when the absolute value of the calibrated sampling signal capacitance value is smaller than the step value of the offset error calibration and is greater than or equal to the preset nonlinear error threshold value, the step value of the offset error calibration is halved, and the step S630 is repeated.
7. The method for accuracy calibration of a non-linear error based SAR ADC of claim 3, wherein the calibration signal comprises an offset error calibration step value, the offset error calibration step value is a fixed value, the fixed value is one of 0.1 LSB, 0.2 LSB, 0.3 LSB.
8. The method for calibrating the accuracy of a SAR ADC based on nonlinear errors as recited in any one of claims 2 to 7, wherein the step of calculating the corresponding first nonlinear error of the first periodic oscillator sub-signal according to the stair-climbing signal and the first sampling signal capacitance value by the nonlinear error detection calibration module is based on a sine wave histogram code density test.
9. The method for calibrating the accuracy of a SAR ADC based on non-linear errors according to any of claims 1 to 7, wherein the non-linear error is an integral non-linear error or a differential non-linear error.
10. The method for calibrating the accuracy of the SAR ADC based on the nonlinear error as recited in any one of claims 1 to 7, wherein the preset nonlinear error threshold is calculated by the following formula:
wherein,E NL for the pre-set non-linear error threshold,kis a constant of proportionality that is,S N the number of sampling points of the SAR ADC.
11. The method for calibrating the precision of the SAR ADC based on the nonlinear error as recited in any one of claims 1 to 7, wherein the number of sampling points of the SAR ADC is positively correlated with the number of capacitance bits to be calibrated of the SAR ADC; the calculation formula of the sampling points of the SAR ADC is as follows:
wherein,S N and N is the number of the sampling points of the SAR ADC, and N is the number of the capacitance bits to be calibrated of the SAR ADC.
12. The method for calibrating the precision of a non-linearity error based SAR ADC according to any one of claims 1 to 7, wherein the number of capacitance bits N to be calibrated ranges from 2 to 16.
13. A precision calibration device of a SAR ADC based on nonlinear error is characterized in that the number of capacitance bits to be calibrated of the SAR ADC is N, wherein N is a natural number greater than or equal to 2, and the precision calibration device comprises:
a signal generation module configured to generate a periodic oscillating signal, wherein the SAR ADC has an input offset error, an input noise, and an input DC level error, and an amplitude of the periodic oscillating signal is greater than or equal to a sum of the input offset error, the input noise, and the input DC level error;
a nonlinear error detection calibration module configured to generate a step climbing signal, wherein the number of steps of the step climbing signal is the same as the number of bits N of the capacitor to be calibrated of the SAR ADC, and the width of the steps of the step climbing signal is related to the sampling rate of the SAR ADC;
a signal superposition module configured to superpose the periodic oscillation signal and the step climbing signal to obtain a superposed signal, wherein the superposed signal is composed of a plurality of periodic oscillation sub-signals respectively corresponding to the number of the capacitance bits to be calibrated of the SAR ADC, and amplitudes of the plurality of periodic oscillation sub-signals are respectively greater than or equal to the amplitude of the periodic oscillation signal; and
the SAR ADC configured to receive a first periodic oscillator sub-signal of a plurality of periodic oscillator sub-signals of the superimposed signal, the first periodic oscillator sub-signal sampled at a plurality of sampling signal points to obtain a first sampled signal capacitance value;
wherein the non-linear error detection calibration module is further configured to receive the first sampled signal capacitance value from the SAR ADC, calculate a corresponding first non-linear error of the first periodic oscillator sub-signal according to the step ramp signal and the first sampled signal capacitance value, and compare the first non-linear error with a preset non-linear error threshold value to obtain a comparison result, wherein the preset non-linear error threshold value is inversely related to the number of sampling points of the SAR ADC;
when the comparison result is that the first nonlinear error is greater than the preset nonlinear error threshold, the nonlinear error detection calibration module sends a calibration signal to the SAR ADC to calibrate the capacitance value of the first sampling signal so that the first nonlinear error is less than the preset nonlinear error threshold; and
and when the comparison result shows that the first nonlinear error is smaller than or equal to the preset nonlinear error threshold, repeatedly executing the calibration step aiming at a next periodic oscillator sub-signal of the first periodic oscillator sub-signal.
14. The apparatus of claim 13, wherein the SAR ADC is disposed within a chip and the nonlinear error detection calibration module is disposed outside the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211690383.0A CN115664418B (en) | 2022-12-28 | 2022-12-28 | SAR ADC precision calibration method and device based on nonlinear error |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211690383.0A CN115664418B (en) | 2022-12-28 | 2022-12-28 | SAR ADC precision calibration method and device based on nonlinear error |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115664418A CN115664418A (en) | 2023-01-31 |
| CN115664418B true CN115664418B (en) | 2023-02-28 |
Family
ID=85022503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211690383.0A Active CN115664418B (en) | 2022-12-28 | 2022-12-28 | SAR ADC precision calibration method and device based on nonlinear error |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115664418B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102859882A (en) * | 2010-04-22 | 2013-01-02 | 德州仪器公司 | Successive approximation register analog-to-digital converter with integral non-linearity correction |
| CN108988860A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of calibration method and SAR ADC system based on SAR ADC |
| CN111555603A (en) * | 2020-06-22 | 2020-08-18 | 无锡英迪芯微电子科技股份有限公司 | Self-calibration soft start circuit of buck converter |
| CN111800131A (en) * | 2019-04-03 | 2020-10-20 | 半导体元件工业有限责任公司 | Calibration circuit and method for calibrating ADC output codes from a set of analog-to-digital converters |
| CN113037283A (en) * | 2019-12-09 | 2021-06-25 | 中兴通讯股份有限公司 | Time-interleaved successive approximation type analog-to-digital converter and calibration method thereof |
-
2022
- 2022-12-28 CN CN202211690383.0A patent/CN115664418B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102859882A (en) * | 2010-04-22 | 2013-01-02 | 德州仪器公司 | Successive approximation register analog-to-digital converter with integral non-linearity correction |
| CN108988860A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of calibration method and SAR ADC system based on SAR ADC |
| CN111800131A (en) * | 2019-04-03 | 2020-10-20 | 半导体元件工业有限责任公司 | Calibration circuit and method for calibrating ADC output codes from a set of analog-to-digital converters |
| CN113037283A (en) * | 2019-12-09 | 2021-06-25 | 中兴通讯股份有限公司 | Time-interleaved successive approximation type analog-to-digital converter and calibration method thereof |
| CN111555603A (en) * | 2020-06-22 | 2020-08-18 | 无锡英迪芯微电子科技股份有限公司 | Self-calibration soft start circuit of buck converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115664418A (en) | 2023-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6563445B1 (en) | Self-calibration methods and structures for pipelined analog-to-digital converters | |
| US8451151B2 (en) | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof | |
| US7501965B2 (en) | Correcting for errors that cause generated digital codes to deviate from expected values in an ADC | |
| US6897794B2 (en) | All-analog calibration of sting-DAC linearity: application to high voltage processes | |
| US7378999B1 (en) | Method and apparatus for digital calibration of an analog-to-digital converter | |
| TWI509997B (en) | Data conversion circuitry and method therefor | |
| US20020014982A1 (en) | A/D converter calibration | |
| US20160079995A1 (en) | Error Measurement and Calibration of Analog to Digital Converters | |
| US20140097975A1 (en) | Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same | |
| US9432041B2 (en) | Method of calibrating a thermometer-code SAR A/D converter and thermometer-code SAR-A/D converter implementing said method | |
| US20090085785A1 (en) | Digital-to-analog converter calibration for multi-bit analog-to-digital converters | |
| FI86120B (en) | A / D- ELLER D / A-OMVANDLARE, A / D- ELLER D / A-OMVANDLARSYSTEM SAMT KALIBRERINGSFOERFARANDE FOER DESSA. | |
| TW201310918A (en) | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof | |
| TW201916595A (en) | Analog to digital conversion apparatus and analog to digital converter calibration method of the same | |
| JP4947899B2 (en) | Digital correction integrated circuit and digital-analog converter (DAC) | |
| CN115664418B (en) | SAR ADC precision calibration method and device based on nonlinear error | |
| US10484001B1 (en) | Multi-bit successive-approximation register analog-to-digital converter | |
| US11075644B2 (en) | Efficient all-digital domain calibration architecture for a successive approximation register analog-to-digital converter | |
| US11038517B1 (en) | Multiplying digital-to-analog converter (MDAC) with nonlinear calibration | |
| Lopez-Angulo et al. | Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy | |
| CN109600139B (en) | Analog-to-digital conversion device and analog-to-digital converter correction method thereof | |
| KR102052728B1 (en) | An apparatus and method of ADC range expansion | |
| Parthasarathy et al. | Accurate self characterization and correction of A/D converter performance | |
| Lyu et al. | An in situ digital background calibration algorithm for multi-channel r-βr ladder dacs | |
| Aswin | New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |