CN115640249A

CN115640249A - Server control system

Info

Publication number: CN115640249A
Application number: CN202110811601.0A
Authority: CN
Inventors: 李韦薇
Original assignee: Kunda Computer Technology Kunshan Co Ltd; Mitac Computing Technology Corp
Current assignee: Kunda Computer Technology Kunshan Co Ltd; Mitac Computing Technology Corp
Priority date: 2021-07-19
Filing date: 2021-07-19
Publication date: 2023-01-24

Abstract

A server control system is applied to update firmware data of a management engine of a platform path controller. The platform path controller has an HDA _ SDO pin. The server control system comprises a management and control unit connected with the HDA _ SDO pin and a Super I/O connected with the management and control unit. The control unit includes a switch circuit module. The Super I/O comprises a control pin connected with the management and control unit. The control pin of the Super I/O sends a second control signal to the control unit in a controlled manner, and after the control signal is operated by the switch circuit module, the control unit generates a high level and transmits the high level to the HDA _ SDO pin, at the moment, the HDA _ SDO pin is at the high level, so that the firmware data of the management engine can be updated and overwritten, the level of the HDA _ SDO pin can be pulled up without using an external Jumper, and the time is effectively saved.

Description

Server control system

[ technical field ] A

The present invention relates to a server, and more particularly, to a server control system.

[ background of the invention ]

The Management Engine (ME) proposed by Intel can provide server power Management and peripheral function Management, and the platform Path Controller (PCH) of Intel is commonly configured to apply the Management Engine. Generally, under normal conditions, the management engine is in the protection mode, so the firmware data of the management engine cannot be modified and updated, and the HDA _ SDO pin of the platform path controller is preset to be at a low level, so that the management engine is in the protection mode and the protected firmware data cannot be updated.

However, since the firmware data of the Management Engine (ME) needs to be updated and maintained, when the firmware data of the Management Engine (ME) is to be updated, the protection mechanism of the management engine needs to be released by pulling up the level of the HDA _ SDO pin of the platform path controller by using the external Jumper and making the HDA _ SDO pin in a high level state, and at this time, the firmware data of the management engine can be updated. However, in the manual mode of manually connecting the Jumper externally, each time the firmware data is updated, the user needs to manually insert the Jumper in a troublesome manner, and the Jumper needs to be pulled out after the update is completed to perform the subsequent operation, which is inconvenient and causes trouble to the user, and wastes time, and thus, the user needs to research, study and improve greatly.

[ summary of the invention ]

The invention aims to provide a server control system convenient to update.

To solve the above technical problem, the server control system of the present invention is applied to update a firmware data of a Management Engine (ME) of a platform Path Controller (PCH). The platform path controller has an HDA _ SDO pin. The server control system comprises a management and control unit connected with an HDA _ SDO pin of the platform path controller and a Super I/O connected with the management and control unit.

The control unit comprises a switch circuit module, an input end connected with the switch circuit module, and an output end connected with the switch circuit module and an HDA _ SDO pin of the platform path controller.

The Super I/O comprises a control pin connected with the input end of the control unit. The input end of the control unit is connected with the switch circuit module and the control pin of the Super I/O. The control pin of the Super I/O can be controlled to send out a first control signal and a second control signal. Sending the first control signal to the input end of the control unit by the control pin, and generating a low level from the output end after the control signal is operated by the switch circuit module and is transmitted to the HDA _ SDO pin of the platform path controller, wherein at the moment, the HDA _ SDO pin is the low level and makes the firmware data of the Management Engine (ME) in a protection mechanism and can not be changed; the control pin sends the second control signal to the input terminal of the management control unit and after the control pin is operated by the switch circuit module, the control pin generates a high level from the output terminal of the management control unit and sends the high level to the HDA _ SDO pin of the platform path controller, and at this time, the HDA _ SDO pin is the high level, so that the firmware data of the Management Engine (ME) can be updated.

Compared with the prior art, the invention has the advantages that the switch circuit module of the control unit can receive the design of the signal sent by the Super I/O from the input end, and the switch circuit module generates the high level from the output end and transmits the high level to the application of the HDA _ SDO pin of the platform path controller after receiving the second control signal, so that the HDA _ SDO pin is in the high level state, the firmware data of the Management Engine (ME) can be updated and overwritten, the level of the HDA _ SDO pin can be pulled up without using an additional manual external Jumper mode, and the time is effectively saved.

[ description of the drawings ]

Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating an embodiment of a server control system according to the present invention.

[ detailed description ] embodiments

Referring to fig. 1, the embodiment of the server control system according to the present invention is applied to update a firmware data (not shown) of a management engine 61 (ME) of a platform path controller 6 (PCH). The platform path controller 6 has an HDA _ SDO pin 62. The server control system comprises a processing unit 1 connected with the platform path controller 6, a basic input/output unit 2 connected with the platform path controller 6, a management and control unit 3 connected with an HDA _ SDO pin 62 of the platform path controller 6, and a Super I/O4 connected with the management and control unit 3.

The BIOS 2 includes an execution module 21 and a setting parameter (not shown) corresponding to the Super I/O4. In the embodiment, the basic input/output unit 2 (BIOS) is stored in a Flash Memory (Flash Memory) as shown in fig. 1, but not limited thereto.

The management and control unit 3 includes a switch circuit module 33, an input terminal 31 connected to the switch circuit module 33, and an output terminal 32 connected to the switch circuit module 33 and the HDA _ SDO pin 62 of the platform path controller 6.

The Super I/O4 comprises a control pin 41 connected to the input terminal 31 of the policing unit 3, and an LPC bus 42 linked to the platform path controller 6. In this embodiment, the control pin 41 of the Super I/O4 is a GPIO pin. The input terminal 31 of the management and control unit 3 is connected to the switch circuit module 33 and the control pin 41 of the Super I/O4. The control pin 41 of the Super I/O4 can be controlled to send out a first control signal and a second control signal. After the control pin 41 sends the first control signal to the input terminal 31 of the management control unit 3 and runs through the switch circuit module 33, a low level is generated from the output terminal 32 and is transmitted to the HDA _ SDO pin 62 of the platform path controller 6, at this time, the HDA _ SDO pin 62 is at the low level and the firmware data of the management engine 61 is in a protection mechanism and cannot be changed. After the control pin 41 sends the second control signal to the input terminal 31 of the management control unit 3 and the switch circuit module 33 is operated, a high level is generated from the output terminal 32 and is transmitted to the HDA _ SDO pin 62 of the platform path controller 6, and at this time, the HDA _ SDO pin 62 is at the high level, so that the firmware data of the management engine 61 can be updated.

When the server control system is powered on, the processing unit 1 receives and executes the execution module 21 of the bios 2 via the platform path controller 6 and reads the setting parameters. When the processing unit 1 reads that the setting parameter is a first bit value, the processing unit 1 controls the control pin 41 of the Super I/O4 to send the first control signal to the input terminal 31 of the management and control unit 3, and after the operation of the switch circuit module 33, the processing unit 1 generates the low level from the output terminal 32 of the management and control unit 3 and transmits the low level to the HDA _ SDO pin 62 of the platform path controller 6, at this time, the HDA _ SDO pin 62 is the low level, so that the firmware data of the management engine 61 is in a protection mechanism and cannot be changed, and the processing unit 1 completes the execution of the execution module 21 of the basic input and output unit 2 to perform a boot operation; when the processing unit 1 reads that the setting parameter is a second bit value, the processing unit 1 controls the control pin 41 of the Super I/O4 to send the second control signal to the input terminal 31 of the management and control unit 3, and after the operation of the switch circuit module 33, the processing unit 1 generates the high level from the output terminal 32 of the management and control unit 3 and transmits the high level to the HDA _ SDO pin 62, and at this time, the HDA _ SDO pin 62 is at the high level, so that the firmware data of the management engine 61 can be updated. That is, when the user turns on the server control system, the processing unit 1 executes the execution module 21 of the bios 2 and reads the setting parameter corresponding to the Super I/O4, when the first bit value is read, it represents that the update and overwrite operation of the firmware data of the management engine 61 is not required, and the processing unit 1 controls the control pin 41 of the Super I/O4 to send the first control signal to the input terminal 31 of the management and control unit 3 and to be operated by the switch circuit module 33, and generates the low level from the output terminal 32, and since the HDA _ SDO pin 62 of the platform path controller 6 is connected to the output terminal 32, the HDA _ SDO pin 62 is in the low level state, so that the firmware data of the management engine 61 is in the protection mechanism and cannot be changed, and the processing unit 1 completes the execution of the execution module 21 of the bios 2 to turn on the server. In contrast, when the processing unit 1 reads the second bit value, it represents that the firmware data of the management engine 61 needs to be updated, and the processing unit 1 controls the control pin 41 of the Super I/O4 to send the second control signal to the input terminal 31 of the management unit 3 and to generate the high level from the output terminal 32 of the management unit 3 after the operation of the switch circuit module 33, and since the HDA _ SDO pin 62 is connected to the output terminal 32, the HDA _ SDO pin 62 is in the high level state and the firmware data of the management engine 61 can be updated.

In the present embodiment, the first bit value of the setting parameter of the basic input/output cell 2 is "1", and the second bit value is "0", but the present invention is not limited thereto. In detail, in a general case, the firmware data of the management engine 61 is in a protection mechanism and cannot be changed, so the Default value (Default) of the setting parameter is "1" as the first bit value. When the firmware data overwriting the management engine 61 needs to be updated, when the server control system is powered on, the processing unit 1 executes the execution module 21 of the BIOS 2 and enters the setting of the BIOS 2 in the POST stage, and changes the first bit value of the setting parameter to "1" to the second bit value to "0" and restarts the operation. During the restart process, when the processing unit 1 reads the second bit value "0", the processing unit 1 controls the control pin 41 of the Super I/O4 to send the second control signal to the input terminal 31 of the management and control unit 3 and to be operated by the switch circuit module 33, and then the output terminal 32 generates the high level and transmits the high level to the HDA _ SDO pin 62 of the platform path controller 6, at this time, the HDA _ SDO pin 62 is the high level, so that the firmware data of the management engine 61 can be updated.

It should be noted that, in the present embodiment, the switch circuit module 33 of the control unit 3 has a PMOS circuit 34 linking the input terminal 31 and the output terminal 32, and a pull-up resistor 35 linking the PMOS circuit 34. The pull-up resistor 35 has a first terminal 351 connected to the PMOS circuit 34, and a second terminal 352 for receiving power-up of the server control system. In this embodiment, the first control signal sent from the control pin 41 of the Super I/O4 is a High voltage level signal (High), and the second control signal is a Low voltage level signal (Low), but not limited thereto. When the control pin 41 sends the low voltage level signal to the input terminal 31 of the control unit 3, the pull-up resistor 35 is connected to the output terminal 32 through the PMOS circuit 34 of the switch circuit module 33 and the PMOS circuit 34 is turned on, and the output terminal 32 generates the high level signal and transmits the high level signal to the HDA _ SDO pin 62 of the platform path controller 6; when the control pin 41 sends the high voltage level signal to the input terminal 31 of the management and control unit 3, the output terminal 32 generates the low level signal and transmits the low level signal to the HDA _ SDO pin 62 of the platform path controller 6 through the PMOS circuit 34 of the switch circuit module 33 and the PMOS circuit 34 is unable to conduct and link the first terminal 351 of the pull-up resistor 35 and the output terminal 32. In other words, when the PMOS circuit 34 of the switch circuit module 33 receives the low voltage level signal via the input terminal 31, the PMOS circuit 34 is turned on to connect the first terminal 351 of the pull-up resistor 35 to the output terminal 32, and since the second terminal 352 of the pull-up resistor 35 receives the power-on voltage of the server control system, when the first terminal 351 of the pull-up resistor 35 is turned on to connect the output terminal 32, the level of the output terminal 32 is pulled up to be in the high level state, and the HDA _ SDO pin 62 of the platform path controller 6 is synchronously turned to be in the high level state. In contrast, when the PMOS circuit 34 of the switch circuit module 33 receives the high voltage level signal via the input terminal 31, the PMOS circuit 34 cannot turn on the pull-up resistor 35 and the output terminal 32, so the output terminal 32 is at the low level state and the HDA _ SDO pin 62 of the stage path controller 6 is at the low level synchronously. In this embodiment, the power-on voltage of the server control system to the second terminal 352 of the pull-up resistor 35 is 3.3 volts, but not limited thereto. In addition, in the present embodiment, a source (S) (not shown) of the PMOS circuit 34 is connected to the first end 351 of the pull-up resistor 35, a drain (D) (not shown) of the PMOS circuit 34 is connected to the output end 32 of the control unit 3, and a gate (G) (not shown) of the PMOS circuit 34 is connected to the input end 31 of the control unit 3, but not limited thereto.

By means of the design that the switch circuit module 33 of the management and control unit 3 can receive the signal sent by the Super I/O4 from the input terminal 31 and the application that the switch circuit module 33 generates the high level from the output terminal 32 and transmits the high level to the HDA _ SDO pin 62 of the platform path controller 6 after receiving the second control signal, the HDA _ SDO pin 62 is in the high level state, so that the firmware data of the management engine 61 (ME) can be updated and overwritten, the level of the HDA _ SDO pin 62 can be raised without using an additional manual external Jumper mode, and the time is effectively saved.

In addition, it is to be noted that, in the present embodiment, the server control system further includes an update unit 5 having an update module 51. The update module 51 has update firmware data 52 and an initial configuration parameter mode 53. When the processing unit 1 executes the execution module 21 of the bios 2 and reads that the setting parameter is the second bit value, the processing unit 1 controls the control pin 41 of the Super I/O4 to send the second control signal to the input terminal 31 of the management and control unit 3 and to operate through the switch circuit module 33, and generates the high level from the output terminal 32 to make the HDA _ SDO pin 62 the high level and to enable the firmware data of the management engine 61 to be updated, the processing unit 1 executes the update module 51 of the update unit 5 and updates and overwrites the update firmware data 52 in the management engine 61, and when the update firmware data 52 is updated and overwrites in the management engine 61, the processing unit 1 executes the initial setting parameter mode 53 of the update module 51 and changes the setting parameter of the bios 2 back to the first bit value. That is, after the new firmware data is updated and written into the management engine 61, the processing unit 1 executes the initial setting parameter mode 53 of the update module 51 and changes the setting parameter back to the Default value (Default) as the first bit value "1", so that when the server control system is powered on next time, the processing unit 1 executes the execution module 21 of the bios 2 and reads that the setting parameter is the first bit value "1", and the control pin 41 controlling the Super I/O4 sends the first control signal to the input terminal 31 of the management and control unit 3 and runs through the switch circuit module 33, and makes the HDA _ SDO pin 62 at the low level to make the firmware data of the management engine 61 in the protection mechanism and unable to be changed, and the processing unit 1 continues to execute the execution module 21 of the bios 2 to perform the power on operation. In this embodiment, the update unit 5 is a Flash Memory (Flash Memory) storing the update module 51, but not limited thereto, the update unit 5 may also be a baseboard management control system (BMC), as long as the processing unit 1 can obtain the update firmware data 52 of the update module 51 through the update unit 5 and update and overwrite the update firmware data 52 into the management engine 61.

In summary, in the server control system of the present invention, the switch circuit module 33 of the management and control unit 3 is designed to receive the signal from the Super I/O4 through the input terminal 31, and the switch circuit module 33 generates the high level from the output terminal 32 and transmits the high level to the HDA _ SDO pin 62 of the platform path controller 6 after receiving the second control signal, so that the HDA _ SDO pin 62 is in the high level state and the firmware data of the management engine 61 (ME) can be updated and overwritten, and the level of the HDA _ SDO pin 62 can be raised without using an additional manual external connection Jumper manner, thereby effectively saving time.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A server control system for updating a firmware data of a management engine of a platform path controller having an HDA _ SDO pin, the server control system comprising:

the control unit is connected with the HDA _ SDO pin of the platform path controller and comprises a switch circuit module, an input end connected with the switch circuit module and an output end connected with the switch circuit module and the HDA _ SDO pin of the platform path controller; and

a Super I/O connected to the control unit, including a control pin, the input end of the control unit is connected to the switch circuit module and the control pin of the Super I/O, the control pin of the Super I/O can be controlled to send out a first control signal, and a second control signal, after the control pin sends out the first control signal to the input end of the control unit and runs through the switch circuit module, and from the output end generates a low level and transmits to the HDA _ SDO pin of the platform path controller, at this time, the HDA _ SDO pin is the low level and makes the firmware data of the Management Engine (ME) in the protection mechanism and can not be changed; the control pin sends the second control signal to the input end of the control unit and after the control signal is operated by the switch circuit module, a high level is generated from the output end and is transmitted to the HDA _ SDO pin of the platform path controller, and at the moment, the HDA _ SDO pin is the high level, so that the firmware data of the Management Engine (ME) can be updated.

2. The server control system of claim 1, wherein the first control signal sent from the control pin of the Super I/O is a high voltage level signal, and the second control signal is a low voltage level signal.

3. The server control system of claim 2, wherein the switch circuit module of the management and control unit has a PMOS circuit linking the input terminal and the output terminal, and a pull-up resistor linking the PMOS circuit, the pull-up resistor having a first end linking the PMOS circuit and a second end receiving power-up of the server control system, when the control pin sends the low voltage level signal to the input terminal of the management and control unit, the PMOS circuit of the switch circuit module is turned on to connect the first end of the pull-up resistor to the output terminal, and the output terminal generates the high level and transmits the high level to the HDA _ SDO pin of the platform path controller; when the control pin sends the high voltage level signal to the input terminal of the control unit, the output terminal generates the low level and transmits the low level to the HDA _ SDO pin of the platform path controller through the PMOS circuit of the switch circuit module and the PMOS circuit is unable to conduct and link the first terminal of the pull-up resistor and the output terminal.

4. The server control system according to claim 1, wherein the Super I/O further comprises an LPC bus linking the platform path controller, and a control pin of the Super I/O is a GPIO pin.

5. The server control system according to claim 4, wherein the server control system further comprises a processing unit connected to the platform path controller, and a bios connected to the platform path controller, the bios including an execution module and a setting parameter corresponding to the Super I/O, when the server control system is powered on, the processing unit receives and executes the execution module of the bios through the platform path controller and reads the setting parameter, when the setting parameter is read as a first bit value, the processing unit controls the control pin of the Super I/O to send the first control signal to the input terminal of the management control unit and to operate through the switch circuit module, and generates the low level from the output terminal of the management control unit and transmits the low level to the HDA _ SDO pin of the platform path controller, at this time, the HDA _ SDO pin is the low level and makes the firmware data of the management engine in a protection mechanism and cannot be changed, and the processing unit executes the execution module of the bios to obtain the boot-on operation; when the setting parameter is read to be a second bit value, the processing unit controls the control pin of the Super I/O to send the second control signal to the input end of the control unit, and after the control signal is operated by the switch circuit module, the high level is generated from the output end of the control unit and is transmitted to the HDA _ SDO pin, and at the moment, the HDA _ SDO pin is the high level, so that the firmware data of the management engine can be updated.

6. The server control system of claim 5, further comprising an update unit having an update module with an update firmware data, wherein when the processing unit executes the execution module of the BIOS and reads that the setting parameter is the second bit value, the processing unit controls the control pin of the Super I/O to send the second control signal to the input terminal of the management control unit, so that the HDA _ SDO pin is at the high level and the firmware data of the management engine can be updated, and then the processing unit executes the update module of the update unit and writes the update firmware data into the management engine.

7. The server control system of claim 6, wherein the update module of the update unit further has an initial configuration parameter mode, and after the processing unit executes the update module of the update unit and updates and overwrites the updated firmware data in the management engine, the processing unit executes the initial configuration parameter mode of the update module and changes the configuration parameter of the BIOS back to the first bit value.

8. The system of claim 5, wherein the first bit value of the parameter configuration of the basic input/output unit is "1", the second bit value is "0", and when the parameter configuration is "1", the processing unit controls the control pin of the Super I/O to send the first control signal as a High voltage level signal (High); when the setting parameter is set to "0", the processing unit controls the control pin of the Super I/O to send the second control signal as a low voltage level signal.