CN115632903B - Virtual peripheral communication bus control method and device and computer equipment - Google Patents
Virtual peripheral communication bus control method and device and computer equipment Download PDFInfo
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- 238000005070 sampling Methods 0.000 claims description 16
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- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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Abstract
The invention provides a virtual peripheral communication bus control method, a device and computer equipment, wherein the method comprises the steps of obtaining a channel mapping relation between an input pin and an output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one; when the first channel meets the setting condition, the first channel performs data transmission through a public interface processing engine, and the first channel is any channel corresponding to the communication interface. The method provided by the invention can enable the user to automatically expand the number of the communication interfaces according to application requirements, automatically define the positions of the communication pins, increase the communication interfaces on the premise of reducing the number of the IP cores and the chip area, improve the communication performance of the microcontroller and reduce the communication cost.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for controlling a virtual peripheral communications bus, and a computer device.
Background
Microcontrollers require multiple asynchronous serial interfaces or synchronous serial interfaces for communication with external devices, and commonly used interfaces include a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) interface, and a two-wire serial bus (Inter-INTEGRATED CIRCUIT, I2C) interface, among others. In order to process data transmitted by the interfaces, an intellectual property (Intellectual Property, IP) core is usually designed for each communication interface, so as to implement simultaneous processing of input and output data of multiple communication interfaces.
If the number of communication interfaces required by the user is greater than the number of communication interfaces contained by the microcontroller, software or timers are typically employed to capture the input pin level and control the output pin level to simulate the communication interfaces. Such methods are not only inconvenient to use, but also waste processing power and timer resources of the processor. If the method of adding the multipath communication IP core is adopted, the chip area is increased, and the cost is increased.
Disclosure of Invention
In order to solve the problem of inconvenient use and high cost when the existing microcontroller expands interfaces, the application provides a virtual peripheral communication bus control method, a device and computer equipment, so that the communication performance of the microcontroller can be improved on the premise of not increasing the area of a chip.
In one aspect, a virtual peripheral communication bus control method is provided, and the method includes:
Obtaining a channel mapping relation between an input/output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one;
When the first channel meets the setting condition, the first channel performs data transmission through an interface processing engine, and the first channel is any channel corresponding to the communication interface.
In another aspect, there is provided a virtual peripheral communication bus control apparatus, the apparatus comprising:
The mapping relation acquisition module is used for acquiring the channel mapping relation between the input and output pins and the communication interfaces, wherein the number of channels corresponding to the communication interfaces is more than one;
and the data transmission module is used for transmitting data through the interface processing engine when the first channel meets the setting condition, wherein the first channel is any channel corresponding to the communication interface.
In another aspect, a computer device is provided, where the computer device includes a processor and a memory, where the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the processor may load and execute the at least one instruction, the at least one program, the code set, or the instruction set, so as to implement the virtual peripheral communication bus control method provided in the foregoing application embodiment.
In another aspect, a microcontroller is provided, comprising a computer device as described above.
In another aspect, a computer readable storage medium is provided, where at least one instruction, at least one program, a code set, or an instruction set is stored in the readable storage medium, and a processor may load and execute the at least one instruction, the at least one program, the code set, or the instruction set, so as to implement the virtual peripheral communication bus control method provided in the embodiment of the present application.
In another aspect, a computer program product or computer program is provided, the computer program title or computer program comprising computer program instructions stored in a computer readable storage medium. The processor reads the computer instructions from the computer-readable storage medium and executes the computer instructions to cause the computer device to perform the virtual peripheral communication bus control method according to any of the above embodiments.
The technical scheme provided by the application has the beneficial effects that at least: the embodiment of the application provides a virtual peripheral communication bus control method, a device and computer equipment, wherein the method comprises the steps of obtaining a channel mapping relation between an input pin and an output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one; when the first channel meets the setting condition, the first channel performs data transmission through an interface processing engine, and the first channel is any channel corresponding to the communication interface. The method provided by the embodiment of the application can enable the user to automatically expand the number of the communication interfaces according to application requirements and automatically define the positions of the communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the area of chips, improve the communication performance of the microcontroller and reduce the communication cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates a flow chart of a virtual peripheral communication bus control method provided by an exemplary embodiment of the present application;
Fig. 2 is a schematic diagram of a communication interface controller corresponding to a virtual peripheral communication bus control method according to an exemplary embodiment of the present application;
FIG. 3 is a flow chart of a method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application;
FIG. 4 is a flow chart illustrating another method for virtual peripheral communication bus control according to an exemplary embodiment of the present application;
FIG. 5 is a flowchart illustrating a method for virtual peripheral communication bus control according to yet another exemplary embodiment of the present application;
fig. 6 is a block diagram showing a virtual peripheral communication bus control apparatus according to an exemplary embodiment of the present application;
Fig. 7 is a schematic structural diagram of a computer device corresponding to a virtual peripheral communication bus control method according to an exemplary embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The virtual peripheral communication bus control method provided by the application can enable a user to automatically expand the number of communication interfaces according to application requirements, automatically define the positions of communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the chip area, improve the communication performance of a microcontroller and reduce the communication cost.
Embodiment 1,
Fig. 1 is a schematic implementation flow diagram of a virtual peripheral communication bus control method according to an embodiment of the present invention.
Referring to fig. 1, the virtual peripheral communication bus control method provided by the embodiment of the present invention may include step 101 and step 102.
Step 101: and obtaining the channel mapping relation between the input and output pins and the communication interfaces, wherein the number of channels corresponding to the communication interfaces is more than one.
The virtual peripheral communication bus control method provided by the embodiment of the invention enables the pins of the external communication channel to be mapped to any general input/output pins through the pin mapping matrix, and is convenient for a user to define the corresponding relation according to the needs so as to increase the flexibility of pin configuration.
In some embodiments, each communication interface channel has an independent clock divider, i.e., the sampling frequency/output frequency of each channel is independently configurable and modifiable by a user.
In some embodiments, each of the channels corresponds to an independent output first-in-first-out (First Input First Output, FIFO) queue and an independent input first-in-first-out queue. The output first-in first-out queue is used for caching at least one of output data, command sequences and configuration sequences; the input first-in first-out queue is used for caching at least one of input data or a state sequence.
The virtual peripheral communication bus control method provided by the embodiment of the invention connects each channel with an independent output buffer FIFO and an input buffer FIFO and stores the required data sequences respectively.
Step 102: when the first channel meets the setting condition, the first channel performs data transmission through an interface processing engine, and the first channel is any channel corresponding to the communication interface.
In some embodiments, the set condition comprises an input set condition comprising the number of input samples of the channel reaching a preset threshold;
When the first channel meets the setting condition, the first channel performs data transmission, including:
When the input sampling number of the first channel reaches the preset threshold, the input task position of the first channel is set, and the first channel inputs data.
In some embodiments, the set condition comprises an output set condition comprising an internal bus outputting data to the channel;
When the first channel meets the setting condition, the first channel performs data transmission, including:
When the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
In some embodiments, the internal bus may include at least one of AHB, APB, AXI buses.
In some embodiments, the first channel performs a data transfer operation, including:
And controlling all the first channels meeting the setting conditions to transmit data according to a preset sequence based on an interface processing engine.
In the virtual peripheral communication bus control method provided by the embodiment of the invention, the high-speed interface data engine processes the input and output data of all channels with task position bits according to the priority order or the first-in first-out order defined by the user.
In some embodiments, the first channel performs a data transfer operation, including:
The interface processing engine obtains the sampling level in the input buffer first-in first-out queue of the first channel, converts the sampling level into input data, and stores the input data into a device static random access memory (Static Random Access Memory, SRAM);
And/or the interface processing engine acquires a state sequence in the input buffer first-in first-out queue of the first channel, converts the state sequence into a state bit of the first channel, and stores the state bit data into a device static random access memory.
The virtual peripheral communication bus control method provided by the embodiment of the invention centralizes the configuration and state data of each virtual communication IP in the SRAM, and correspondingly switches the configuration and state data when switching one virtual channel, so as to realize the correct operation of the virtual channel.
Specifically, for output, the interface processing engine sets the output task position, notifies the channel to output data, and clears the output task position after the channel processing is completed. For input, the channel sets the input task position, informs the interface processing engine to process the input data, and clears the input task position after the engine finishes processing.
Alternatively, the input output task bits may be replaced by status bits of the input output FIFO.
Specifically, the high-speed interface processing engine converts output data into a sequence of output levels in the output buffer FIFO of the corresponding channel, and for more complex communication interfaces, such as an I2C interface, may convert output data into a sequence of commands according to the I2C protocol in the output buffer FIFO of the corresponding channel.
In some embodiments, the high-speed interface processing engine fetches sample levels from the input-output buffer FIFOs of the corresponding channels and converts the sample levels to input data for placement in the data SRAM, and the interface processing engine may fetch state sequences from the input-buffer FIFOs of the corresponding channels and convert the state bits of the corresponding channels to placement in the state SRAM.
In some embodiments, the peripheral bus controller communicates with a processor of the microcontroller or a direct memory access (Direct Memory Access, DMA) engine, passing input-output data.
The virtual peripheral communication bus control method provided by the embodiment of the invention can realize virtual multipath communication, multipath communication IP can be expanded on one communication IP core, and each communication IP is independent from the use angle of a user, so that the receiving and transmitting data of respective input and output pins can be processed simultaneously. The method can realize sharing of the interface processing engines, time-sharing switching of the engines is carried out, and input and output data of each channel are processed by switching multiple channels.
Embodiment II,
Fig. 2 is a schematic diagram of a communication interface controller corresponding to a virtual peripheral communication bus control method according to an exemplary embodiment of the present application.
Referring to fig. 2, in one specific example, the virtual multi-way peripheral communication interface controller is divided into an interface clock domain, a data processing clock domain, and a bus clock domain. The interface clock domain comprises a pin mapping function, a channel selection function and a pin level input and output function; the data processing clock domain comprises a high-speed interface processing engine processing and SRAM configuration function; the bus clock domain includes internal bus control processing functions.
The virtual peripheral communication bus control method provided by the embodiment of the invention divides the clock domain into the communication interface clock domain, the high-speed data processing clock domain and the bus control clock domain, and can realize the input and output data transmission crossing 3 clock domains.
In some embodiments, the communication interface clock domain, the high-speed data processing clock domain and the bus control clock domain can be regarded as three asynchronous clock domains, or the high-speed data processing and the bus control can be combined into one clock domain, and the combined clock is also a clock source of each channel of the communication interface.
In some embodiments, multiple sets of general purpose input output pins are connected to a certain set of channels of the communication interface through a pin mapping matrix.
In some embodiments, the configuration, status and data registers of all virtual devices may be implemented as configuration SRAM and data/status SRAM, as well as register files.
Specifically, the multiple sets of general input/output pins are connected to a certain set of channels of the communication interface through a pin mapping matrix, where the channels may include a plurality of sampling/IO buffer channels. And connecting the selected channel with a high-speed interface processing engine, selecting configuration SRAM or state/data SRAM, and finally connecting with an internal bus control engine to realize a data transmission function.
Fig. 3 is a flowchart illustrating a method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application.
Before input/output channel configuration, multiple groups of general input/output pins are connected with a certain group of channels of a communication interface through a pin mapping matrix.
Referring to fig. 3, the workflow of the input-output channel in the present application specifically includes the following steps.
And step one, configuring parameters such as a clock source, a frequency division coefficient and the like.
Specifically, the clock source and the clock divide value for each expansion channel are set by outputting the configuration sequence in the buffer FIFO.
And step two, controlling the bus signal level according to the output buffer data or command sequence.
Specifically, when the output task position of the corresponding channel is set, the corresponding channel takes out the output data or command sequence in the buffer FIFO, controls the communication bus signal pin level according to the clock frequency set by the user, and resets the output task position of the channel after completion.
And step three, the input pin level is sampled according to the clock and is put into an input buffer.
Specifically, the input pins are correspondingly sampled according to the clock frequency set by the user, and the sampled level value is placed in the input sampling buffer FIFO.
And step four, setting task bits corresponding to the channel states when the input buffer reaches a fixed threshold value.
Specifically, when the number of level values in the input sample buffer FIFO reaches a threshold, the input task bit corresponding to the channel state is set, so that the high-speed interface data engine starts to process the input data.
And circularly executing the second step to the fourth step to realize the control of the input/output channel.
Fig. 4 is a flowchart illustrating another method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application.
Referring to FIG. 4, the workflow of the high-speed interface processing engine of the present application specifically includes the following steps
The output data is converted into a sequence of levels or a sequence of commands placed in an output buffer FIFO.
Specifically, the high-speed interface processing engine converts output data into output signals and places the output signals in output buffer FIFOs of corresponding channels, and for a more complex communication interface, the command sequence for converting the output data into a bus state machine according to a bus protocol can be placed in the output buffer FIFOs of the corresponding channels and output task bits of the corresponding channels are located.
Specifically, if the input task bit of all channel states has a set, the high-speed interface processing engine begins processing the communication interface input data.
If any channel inputs the task position setting, the setting channel is selected according to the priority order or the first-in first-out order.
Specifically, the high-speed interface processing engine selects one channel from all channels with input task position bits according to the user-defined priority order or first-in first-out order.
The input level is fetched from the input buffer FIFO and converted into input data for placement in the data SRAM.
The state sequence is fetched from the input buffer FIFO and placed in the state SRAM.
Specifically, the high-speed interface processing engine fetches the sample level from the input buffer FIFO of the corresponding channel, converts it into input data, and places it in the data SRAM. The interface processing engine may also fetch a state sequence from the input buffer FIFO of the corresponding lane, converting to a state bit of the corresponding lane to be placed in the state SRAM.
Finally, the internal bus control engine is notified to receive the input data and reset the channel input task bit.
Specifically, the high-speed interface processing engine notifies the internal bus control engine to receive input data and resets the input task bit corresponding to the channel state.
And circularly executing the steps, and continuing to process the next channel after the current channel is completed.
Fig. 5 is a flowchart illustrating a method for controlling a virtual peripheral communication bus according to another exemplary embodiment of the present application.
Referring to fig. 5, the operation flow of the internal bus control engine in the present application is as follows.
Step one: a read-write request is received to designate a configuration register for a designated channel.
Specifically, the internal bus control engine receives a read-write request from the microcontroller processor to a specified configuration register of a specified channel.
Step two: corresponding registers are read and written from the configuration, data and state SRAM and the result is returned.
Specifically, the internal bus control engine reads and writes corresponding registers from the configuration SRAM and the state/data SRAM, and transmits the results to the microcontroller processor, wherein the configuration SRAM and the state/data SRAM are dual-port SRAMs.
Step three: the received output data is placed in a data SRAM and the interface processing engine is notified to process the output data.
Specifically, after receiving the output data sent from the processor or the DMA, the high-speed interface processing engine is caused to start processing the output data.
Step four: input data is received from the interface processing engine and transferred to the DMA engine.
Specifically, after receiving the input data sent from the high-speed interface processing engine, the input data is sent to the DMA.
And circularly executing the second step to the fourth step to realize the process of the internal bus control engine.
In summary, the virtual peripheral communication bus control method provided by the embodiment of the invention can enable the user to automatically expand the number of communication interfaces according to application requirements, automatically define the positions of communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the chip area, improve the communication performance of the microcontroller and reduce the communication cost.
Third embodiment,
Fig. 6 is a schematic structural diagram of a virtual peripheral communication bus control device according to an embodiment of the present invention.
Referring to fig. 6, a virtual peripheral communication bus control device provided by an embodiment of the present invention may include:
The mapping relation obtaining module 201 is configured to obtain a channel mapping relation between an input/output pin and a communication interface, where the number of channels corresponding to the communication interface is greater than one;
The data transmission module 202 is configured to perform data transmission by the first channel through the interface processing engine when the first channel meets the set condition, where the first channel is any channel corresponding to the communication interface.
In some embodiments, each of the channels corresponds to an independent output first-in-first-out queue and an independent input first-in-first-out queue;
The output first-in first-out queue is used for caching at least one of output data, command sequences and configuration sequences;
The input first-in first-out queue is used for caching at least one of input data or a state sequence.
The setting conditions comprise input setting conditions, wherein the input setting conditions comprise that the input sampling number of the channel reaches a preset threshold; in some embodiments, the data transmission module 202 is specifically configured to:
When the input sampling number of the first channel reaches the preset threshold, the input task position of the first channel is set, and the first channel inputs data.
The set conditions include an output set condition including an internal bus outputting data to the channel; in some embodiments, the data transmission module 202 is specifically configured to:
When the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
In some embodiments, the data transmission module 202 is specifically configured to:
and the interface processing engine controls all the first channels meeting the setting conditions to transmit data according to a preset sequence.
In some embodiments, the data transmission module 202 is specifically configured to:
The interface processing engine obtains a sampling level from an input buffer first-in first-out queue of the first channel, converts the sampling level into input data, and stores the input data into a device static random access memory;
And/or the interface processing engine acquires a state sequence from the input buffer first-in first-out queue of the first channel, converts the state sequence into a state bit of the first channel, and stores the state bit data into a device static random access memory.
In summary, the virtual peripheral communication bus control device provided by the embodiment of the invention can enable a user to automatically expand the number of communication interfaces according to application requirements, automatically define the positions of communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the chip area, improve the communication performance of a microcontroller, and reduce the communication cost.
Fourth embodiment,
Fig. 7 shows a schematic structural diagram of a computer device according to an exemplary embodiment of the present application, where the computer device includes:
processor 301, including one or more processing cores, executes various functional applications and data processing by running software programs and modules by processor 301.
The receiver 302 and the transmitter 303 may be implemented as one communication component, which may be a communication chip. Alternatively, the communication component may be implemented to include a signaling function. That is, the transmitter 303 may be used to transmit control signals to the image acquisition device and the scanning device, and the receiver 302 may be used to receive corresponding feedback instructions.
The memory 304 is connected to the processor 301 by a bus 305.
The memory 304 may be configured to store at least one instruction, and the processor 301 is configured to execute the at least one instruction to implement steps 101 to 102 in the above-described embodiment of the virtual peripheral communication bus control method.
Fifth embodiment (V),
The embodiment of the application also provides a microcontroller comprising the computer equipment.
Embodiment six,
The embodiment of the application also provides a computer readable storage medium, wherein at least one instruction, at least one section of program, code set or instruction set is stored in the readable storage medium, so as to be loaded and executed by a processor to realize the virtual peripheral communication bus control method.
Embodiment seven,
The present application also provides a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the virtual peripheral communication bus control method according to any one of the above embodiments.
Alternatively, the computer-readable storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), solid state disk (SSD, solid STATE DRIVES), or optical disk, etc. The random access memory may include resistive random access memory (ReRAM, RESISTANCE RANDOM ACCESS MEMORY) and dynamic random access memory (DRAM, dynamic Random Access Memory), among others. The foregoing description of the embodiments of the present application is provided for the purpose of illustration only, and does not represent the advantages or disadvantages of the implementation.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.
Claims (8)
1. A method for controlling a virtual peripheral communication bus, the method comprising:
Obtaining a channel mapping relation between an input/output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one;
When the first channel meets a setting condition, the first channel performs data transmission corresponding to the input/output pin based on an interface processing engine, wherein the first channel is any channel of the communication interface;
the setting conditions comprise input setting conditions, wherein the input setting conditions comprise that the input sampling number of the channel reaches a preset threshold;
when the first channel meets the setting condition, the first channel performs data transmission corresponding to the input/output pin based on the interface processing engine, and the method comprises the following steps:
When the input sampling number of the first channel reaches the preset threshold value, the input task position of the first channel is set, and the first channel inputs data;
the set conditions include an output set condition including an internal bus outputting data to the channel;
when the first channel meets the setting condition, the first channel performs data transmission corresponding to the input/output pin based on the interface processing engine, and the method comprises the following steps:
When the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
2. The method of claim 1, wherein each of the channels corresponds to an independent output first-in-first-out queue and an independent input first-in-first-out queue;
The output first-in first-out queue is used for caching at least one of output data, command sequences and configuration sequences;
The input first-in first-out queue is used for caching at least one of input data or a state sequence.
3. The method according to any one of claims 1 to 2, wherein the first channel performs data transmission corresponding to the input-output pins based on an interface processing engine, comprising:
And controlling all the first channels meeting the setting conditions to transmit data according to a preset sequence based on an interface processing engine.
4. The method according to any one of claims 1 to 2, wherein the first channel performs a data transfer operation corresponding to the input-output pin based on an interface processing engine, comprising:
The interface processing engine acquires a sampling level from an input buffer first-in first-out queue of the first channel, converts the sampling level into input data, and stores the input data into a device static random access memory;
And/or the interface processing engine acquires a state sequence from the input buffer first-in first-out queue of the first channel, converts the state sequence into a state bit of the first channel, and stores the state bit data into a device static random access memory.
5. A virtual peripheral communication bus control apparatus, the apparatus comprising:
The mapping relation acquisition module is used for acquiring the channel mapping relation between the input and output pins and the communication interfaces, wherein the number of channels corresponding to the communication interfaces is more than one;
The data transmission module is used for transmitting data corresponding to the input and output pins based on an interface processing engine when the first channel meets a setting condition, wherein the first channel is any channel of the communication interface;
the setting conditions comprise input setting conditions, wherein the input setting conditions comprise that the input sampling number of the channel reaches a preset threshold;
The data transmission module is specifically used for:
When the input sampling number of the first channel reaches the preset threshold value, the input task position of the first channel is set, and the first channel inputs data;
the set conditions include an output set condition including an internal bus outputting data to the channel;
The data transmission module is specifically used for:
When the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
6. A computer device comprising a processor and a memory having stored therein at least one instruction, at least one program, code set, or instruction set that is loaded and executed by the processor to implement the virtual peripheral communication bus control method of any of claims 1 to 4.
7. A microcontroller comprising the computer device of claim 6.
8. A computer readable storage medium having stored therein at least one instruction, at least one program, code set, or instruction set loaded and executed by a processor to implement the virtual peripheral communication bus control method of any of claims 1 to 4.
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| CN111147340A (en) * | 2019-12-26 | 2020-05-12 | 山东超越数控电子股份有限公司 | Method, equipment and medium for carrying out networked access on CAN bus interface |
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| CN1556956A (en) * | 2001-09-21 | 2004-12-22 | ض� | Multi-channel interface for communications between devices |
| CN111147340A (en) * | 2019-12-26 | 2020-05-12 | 山东超越数控电子股份有限公司 | Method, equipment and medium for carrying out networked access on CAN bus interface |
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