CN115630600B

CN115630600B - Method, apparatus, and medium for layout processing

Info

Publication number: CN115630600B
Application number: CN202211638035.9A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Advanced Manufacturing EDA Co Ltd
Current assignee: Advanced Manufacturing EDA Co Ltd
Priority date: 2022-12-20
Filing date: 2022-12-20
Publication date: 2023-03-14
Anticipated expiration: 2042-12-20
Also published as: CN115630600A

Abstract

Example embodiments in accordance with the present disclosure provide methods, apparatus, and media for layout processing. In the method, a plurality of target patterns in the layout is determined for a plurality of measurement points in the layout. Each target pattern corresponds to a measurement point and is within the range associated with that measurement point. A first set of measurement points having a first symmetry is determined from the plurality of measurement points by applying a first operation corresponding to the first symmetry to the plurality of target patterns, respectively. The layout is optimized based on at least the first set of measurement points such that the first set of measurement points maintains a first symmetry in the optimized layout. In this way, the symmetry of the target patterns can be maintained in the process of optimizing the layout, and therefore the actual patterns corresponding to the target patterns on the wafer have symmetry.

Description

Method, apparatus, and medium for layout processing

Technical Field

Embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly, to methods, apparatuses, and media for layout processing.

Background

The circuit Layout (also called Layout for short) is a series of geometric figures converted from the designed and simulated optimized circuit, and contains physical information data related to devices such as the size of the integrated circuit and the definition of each layer topology. The integrated circuit manufacturer manufactures the mask according to the data. The layout pattern on the mask determines the size of the devices or physical layer of connections on the chip.

As technology nodes of an integrated circuit manufacturing process decrease, distances between target patterns in the integrated circuit decrease, and the density of layout patterns on the mask corresponding to the target patterns increases. Since the light wave is diffracted at the layout pattern of the mask, the actually formed pattern is distorted compared to the layout pattern. For this reason, optical Proximity Correction (OPC) has been proposed to adjust the layout pattern of the mask in order to form a desired target pattern. However, in a grid-based simulation environment, the layout pattern on the mask often has deviations from the pattern actually formed on the wafer. This results in the layout pattern losing symmetry in the grid and the pattern actually formed on the wafer corresponding to the layout pattern losing symmetry.

Disclosure of Invention

In a first aspect of the disclosure, a method for layout processing is provided. In the method, a plurality of target patterns in the layout are determined for a plurality of measurement points in the layout. Each target pattern corresponds to a measurement point and is within the range associated with that measurement point. The method also includes determining a first set of measurement points from the plurality of measurement points having a first symmetry by applying a first operation corresponding to the first symmetry to the plurality of target graphics, respectively. The method also includes optimizing the layout based at least on the first set of measurement points such that the first set of measurement points maintains a first symmetry in the optimized layout. In this way, the plurality of target patterns in the layout are adjusted, so that the plurality of target patterns keep symmetry in the process of optimizing the layout.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor, and a memory coupled with the processor. The memory has instructions stored therein, which when executed by the processor, cause the electronic device to perform a method for layout processing according to the first aspect of the present disclosure.

In a third aspect of the disclosure, a computer-readable storage medium is provided. The computer readable storage medium has stored thereon a computer program. The computer program, when executed by a processor, implements a method for layout processing according to the first aspect of the present disclosure.

According to an embodiment of the present disclosure, a plurality of target patterns corresponding to a plurality of measurement points in a layout, respectively, are determined. Each target pattern is within a range associated with a respective measurement point. A set of measurement points having a given symmetry (e.g., a first symmetry) is determined from among the plurality of measurement points by applying an operation corresponding to the given symmetry to the plurality of target patterns, respectively. Further, the layout is optimized based on at least the set of measurement points such that the set of measurement points maintains a given symmetry in the optimized layout. In this way, the target feature is optimized based on a set of measurement points having a given symmetry determined from a plurality of measurement points corresponding to the plurality of target features such that the plurality of target features maintain symmetry during optimization of the layout. Therefore, the embodiment of the disclosure can keep the symmetry of the target patterns in the layout optimization process, so that the actual patterns corresponding to the target patterns on the wafer have the same symmetry. In this way, the quality of the layout can be improved.

It should be understood that the statements herein set forth in this summary are not intended to limit the essential or critical features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

FIG. 2 illustrates a flow diagram of a method for layout processing according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic diagram of determining a target pattern from measurement points, according to some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of determining a first set of measurement points having a first symmetry from a plurality of measurement points, according to some embodiments of the present disclosure;

FIG. 5 illustrates a schematic diagram of determining that a plurality of measurement points do not belong to a first set of measurement points, according to some embodiments of the present disclosure;

6A-6I illustrate schematic diagrams of determining a second set of measurement points having a second symmetry from a plurality of measurement points, according to some embodiments of the present disclosure;

FIG. 7 shows a schematic diagram of the results of processing a layout according to some embodiments of the present disclosure; and

fig. 8 illustrates a block diagram of an electronic device/server in which one or more embodiments of the present disclosure may be implemented.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and the embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, in a grid-based simulation environment, layout patterns on a mask often have deviations, such as shift variances, from the patterns actually formed on the wafer. These deviations may cause signal differences in the layout patterns of the symmetric layout structure. For example, the first layout pattern and the second layout pattern corresponding to the first measurement point and the second measurement point, respectively, in the layout are symmetrically arranged. However, since the position of the first measurement point relative to the network is different from the position of the second measurement point relative to the grid, the signal strength at the first measurement point is different from the signal strength at the second measurement point. This results in loss of symmetry in the patterns actually formed on the wafer corresponding to the first layout pattern and the second layout pattern. Therefore, it is necessary to provide an effective layout optimization method to maintain the symmetry of the patterns in the layout.

To this end, an embodiment of the present disclosure proposes a method for layout processing. According to an embodiment of the present disclosure, a plurality of target patterns corresponding to a plurality of measurement points in a layout, respectively, are determined. Each target pattern is within a range associated with a respective measurement point. A set of measurement points having a given symmetry (e.g., a first symmetry) is determined from a plurality of measurement points by applying an operation corresponding to the given symmetry to the plurality of target patterns, respectively. Further, the layout is optimized based on at least the set of measurement points such that the set of measurement points maintains a given symmetry in the optimized layout. In this way, the target feature is optimized based on a set of measurement points having a given symmetry determined from a plurality of measurement points corresponding to the plurality of target features such that the plurality of target features maintain symmetry during optimization of the layout. Therefore, the embodiment of the disclosure can keep the symmetry of the target patterns in the layout optimization process, so that the actual patterns corresponding to the target patterns on the wafer have the same symmetry.

Various example implementations of this scheme will be described in detail below with reference to the accompanying drawings.

Referring initially to FIG. 1, a schematic diagram of an example environment 100 is shown in which embodiments of the present disclosure can be implemented. The example environment 100 may generally include an electronic device 110. In some embodiments, the electronic device 110 may be a computing-enabled device such as a personal computer, workstation, server, or the like. The scope of the present disclosure is not limited in this respect.

The electronic device 110 takes as input the layout 120 to be processed. Layout 120 has layout patterns or graphics therein. As an example, the layout 120 to be processed includes a graph 122 and a graph 124. It should be understood that the shapes and sizes of the various layouts, graphics shown in FIG. 1 are exemplary only, and not limiting. The scope of the present disclosure is not limited in this respect.

The electronic device 110 processes the to-be-processed layout 120 to obtain a processed layout 130. The processed layout 130 includes a graph 132 and a graph 134. The graph 132 and the graph 134 in the processed layout 130 are shifted, respectively, compared to the graph 132 and the graph 134 in the layout 120 to be processed. The above-described displacement of graph 132 and graph 134 may be determined by electronic device 110. This will be described in further detail below in conjunction with fig. 2-5.

FIG. 2 illustrates a flow diagram of a method 200 for layout processing according to some embodiments of the present disclosure. In some embodiments, the method 200 may be performed by the electronic device 110 as shown in fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or may omit certain block(s) shown, as the scope of the present disclosure is not limited in this respect.

At block 210, the electronic device 110 determines a plurality of target features in the layout for a plurality of measurement points in the layout. Each target pattern corresponds to a measurement point and is within the range associated with that measurement point. The plurality of measurement points may be measurement points specified by a user in the layout. For example, the user may specify the measurement points according to constraints for the layout, graphical features of the layout, or other suitable information. The location and number of measurement points may be arbitrarily specified by the user, and the scope of the present disclosure is not limited in this respect.

In some embodiments, the range associated with the measurement point has a predefined size and the measurement point is located within the range. For example, the range associated with a measurement point may be a circle of a predefined radius centered at the measurement point or having a vertex at the measurement point. As another example, the range associated with a measurement point may be a square or other shaped graph having a predefined area centered on or vertex to the measurement point. The electronic device 110 may determine a target graphic associated with the measurement point based on the location of the measurement point and the range associated with the measurement point.

FIG. 3 illustrates a schematic diagram of determining a target pattern from measurement points, according to some embodiments of the present disclosure. The following description will be given by taking the layout 120 in fig. 1 as an example. As shown in FIG. 3, the layout 120 has

measurement points

302 and 304 therein. The electronic device 110 determines a plurality of target graphics for the measurement points 302 and 304. It should be understood that while in the example of FIG. 3, two images and two measurement points are shown, in some embodiments, there may be more graphics and more measurement points in the layout.

In some embodiments, if a given measurement point is located on a graphic in the layout 120 or the given measurement point is closest to the graphic and the graphic is within a range associated with the given measurement point, the electronic device 110 may determine the graphic as the target graphic corresponding to the given measurement point. For example, if graphic 122 is within a range corresponding to measurement point 302, electronic device 110 may determine graphic 122 as a target graphic corresponding to measurement point 302. Similarly, if the graphic 124 is within the range corresponding to the measurement point 304, the electronic device 110 determines the graphic 124 as the target graphic corresponding to the measurement point 304.

The electronic device 110 may employ any suitable rule to determine the target pattern corresponding to the measurement points. Several examples of determining a target range from measurement points, and thus a target pattern, will be described below with continued reference to fig. 3. In some embodiments, the electronic device 110 may determine a distance extending outward from a measurement point of the plurality of measurement points. As an example, the electronic device 110 may obtain user input specifying a distance. The electronic device 110 may then read the distance from the user input. In other words, the distance by which the measurement point expands outward may be input in advance by the user or entered in real time by the user. For example, the electronic device 110 may obtain a configuration file. The configuration file comprises information which is input by a user in advance and relates to the outward expansion distance of the measuring point. As another example, the electronic device 110 may obtain information about the distance that the measurement point extends outward, entered by the user in real time.

In some embodiments, the measurement points extend outward a distance less than the size of the simulation window. The simulation window indicates the layout range involved in the optimization. For example, in OPC, the simulation window is a characteristic of the model that describes the optical proximity effect. In particular, the optical signal of the measurement point at a given position will be affected by the pattern present within the analog window. The size of the analog window may be, for example, in the range of 1000nm to 2000nm, but this is merely an example and is not intended to limit the scope of the present disclosure. Taking FIG. 3 as an example, the simulation window indicates the extent of the layout 120 to be processed. The outward extension range of each measurement point is located within the simulation window.

In some embodiments, the electronic device 110 may determine, for a given measurement point of the plurality of measurement points, a target range associated with the given measurement point based on the location and distance of the given measurement point. The given measurement point may be any one of a plurality of measurement points.

As an example, the electronic device 110 may extend a distance in any direction around the location of a given measurement point as a starting point to determine a target range associated with the given measurement point. For example, the target range associated with a given measurement point may be any shape, such as square, rectangle, circle, polygon, and the like. The scope of the present disclosure is not limited in this respect. In some embodiments, the target range associated with a given measurement point may be the range associated with the given measurement point that has a predefined size and in which the given measurement point is located. In this example, the predefined size is related to the distance the measurement point extends.

In examples where the distance by which a given measurement point expands outward is determined based on user input, the predefined size of the range associated with the given measurement point may also be determined based on user input. The predefined size of the target range associated with different measurement points may be the same or different. Using the same predefined size range for different measurement points may improve the efficiency of cropping the target graphic based on the target range with which the measurement points are associated.

As an example, the electronic device 110 determines a square area with a length of two times the distance (denoted by r) centered at the position of a given measurement point as the target range. As shown in fig. 3, the electronic device 110 may determine a square area with twice r as a side length centered on the measurement point 302 as the target range 312 of the measurement point 302. Similarly, the electronic device 110 may determine a square area centered at the measurement point 304 and having two sides r as a side length as the target range 314 for the measurement point 304. In this example, the target range 312 and the target range 314 are square regions of the same area. It should be understood that the extended distances for measurement point 302 and measurement point 304 may be different in some embodiments. In other words, the areas of the target range 312 and the target range 314 may also be set to different areas.

Next, the electronic device 110 may determine the pattern in the layout 120 within the target range as the target pattern corresponding to the given measurement point. For example, the electronic device 110 may determine a portion of an intersection of the target range associated with a given measurement point and the graphic associated with the given measurement point as the target graphic.

As shown in the layout 320 in FIG. 3, the electronic device 110 determines the portion of the intersection of the target range 312 for the measurement point 302 and the graphic 122 as a target graphic 322 corresponding to the measurement point 302. Similarly, the electronic device 110 determines the portion of the intersection of the target range 314 for the measurement point 304 and the graphic 124 as the target graphic 324 corresponding to the measurement point 304.

It should be understood that although in the example of fig. 3, the

target graphics

322 and 324 are shown as rectangles, this is merely exemplary and the target graphics may be any shape of graphics. The target pattern determines the pattern and size of devices or traces on the wafer. For example, the target pattern may be rectangular, square, circular, and the like. The scope of the present disclosure is not limited in this respect.

An example of determining a plurality of target features in layout 120 for a plurality of measurement points in layout 120 is described above in connection with fig. 3. In the OPC process, the target graph is optimized based on a group of symmetrical measuring points corresponding to the target graphs, and further layout optimization is achieved.

With continued reference to FIG. 2, at block 220, the electronic device 110 determines a first set of measurement points having a first symmetry from the plurality of measurement points by applying a first operation corresponding to the first symmetry to the plurality of target graphics, respectively. Still taking FIG. 3 as an example, the electronic device 110 may apply a first operation corresponding to the first symmetry to the target feature 312 and the target feature 314, respectively, in the layout 320 to determine whether the measurement point 302 and the measurement point 304 have the first symmetry. If measurement points 302 and 304 have a first symmetry, electronic device 110 may determine

measurement points

302 and 304 as a first set of measurement points.

In some embodiments, the electronic device 110 applies a first operation to a first target graphic of the plurality of target graphics to obtain a transformed first target graphic. The first target pattern corresponds to a first measurement point of the plurality of measurement points. The first operation may be various types of symmetric operations, including, but not limited to, a symmetric operation (also referred to as a mirror symmetric operation) about a horizontal axis (also referred to as an x-axis), a vertical axis (also referred to as a y-axis), a clockwise or counterclockwise rotation operation about a center point of the first target figure, and the like. The rotation angle of the rotation operation can be customized, for example, 45 °, 90 °, 180 °, 270 °, 315 °, and the like. Accordingly, the position of the first measurement point corresponding to the first target pattern is also changed after the first operation.

Fig. 4 illustrates a schematic diagram of determining a first set of measurement points having a first symmetry from a plurality of measurement points, according to some embodiments of the present disclosure. Taking the layout 320 in fig. 3 as an example, the electronic device 110 applies a first operation (e.g., a y-axis symmetry operation) to the target pattern 322 in the layout 320 to obtain a transformed target pattern 422 in the layout 420. The target pattern 322 is also referred to herein as a first symmetric pattern and the measurement points 302 are also referred to as first measurement points.

Similarly, the electronic device 110 may apply a first operation to the target graphic 324, which may result in a transformed target graphic 424 in the layout 420. In some embodiments, the position of the measurement point 302 changes after the first operation as compared to the target graphic 322 for the target graphic 422 in the layout 420. For example, after the measurement point 302 of the target graphic 322 located at the left edge position is subjected to the y-axis symmetry operation, the corresponding measurement point 402 in the layout 420 is located at the right edge position of the target graphic 422. The measurement points 402 corresponding to the target feature 422 are symmetric about the y-axis with the measurement points 302 corresponding to the target feature 322.

Similarly, after the measurement point 304 of the target graphic 324 at the right-side edge position is subjected to the y-axis symmetry operation, the corresponding measurement point 404 in the layout 420 is located at the left-side edge position of the target graphic 424. The measurement points 304 corresponding to the target feature 324 are symmetric about the y-axis with the measurement points 404 corresponding to the target feature 424.

Next, the electronic device 110 determines whether the transformed first target graphic matches a second target graphic of the plurality of target graphics. The second target pattern corresponds to a second measurement point of the plurality of measurement points. For example, the second target graphic may be the target graphic 324. Accordingly, the second measurement point may be measurement point 304.

In some embodiments, if the target feature 422 (i.e., the transformed first target feature) in the layout 420 is the same as the target feature 324 (i.e., the second target feature) in the layout 320, e.g., the pattern and size are the same, the electronic device 110 determines that the target feature 422 matches the target feature 324. In other words, if the position of the measurement point 402 relative to the target graphic 422 is the same as the position of the measurement point 304 relative to the target graphic 324, e.g., both located at the end positions of the right long side of the rectangle in the example of fig. 4, the electronic device 110 determines that the target graphic 422 matches the target graphic 324.

Similarly, if the target feature 424 in the layout 420 is the same as the target feature 322 in the layout 320, the electronic device 110 determines that the target feature 424 matches the target feature 322. In other words, if the position of the measurement point 404 relative to the target graphic 422 is the same as the position of the measurement point 302 relative to the target graphic 322, e.g., at the end position of the left long side of the rectangle in the example of fig. 4, the electronic device 110 determines that the target graphic 424 matches the target graphic 322.

In some embodiments, if the electronic device 110 determines that the transformed first target pattern matches the second target pattern, the electronic device 110 groups the first measurement point and the second measurement point into a first set of measurement points. In the example of fig. 4, electronic device 110 groups measurement points 302 and measurement points 304 into a first set of measurement points.

In some embodiments, if the electronic device 110 determines that the transformed first target pattern does not match the second target pattern, the electronic device 110 determines that the first measurement point and the second measurement point cannot be grouped into the first set of measurement points. As an example, fig. 5 shows a schematic diagram of determining that a plurality of measurement points do not belong to a first set of measurement points, according to some embodiments of the present disclosure. As shown in FIG. 5, a first operation (e.g., a y-axis symmetric operation) is applied to each target feature in layout 510, resulting in layout 550.

Specifically, a first operation is applied to target graphic 522 to arrive at target graphic 562 in layout 550. The measurement point 532 associated with target graphic 522 will become the measurement point 572 associated with target graphic 562. Similarly, a first operation is applied to target graphic 524 to obtain target graphic 564 in layout 550. The measurement point 534 associated with the target graphic 524 will become the measurement point 574 associated with the target graphic 564. Comparing target pattern 562 to each of the target patterns in layout 510 may determine that there are no target patterns in layout 510 that match target pattern 562. In addition, there is no target feature in layout 510 that matches target feature 564. In such a case, measurement points 532 and 534 would not be grouped into the first set of measurement points.

Several examples of performing a first operation corresponding to a first symmetry on the target pattern to determine a first set of measurement points are described in the examples of fig. 4 and 5, taking the y-axis symmetry operation as an example. In some embodiments, the first symmetry may be any symmetry. The first operation may also be an arbitrary symmetry operation. 6A-6I illustrate schematic diagrams of a first operation of applying a first symmetry to a target graphics, according to some embodiments of the present disclosure. In the example of fig. 6A-6I, the target graphic is shown as having the shape of the letter "R". It should be understood that this graphic shape of the letter "R" is merely exemplary and not limiting, and the target graphic may be an image or graphic of any other shape. The scope of the present disclosure is not limited in this respect.

As an example, FIG. 6A illustrates a schematic diagram of applying symmetric operations about the x-axis to a target graphic. The two target patterns before and after the symmetry operation in fig. 6A have x-axis symmetry. FIG. 6B shows a schematic diagram of the application of operations about the y-axis to a target graphic. The two target patterns before and after the symmetry operation in fig. 6B have y-axis symmetry.

Fig. 6C shows a schematic diagram of an operation of applying an operation of rotating 90 ° counterclockwise based on the center point of the target graphic to the target graphic. The two target patterns before and after the symmetric operation in fig. 6C have counterclockwise rotational symmetry along 90 °. Fig. 6D shows a schematic diagram of applying an operation of rotating 180 ° counterclockwise based on the center point of the target graphic or an operation of being symmetrical about the x-axis and the y-axis to the target graphic. The two target patterns before and after the symmetry operation in fig. 6D have counterclockwise rotational symmetry along 180 ° or have symmetry about the x-axis and the y-axis. Fig. 6E illustrates a schematic diagram of an operation of applying an operation of rotating counterclockwise by 270 ° based on the center point of the target graphic to the target graphic. The two target patterns before and after the symmetric operation in fig. 6E have counterclockwise rotational symmetry along 270 °. Fig. 6F shows a schematic diagram of an operation of applying an operation of rotating counterclockwise by 45 ° based on the center point of the target graphic to the target graphic. The two target patterns before and after the symmetric operation in fig. 6F have counterclockwise rotational symmetry along 45 °. Fig. 6G shows a schematic diagram of an operation of applying counterclockwise rotation of 315 ° based on the center point of the target graphic to the target graphic. The two target patterns before and after the symmetric operation in fig. 6G have counterclockwise rotational symmetry along 315 °.

Fig. 6H shows a schematic diagram of mirror symmetry operation with an axis of 315 ° to the target graphic application. The two target patterns before and after the symmetry operation in fig. 6H have symmetry along the axis of 315 °. Fig. 6I shows a schematic diagram of mirror symmetry operation with an axis of 45 ° applied to the target graphic. The two target patterns before and after the symmetry operation in fig. 6I have symmetry along an axis of 45 °. In some embodiments, applying the symmetry operation to the target graphics further comprises an invariant operation (also referred to as a copy operation). The unchanged target graph is consistent with the original target graph.

Several examples of applying symmetry operations to target graphics are described above. It should be understood that the various examples described above are merely exemplary. Any rotation angle may be used to rotate the target pattern. The target pattern may also be symmetrically manipulated with any angle of the axis.

With continued reference to FIG. 2, at block 230, the electronic device 110 optimizes the layout based at least on the first set of measurement points such that the first set of measurement points maintains a first symmetry in the optimized layout. Optimizing the layout refers herein to reducing imaging costs by changing patterns in the layout (e.g., moving the pattern as a whole, moving a portion of the pattern, changing the distance between different patterns, etc.). Specifically, at block 230, the relationships between the first set of measurement points are taken into account in changing the graphics in the layout. In performing layout optimization, the amount of movement of optical signals and/or pattern components (e.g., edges) associated with the first set of measurement points may be considered.

For example, in some embodiments, the electronic device 110 may optimize the layout based on predicted optical signals for wafer locations corresponding to the first set of measurement points.

In some embodiments, for each measurement point in the first set of measurement points, the electronic device 110 determines a predicted optical signal for the wafer position corresponding to the measurement point. As an example, the optical signal may be the light intensity itself. Alternatively, the light signal may be other forms of light intensity, such as the square of the light intensity, the logarithm of the light intensity, or other parameters related to the light intensity. In the example of fig. 4, the electronic device 110 determines predicted optical signals at wafer locations corresponding to

measurement points

302 and 304. The predicted light signals corresponding to the various measurement points may be determined in any suitable manner (e.g., formulaic calculations, model predictions, etc.). The scope of the present disclosure is not limited in this respect.

In some embodiments, the electronic device 110 determines the target light signal based on predicted light signals respectively determined for the first set of measurement points. As an example, the target light signal may be an average or a weighted average of the predicted light signals of the first set of measurement points. The target light signal may also be any predicted light signal selected by a user from the respective predicted light signals of the first set of measurement points. In some embodiments, the target light signal may be obtained by any suitable processing or calculation of the predicted light signals for the first set of measurement points. In the example of fig. 4, the target light signal may be an average or weighted average of the predicted light signal of measurement point 302 and the predicted light signal of measurement point 304. Alternatively, in some embodiments, the target optical signal may be a predicted optical signal for measurement point 302, or a predicted optical signal for measurement point 304. The scope of the present disclosure is not limited in this respect.

Next, the electronic device 110 may optimize the graphical component at the first set of measurement points based on the target light signal. For example, in OPC, the electronic device 110 may calculate the distance and direction of movement of the graphical component at the first set of measurement points based on the target optical signal. The graph component may be an edge at a first set of measurement points of the target graph. The electronic device 110 may calculate the distance and direction moved by the edge at the first set of measurement points based on the target light signal.

In the example of fig. 4, the electronic device 110 may optimize the measurement point 302 and the graphical components at the measurement point 304 based on the target light signal. For example, the electronic device 110 may calculate the distance and direction moved by the sides of the rectangle at the measurement point 302 of the target graphic 322 based on the target light signal. The electronic device 110 may in turn move the edge according to the determined distance and direction. Similarly, the electronic device 110 may calculate, based on the target light signal, the distance and direction that the side of the rectangle at the measurement point 304 of the target pattern 324 moves, and in turn move the side accordingly.

In some embodiments, the electronic device 110 may determine the direction and distance of movement of the graphical component at the measurement point by bringing the moved predicted light signal closer to the target light signal. Taking the measurement point 302 as an example, the electronic device 110 may determine a predicted light signal function for the location of the predicted point 302. The distance and direction of movement for the edge at the measurement point 302 may be a parameter of the predicted light signal function. The electronic device 110 may determine the direction and distance of movement for the edge by bringing the predicted light signal close to or equal to the target light signal.

It should be understood that although in the examples of fig. 3-4, measurement points 302 and 304 are located on graphical components of the target graphic, in some embodiments, measurement points may not be located on any graphical component. In such an example, the graph component closest to the measurement point, e.g., the edge, may be determined as the graph component at the measurement point.

By optimizing different target patterns based on the same target optical signal, the optical signals at the measurement points of the optimized target patterns can be kept consistent. In this way, the first symmetry can be maintained for each graphic on the optimized layout. Several examples of determining the moving direction and distance for each measurement point, respectively, and moving the graphic components at each measurement point, respectively, are described above. In some embodiments, the electronic device 110 may determine, for each measurement point in the first set of measurement points, an optimized operation for the graphic component at the measurement point. The electronic device 110, in turn, can determine a target optimization operation based on the optimization operations respectively determined for the first set of measurement points.

As an example, the electronic device 110 may determine the movement distance for the graphical component at each measurement point separately. The electronic device 110 may determine the target movement distance for the target optimization operation as an average, a weighted average, or a distance value determined via other suitable calculations of the movement distances of the graphical component at all measurement points, and so on. It should be understood that the scope of the present disclosure is not limited in the determination of the distance of movement. In this way, the graphic components corresponding to different measurement points can be moved the same distance.

Additionally or alternatively, in some embodiments, the electronic device 110 also determines a direction of movement for the graphical component at each measurement point, respectively. The electronic device 110, in turn, can determine a direction of movement for the target optimization operation based on various directions of movement for the graphical component at the first set of measurement points. The moving direction of the target optimization operation for the figure component at different measurement points may be different, that is, may be the moving direction determined separately for the figure component at each measurement point.

By adopting the scheme of the disclosure, the layout can be optimized through the first group of measurement points with the first symmetry, so that the optical signals at the wafer positions corresponding to each measurement point in the first group of measurement points are kept consistent. In this way, the first symmetry can be maintained for each target feature in the optimized layout, which in turn enables the symmetry to be maintained for the actual features on the wafer corresponding to the plurality of target features as well.

In some embodiments, the electronic device 110 may further determine a second set of measurement points having a second symmetry from the plurality of measurement points by applying a second operation corresponding to the second symmetry to the plurality of target graphics, respectively. The second symmetry may be a symmetry different from the first symmetry. For example, if the first symmetry is symmetry with respect to the y-axis, the second symmetry may be symmetry with respect to the x-axis, as well as various symmetries described with reference to fig. 6A-6I, or other symmetries not shown. The second operation may be an operation corresponding to the second symmetry, such as operating the various symmetric operations described in fig. 6A-6I.

In an example where the second operation is applied to the plurality of target graphics, respectively, the electronic device 110 further optimizes the layout based on the second set of measurement points such that the second set of measurement points maintains a second symmetry in the optimized layout. The process of optimizing the layout based on the second set of measurement points is similar to the process of optimizing the layout based on the first set of measurement points and will not be described again. The layout may be further optimized by applying a second operation to the target feature and optimizing the layout based on the second set of measurement points. The target graph in the optimized layout obtained in the mode meets the first symmetry and the second symmetry, and therefore the quality of the layout is further improved.

It will be appreciated that in fact, various operations corresponding to various symmetries may be applied separately to multiple target patterns to obtain multiple sets of measurement points that satisfy the symmetry requirements. The layout is optimized based on a plurality of groups of measuring points, so that the target graph in the optimized layout can meet various symmetries, and the quality of the layout is further improved.

FIG. 7 illustrates a schematic diagram of the results of processing a layout according to some embodiments of the present disclosure. As shown in fig. 7, the layout 700 is a processed layout obtained by processing the layout according to a conventional asymmetric scheme. A plurality of

original graphics

710, 720, 730, and 740 are shown in layout 700. Also shown in the layout 700 are optimized

graphs

715, 725, 735, and 745 obtained by optimizing each original graph with an asymmetric scheme. The optimized graph obtained by the traditional scheme is asymmetric relative to each measuring point. This processing method results in different signal strengths at the wafer positions corresponding to the respective measurement points.

Also shown in FIG. 7 is an optimized layout 750 resulting from processing the layout according to an embodiment of the disclosure. In layout 750, optimized

graphics

765, 775, 785, and 795 are shown for a plurality of

original graphics

710, 720, 730, and 740, respectively, optimized for symmetry according to the present disclosure. The optimized graph obtained by adopting the scheme of the disclosure is symmetrical relative to each measuring point. Therefore, the signal intensity of the wafer position corresponding to each measuring point is the same. Thus, the layout meeting the symmetry requirement can be obtained, and the quality of the layout is improved.

Fig. 8 illustrates a block diagram of an electronic device/server 800 in which one or more embodiments of the disclosure may be implemented. The electronic device/server 800 may be used, for example, to implement the electronic device 110 shown in fig. 1. It should be understood that the electronic device/server 800 illustrated in fig. 8 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein in any way.

As shown in fig. 8, the electronic device/server 800 is in the form of a general-purpose electronic device. The components of electronic device/server 800 may include, but are not limited to, one or more processors or processing units 810, memory 820, storage 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860. The processing unit 810 may be a real or virtual processor and can perform various processes according to programs stored in the memory 820. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to increase the parallel processing capabilities of the electronic device/server 800.

Electronic device/server 800 typically includes a number of computer storage media. Such media may be any available media that is accessible by electronic device/server 800 and includes, but is not limited to, volatile and non-volatile media, removable and non-removable media. The memory 820 may be volatile memory (e.g., registers, cache, random Access Memory (RAM)), non-volatile memory (e.g., read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory), or some combination thereof. Storage device 830 may be a removable or non-removable medium and may include a machine-readable medium, such as a flash drive, a diskette, or any other medium, which may be capable of being used to store information and/or data (e.g., training data for training) and which may be accessed within electronic device/server 800.

The electronic device/server 800 may further include additional removable/non-removable, volatile/nonvolatile storage media. Although not shown in FIG. 8, a magnetic disk drive for reading from or writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data media interfaces. Memory 820 may include a computer program product 825 having one or more program modules configured to perform the various methods or acts of the various embodiments of the disclosure.

The communication unit 840 enables communication with other electronic devices through a communication medium. Additionally, the functionality of the components of the electronic device/server 800 may be implemented in a single computing cluster or multiple computing machines, which are capable of communicating over a communications connection. Thus, electronic device/server 800 may operate in a networked environment using logical connections to one or more other servers, network Personal Computers (PCs), or another network node.

Input device 850 may be one or more input devices such as a mouse, keyboard, trackball, or the like. The output device(s) 860 may be one or more output devices such as a display, speakers, printer, or the like. Electronic device/server 800 may also communicate with one or more external devices (not shown), such as storage devices, display devices, etc., with one or more devices that enable a user to interact with electronic device/server 800, or with any device (e.g., network card, modem, etc.) that enables electronic device/server 800 to communicate with one or more other electronic devices, as desired, via communication unit 840. Such communication may be performed via input/output (I/O) interfaces (not shown).

According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, having one or more computer instructions stored thereon, wherein the one or more computer instructions are executed by a processor to implement the above-described method.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products implemented in accordance with the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing has described implementations of the present disclosure, and the above description is illustrative, not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The terminology used herein was chosen in order to best explain the principles of implementations, the practical application, or improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the implementations disclosed herein.

Claims

1. A layout processing method is characterized by comprising the following steps:

determining a plurality of target patterns in a layout for a plurality of measurement points in the layout, wherein each target pattern corresponds to one measurement point and is within a range associated with the measurement point;

determining a first set of measurement points from the plurality of measurement points having a first symmetry by applying a first operation corresponding to the first symmetry to the plurality of target graphics, respectively, wherein determining the first set of measurement points from the plurality of measurement points having the first symmetry comprises:

applying the first operation to a first target graphic of the plurality of target graphics to obtain a transformed first target graphic, the first target graphic corresponding to a first measurement point of the plurality of measurement points;

determining whether the transformed first target pattern matches a second target pattern of the plurality of target patterns, the second target pattern corresponding to a second measurement point of the plurality of measurement points; and

in response to determining that the transformed first target pattern matches the second target pattern, grouping the first measurement point and the second measurement point into the first set of measurement points; and

optimizing the layout based at least on the first set of measurement points such that the first set of measurement points maintains the first symmetry in the optimized layout.

2. The layout processing method according to claim 1, wherein determining a plurality of target patterns in the layout for a plurality of measurement points in the layout comprises:

determining a distance extending outward from a measurement point of the plurality of measurement points;

for a given measurement point of the plurality of measurement points, determining a target range associated with the given measurement point based on the location of the given measurement point and the distance; and

and determining the graph in the target range in the layout as a target graph corresponding to the given measuring point.

3. The layout processing method according to claim 2, wherein determining a distance extending outward from a measurement point of the plurality of measurement points comprises:

obtaining a user input specifying the distance; and

reading the distance from the user input.

4. The layout processing method according to claim 2, wherein the distance is smaller than a size of a simulation window indicating a layout range involved in the optimization.

5. The layout processing method according to claim 2, wherein determining a target range associated with the given measurement point comprises:

and determining a square area with the position of the given measuring point as the center and the double distance as the side length as the target range.

6. The layout processing method according to claim 1, wherein optimizing the layout based on at least the first set of measurement points comprises:

for each measurement point in the first set of measurement points, determining a predicted optical signal for a wafer position corresponding to the measurement point;

determining a target light signal based on the predicted light signals respectively determined for the first set of measurement points; and

optimizing a graph component at the first set of measurement points based on the target light signal.

7. The layout processing method according to claim 1, wherein optimizing the layout based on at least the first set of measurement points comprises:

for each measurement point in the first set of measurement points, determining an optimization operation for a graphical component at the measurement point;

determining a target optimization operation based on the optimization operations respectively determined for the first set of measurement points; and

performing the target optimization operation on the graph components at each measurement point in the first set of measurement points.

8. The layout processing method according to claim 1, characterized in that the layout processing method further comprises:

determining a second set of measurement points having a second symmetry from the plurality of measurement points by applying a second operation corresponding to the second symmetry to the plurality of target graphics, respectively; and is

Wherein optimizing the layout is further based on the second set of measurement points such that the second set of measurement points maintains the second symmetry in the optimized layout.

9. The layout processing method according to claim 1, wherein the range associated with the measurement point has a predefined size and the measurement point is located within the range.

10. An electronic device, comprising:

at least one processing unit; and

at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions when executed by the at least one processing unit cause the electronic device to perform the method of any of claims 1-9.

11. A computer-readable storage medium, on which a computer program is stored, the computer program being executable by a processor for implementing the method according to any one of claims 1 to 9.