CN115576100A - Design method of on-chip mode converter based on reverse design - Google Patents
Design method of on-chip mode converter based on reverse design Download PDFInfo
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Abstract
The invention discloses a design method of an on-chip mode converter based on reverse design, which is characterized by comprising the steps of designing an initial structure of the on-chip mode converter from left to right to sequentially form an input waveguide, a polygonal design area and an output waveguide, and respectively inserting a plurality of discrete optimization points x into the upper boundary, the lower boundary or the upper and lower boundaries of the design area; performing first forward transmission simulation and second accompanying simulation on the mode converter by using a three-dimensional time domain finite difference method, correspondingly acquiring an initial electric field and an accompanying electric field, and calculating a figure of merit change value delta FOM of an optimization point; and finally, iteratively calculating the positions of the edge optimization points on the y axis by using a calculation formula until the delta FOM is less than 1 multiplied by 10 ‑5 Namely, designing the required on-chip mode converter, has the advantages of short time consumption, high design efficiency, small size of the designed product, low loss, large working bandwidth and high conversion efficiency。
Description
Technical Field
The invention belongs to the intelligent design of a silicon-based photonic device, and particularly relates to an on-chip mode converter based on reverse design and a test method.
Background
The rapid development of digital information technology has made higher demands on the transmission capacity and energy consumption of data centers. In order to realize the on-chip data transmission with high capacity, low loss and low cost, a mode multiplexing/demultiplexing technology based on a silicon-based photonic platform becomes a research hotspot in scientific research and industrial fields. Among them, a silicon-based mode converter with high conversion efficiency and low loss is an important prerequisite for realizing the technology.
The mode converters reported at present mostly adopt the traditional design method, and utilize specific structures, such as tapered directional coupler, asymmetric Y-branch, and multi-mode interference coupler, etc., to implement the on-chip mode conversion. However, the three device sizes are usually large, and the design method adopted is often dependent on the experience of the designer, and a lot of time is consumed in structural design and parameter optimization. In addition, when the design target, i.e. the target pattern, changes, the structure often needs to be redesigned and optimized, and a large amount of repetitive work causes the design efficiency to be low. Therefore, the problems of the on-chip mode converter in terms of device size, conversion efficiency, etc. need to be solved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a design method of an on-chip mode converter based on reverse design, which has the advantages of short time consumption, high design efficiency and relatively low design complexity, and the mode converter has good performances of small size, low loss, large working bandwidth and high conversion efficiency.
The technical scheme adopted by the invention for solving the technical problems is as follows: a design method of an on-chip mode converter based on reverse design comprises the following steps:
(1) Designing an initial structure of the on-chip mode converter, namely sequentially arranging an input waveguide, a polygonal design area for mode conversion and an output waveguide from left to right;
(2) Establishing a plane coordinate system, inserting a plurality of discrete optimization points x into the upper boundary or the lower boundary or the upper and lower boundaries of the polygonal design area in the step (1), and performing edge optimization on the mode converter by adjusting the positions of the optimization points x in the y-axis direction;
(3) A light source is positively transmitted to an output waveguide from an input waveguide, a Three-dimensional finite-difference time-domain (3D-FDTD) method is utilized to carry out first positive transmission simulation on a mode converter, and an initial electric field tangential component E at an optimized point in a design area is obtained || (x) And the normal component D of the initial potential shift vector ⊥ (x)；
(4) Placing a light source on an input waveguide on the section of an output waveguide, radiating the light source to an optimization point in a reverse direction, performing secondary adjoint simulation by using a three-dimensional time domain finite difference method, and obtaining a tangential component of an adjoint electric field at the optimization point in a design region
And the normal component of the accompanying displacement vector
(5) And calculating the quality factor change value delta FOM of the optimization point x according to the following calculation formula:
(6) Performing edge shape optimization on the mode converter by continuously adjusting the position of the optimization point x in the y-axis direction, specifically, in a Python programming language, performing iterative calculation on the positions of the inserted optimization points x in the y-axis direction by using the calculation formula in the step (5) until the delta FOM of all the inserted discrete optimization points is less than 1 × 10 -5 I.e. to design the required on-chip mode converter. At this time, the transverse electric field first order mode (TE) in the output optical field 1 ) Normalized power of (1), normalized power = output power/source power, and no loss is equal to 1.
Further, the step (3) is specifically to forward-transmit the light source from the input waveguide to the output waveguide, perform a first forward-transmit simulation on the mode converter by using a Three-dimensional time-domain finite difference method (3D-FDTD), acquire an initial electric field E (x) and an initial electric displacement vector D (x) at an optimized point in the design area by using lumeric software, and calculate and acquire a tangential component E (x) of the initial electric field at the optimized point in the design area by using a Python programming language || (x) And the normal component D of the initial potential shift vector ⊥ (x)。
Further, the step (4) is specifically as follows: placing a light source on an input waveguide on the section of an output waveguide, radiating the light source to an optimization point in a reverse direction, performing secondary adjoint simulation by using a three-dimensional time domain finite difference method, and acquiring an adjoint electric field E at the optimization point in a design area by using Lumerical software adj (x) And a concomitant displacement vector D adj (x) And then, calculating and obtaining the tangential component of the concomitant electric field at the optimized point in the design region by utilizing a Python programming language
And the normal component of the accompanying displacement vector
Further, the width of the input waveguide is 0.5 μm, and the width of the output waveguide is 1.5 μm.
Further, the input waveguide, the polygonal design region and the output waveguide are all made of silicon.
Further, the overall thickness of the on-chip mode converter is 220nm and its upper layer is covered with a 1 μm thick silica cladding.
Further, the coupling length of the on-chip mode converter is 12-30 μm.
Compared with the prior art, the invention has the advantages that: the invention relates to a design method of an on-chip mode converter based on reverse design, which utilizes the reverse design method to ensure that the mode converter has the advantages of wide bandwidth, low loss, high conversion efficiency, high design efficiency and the like while occupying smaller device space size; through the designed mode converter, an on-chip test structure can be designed, the conversion efficiency of the mode converter can be directly tested, a complex external test system does not need to be accessed, for example, an infrared CCD (charge coupled device) does not need to be accessed to capture an output light field, the design method has the advantages of short time consumption, high design efficiency and relatively low design complexity, and the designed mode converter has the advantages of high design efficiency, wide bandwidth, low loss, high conversion efficiency and the like.
Drawings
FIG. 1 is a flow chart of the design of an on-chip mode converter based on reverse design according to the modified corresponding adjustment;
FIG. 2 shows TE optimized based on the adjoint method 0 -TE 1 A converter structure schematic diagram;
FIG. 3 shows TE of the present invention 0 -TE 1 Different coupling lengths of the converter simulate output power at the central wavelength of 1550nm and test output power graphs at the central wavelength of 1550nm with coupling lengths of 12 microns, 16 microns and 20 microns;
FIG. 4 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 16 mu m, and an electric field graph is simulated at 1550 nm;
FIG. 5 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 16 mu m, and a power curve graph is simulated and output in the working bandwidth of 1500 nm-1600 nm;
FIG. 6 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 12 mu m, and an output power curve graph is tested in a 1500 nm-1565 nm working bandwidth;
FIG. 7 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 12 mu m, and an insertion loss curve graph is tested in a 1500 nm-1565 nm working bandwidth;
FIG. 8 shows TE of the present invention 0 -TE 1 Testing an output power curve diagram within the working bandwidth of 1500 nm-1565 nm when the coupling length of the converter is 16 mu m;
FIG. 9 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 16 mu m, and an insertion loss curve graph is tested in a 1500 nm-1565 nm working bandwidth;
FIG. 10 shows TE of the present invention 0 -TE 1 Testing an output power curve diagram within the working bandwidth of 1500 nm-1565 nm when the coupling length of the converter is 20 microns;
FIG. 11 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 20 μm, and an insertion loss curve diagram is tested in the working bandwidth of 1500 nm-1565 nm.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
1. Detailed description of the preferred embodiments
A method for designing an on-chip mode converter based on inverse design, as shown in fig. 1, includes the following steps:
the method comprises the following steps: designing an initial structure of the on-chip mode converter, namely sequentially arranging an input waveguide, a polygonal design area for mode conversion and an output waveguide from left to right;
step two: establishing a plane coordinate system, wherein a design area is 10 microns multiplied by 1.5 microns, inserting 100 discrete optimization points x into the upper and lower boundaries of the design area respectively, and performing edge optimization on the mode converter by adjusting the positions of the optimization points x in the y-axis direction;
step three: forward-transmitting a light source from an input waveguide to an output waveguide, and feeding a mode converter by using a Three-dimensional time-domain finite difference method (3D-FDTD)Carrying out a first forward transmission simulation to obtain an initial electric field E of a tangential component at an optimized point in a design area || (x) And normal component initial magnetic field D ⊥ (x) (ii) a The method specifically comprises the steps of forward transmitting a light source from an input waveguide to an output waveguide, performing first forward transmission simulation on a mode converter by using a Three-dimensional time-domain finite difference method (3D-FDTD), acquiring an initial electric field E (x) and an initial electric displacement vector D (x) at an optimization point in a design area by using Lumerical software, and calculating by using a Python programming language to acquire a tangential component E (E) of the initial electric field at the optimization point in the design area || (x) And the normal component D of the initial potential shift vector ⊥ (x)。
Step four: placing a light source on an input waveguide on the section of an output waveguide, radiating the light source to an optimization point in a reverse direction, performing secondary adjoint simulation by using a three-dimensional time domain finite difference method, and obtaining a tangential component adjoint electric field at the optimization point in a design region
Normal component associated magnetic field
The method specifically comprises the following steps: placing a light source on an input waveguide on the section of an output waveguide, radiating the light source to an optimization point in a reverse direction, performing secondary adjoint simulation by using a three-dimensional time domain finite difference method, and acquiring an adjoint electric field E at the optimization point in a design area by using Lumerical software adj (x) And a concomitant displacement vector D adj (x) And then, calculating and obtaining the tangential component of the concomitant electric field at the optimized point in the design region by utilizing a Python programming language
And the normal component of the accompanying displacement vector
Step five: calculating a quality factor change value delta FOM of the optimization point x, wherein the calculation formula is as follows:
step six: performing edge shape optimization on the mode converter by continuously adjusting the position of the optimization point x in the y-axis direction, specifically in a Python programming language, performing iterative computation on the positions of the inserted optimization points x in the y-axis direction by using a step five computation formula until the delta FOM of all the inserted discrete optimization points is less than 1 × 10 -5 I.e. designing the required on-chip mode converter (TE) 0 -TE 1 A converter). At this time, the transverse electric field first order mode (TE) in the output optical field 1 ) Normalized power of (1), normalized power = output power/source power, and no loss is equal to 1. Will have a transverse electric field fundamental mode (TE) 0 ) Incident from the left input waveguide, the design objective can be represented by a figure of merit FOM, defined as TE in the output optical field 1 Normalized power of the mode. The figure of merit change Δ FOM is a figure of merit change value measured by two adjacent position changes of any one of the optimization points in the y-axis direction.
FIG. 2 shows TE optimized based on the adjoint method 0 -TE 1 The converter structure is schematic. The mode conversionThe optimal boundary parameters are obtained through 30 iterations by using a reverse design method, and the required mode converter is obtained.
The width of the input waveguide is 0.5 μm, and the width of the output waveguide is 1.5 μm. The input waveguide, the polygonal design region and the output waveguide are all made of silicon. The overall on-chip mode converter thickness was 220nm and its upper layer was covered with a 1 μm thick silica cladding.
2. Analysis of results
1、TE 0 -TE 1 Partial description of simulated output power of converter with different coupling lengths
FIG. 3 shows TE of the present invention 0 -TE 1 Different coupling lengths of the converter the output power was simulated at a central wavelength of 1550nm and the output power plots were tested at 1550nm with coupling lengths of 12, 16 and 20 μm. The coupling length of the mode converter is set to be in the range of 12 μm to 30 μm. In the coupling length range, TE 0 -TE 1 The output power of the upper port (indicated by the arrow in (1) in fig. 4) and the output power of the lower port (indicated by the arrow in (3) in fig. 4) of the converter fluctuate at-3 dB, and the performance is stable. The output power of the intermediate port (in the manner indicated by the arrow (2) in fig. 4) remains below-29.4 dB and there is substantially no coupled light in the intermediate waveguide. In the figure, the output power of the upper port and the lower port tested at 1550nm with the coupling lengths of 12 microns, 16 microns and 20 microns is basically consistent with the corresponding simulated output power, and the test output power of the middle port has larger loss than the corresponding simulated output power. TE 0 -TE 1 Different coupling lengths of the converters do not affect the output splitting ratio.
FIG. 4 shows TE of the present invention 0 -TE 1 The transducer coupling length was 16 μm simulating the electric field pattern at 1550 nm. TE (TE) 0 Entering from the input waveguide, passing through the design region, and converting into TE 1 . TE completion at (a) of the figure 0 Conversion to TE 1 (b) treating TE 1 Into the upper and lower waveguides at the coupling portion (c), respectively. Wherein, the phase positions of the two mode spots in the upper and lower waveguides are kept unchanged and differ by pi. (d) The rectangular waveguide structure ensures that two mode spots in the upper waveguide and the lower waveguide are not coupled with each other. In the figure, (1), (3) are the upper and lower waveguide mode spots, respectively, and (2) is the intermediate waveguide, which has almost no coupled light.
FIG. 5 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 16 mu m, and a curve graph of the output power is simulated in the working bandwidth of 1500 nm-1600 nm. Within the working bandwidth of 1500 nm-1600 nm, the output power of the upper and lower ports fluctuates at the-3 dB position, and the output power of the middle waveguide is kept below-17.2 dB. At the central wavelength of 1550nm, the output power of the upper port, the output power of the lower port and the output power of the middle port are-2.9 dB, -3.0dB and-28.9 dB respectively. TE 0 -TE 1 The simulated output power of the upper port and the lower port of the converter is basically kept consistent.
2、TE 0 -TE 1 The test output power and Insertion Loss (Insertion Loss) of each port with a coupling length of 12 μm, 16 μm and 20 μm respectively are described in the following sections:
the mode converter testing method comprises the following steps: aligning optical fibers above an input port and an output port of the SOI device, then injecting a tunable laser source in a wave band of 1500 nm-1600 nm into the input port, and testing the power of each output port.
FIG. 6 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 12 mu m, and an output power curve diagram is tested in the working bandwidth of 1500 nm-1565 nm. Within the 65nm working bandwidth, the output power of the upper port is kept above-4.1 dB, the output power of the lower port is kept above-4.4 dB, and the output power of the middle port is kept below-18.0 dB. At 1550nm, the output power of the upper port, the output power of the lower port and the output power of the middle port are respectively-3.2 dB, -2.6dB and-21.9 dB.
FIG. 7 shows TE according to the present invention 0 -TE 1 The coupling length of the converter is 12 mu m, and an insertion loss curve graph is tested in the working bandwidth of 1500 nm-1565 nm. The Insertion Loss (IL) expression is:
IL＝10·log 10 (T up /10+T down /10) (3)
wherein, T up 、T down Are respectively TE 0 -TE 1 Normalized output power of the upper and lower ports of the converter. IL has a numerical significance for conversion efficiency. Within a 65nm bandwidth, the insertion loss is kept at-1.2 dB toThe above.
FIG. 8 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 16 μm, and an output power curve diagram is tested in the working bandwidth of 1500 nm-1565 nm. Within the 65nm working bandwidth, the minimum output power of the upper port is-4.5 dB, the minimum output power of the lower port is-3.8 dB, and the maximum output power of the middle port is-15.0 dB. At 1550nm, the output power of the upper port, the output power of the lower port and the output power of the middle port are respectively-3.5 dB, -3.0dB and-16.8 dB.
FIG. 9 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 16 mu m, and an insertion loss curve graph is tested in the working bandwidth of 1500 nm-1565 nm. The insertion loss remains above-0.7 dB over a 65nm bandwidth.
FIG. 10 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 20 μm, and an output power curve diagram is tested in the working bandwidth of 1500 nm-1565 nm. Within the 65nm working bandwidth, the minimum output power of the upper port is-4.0 dB, the minimum output power of the lower port is-4.0 dB, and the maximum output power of the middle port is-13.7 dB. At 1550nm, the output power of the upper port, the output power of the lower port and the output power of the middle port are respectively-3.4 dB, -3.6dB and-16.0 dB.
FIG. 11 shows TE of the present invention 0 -TE 1 The coupling length of the converter is 20 μm, and an insertion loss curve diagram is tested in the working bandwidth of 1500 nm-1565 nm. The insertion loss remains above-0.9 dB over a 65nm bandwidth.
The invention provides an on-chip mode converter based on reverse design and a test method. The TE 0 -TE 1 The converter obtains the optimal boundary parameters through 30 iterations by utilizing an edge shape intelligent optimization design method, obtains the required mode converter, and realizes the performances of high design efficiency, large bandwidth, low loss, high conversion efficiency and the like of the mode converter. By applying to TE 0 -TE 1 Simulation is carried out on different coupling lengths of the converter, and the fact that the difference of the coupling lengths has no influence on output power is shown. Through experimental tests, the TE is verified 0 -TE 1 The converter can realize mode conversion with high efficiency. The invention realizes TE through two processes of simulation and test 0 -TE 1 High performance of the converter.
The above description is not intended to limit the present invention, and the present invention is not limited to the above examples. Those skilled in the art should also realize that changes, modifications, additions and substitutions can be made without departing from the true spirit and scope of the invention.
Claims (7)
1. A design method of an on-chip mode converter based on reverse design is characterized by comprising the following steps:
(1) Designing an initial structure of the on-chip mode converter, namely sequentially arranging an input waveguide, a polygonal design area for mode conversion and an output waveguide from left to right;
(2) Establishing a plane coordinate system, inserting a plurality of discrete optimization points x into the upper boundary or the lower boundary or the upper and lower boundaries of the polygonal design area in the step (1), and performing edge optimization on the mode converter by adjusting the positions of the optimization points x in the y-axis direction;
(3) The method comprises the steps of forward transmitting a light source from an input waveguide to an output waveguide, performing first forward transmission simulation on a mode converter by using a three-dimensional time domain finite difference method, and obtaining an initial electric field tangential component E at an optimization point in a design region || (x) And the normal component D of the initial potential shift vector ⊥ (x)；
(4) Placing a light source on an input waveguide on the section of an output waveguide, radiating the light source to an optimization point in a reverse direction, performing secondary adjoint simulation by using a three-dimensional time domain finite difference method, and obtaining a tangential component of an adjoint electric field at the optimization point in a design region
And the normal component of the accompanying electric displacement vector
(5) Calculating a quality factor change value delta FOM of the optimization point x, wherein the calculation formula is as follows:
(6) Performing edge shape optimization on the mode converter by continuously adjusting the position of the optimization point x in the y-axis direction, specifically, in a Python programming language, performing iterative calculation on the positions of the inserted optimization points x in the y-axis direction by using the calculation formula in the step (5) until the delta FOM of all the inserted discrete optimization points is less than 1 × 10 -5 I.e. to design the required on-chip mode converter.
2. The method according to claim 1, wherein the step (3) is specifically as follows: the method comprises the steps of forward transmitting a light source from an input waveguide to an output waveguide, performing first forward transmission simulation on a mode converter by using a three-dimensional time domain finite difference method, acquiring an initial electric field E (x) and an initial electric displacement vector D (x) at an optimization point in a design area by using a logical software, and calculating by using a Python programming language to acquire a tangential component E of the initial electric field at the optimization point in the design area || (x) And the normal component D of the initial potential shift vector ⊥ (x)。
3. An inverse design based on chip as claimed in claim 1The design method of the mode converter is characterized in that the step (4) is specifically as follows: placing a light source on an input waveguide on the section of an output waveguide, radiating reversely to an optimization point, performing secondary adjoint simulation by using a three-dimensional time domain finite difference method, and acquiring an adjoint electric field E at the optimization point in a design area by using Lumerical software adj (x) And a concomitant electric displacement vector D adj (x) And then, calculating and obtaining the tangential component of the adjoint electric field at the optimized point in the design area by utilizing a Python programming language
And the normal component of the accompanying electric displacement vector
4. The method of claim 1, wherein the method comprises: the width of the input waveguide is 0.5 μm, and the width of the output waveguide is 1.5 μm.
5. The method of claim 1, wherein the method comprises: the input waveguide, the polygonal design region and the output waveguide are all made of silicon.
6. The method of claim 1, wherein the method comprises: the overall thickness of the on-chip mode converter is 220nm and its upper layer is covered with a 1 μm thick silica cladding.
7. The method of claim 1, wherein the method comprises: the coupling length of the on-chip mode converter is 12-30 μm.
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| CN116088097B (en) * | 2023-04-12 | 2023-08-15 | 之江实验室 | Polygonal MIMO mode converter and design method |
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