CN115565569A - Read-out circuit structure - Google Patents

Abstract

The embodiment of the present application provides a readout circuit structure, which is disposed in a gap of a memory array, and includes: the structure layer, the first interconnection layer and the second interconnection layer are stacked on the top of the structure layer; the structural layer is provided with a first sensing amplification structure, a second sensing amplification structure and a balance structure; wherein one of the first bit line or the first complementary bit line is disposed in a first interconnect layer and at least a portion of the other is disposed in a second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; the equalization structure directly connects the first complementary bit line and the second bit line; the equalizing structure is arranged between the first sensing amplifier structure and the second sensing amplifier structure and is directly connected with the first complementary bit line and the second bit line in the first interconnection layer, so that the problem of low pre-charging speed is solved, and the layout area of the reading circuit structure is reduced.

Description

Read-out circuit structure

Technical Field

The present application relates to the field of memory layout design, and in particular, to a read circuit structure.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

The DRAM may be classified into a Double Data Rate (DDR) DRAM, a GDDR DRAM, and a Low Power Double Data Rate (LPDDR) DRAM. With the increasing field of DRAM application, such as the increasing application of DRAM to the mobile field, the user's requirement for DRAM power consumption index is higher and higher.

However, the performance of current DRAMs is still to be improved.

Disclosure of Invention

The embodiment of the application provides a reading circuit structure, and provides a layout structure and a wiring mode on the basis of solving the problem of low memory pre-charging speed so as to reduce the layout area of the reading circuit structure.

To solve the above technical problem, an embodiment of the present invention provides a sensing circuit structure disposed in a gap of a memory array, including: the structure layer, the first interconnection layer and the second interconnection layer are stacked on the top of the structure layer; the structural layer is provided with a first sensing amplification structure, a second sensing amplification structure and a balance structure; the first sensing amplification structure is connected with one of the adjacent storage arrays through a first bit line, the first sensing amplification structure is connected with the other of the adjacent storage arrays through a first complementary bit line, the second sensing amplification structure is connected with one of the adjacent storage arrays through a second bit line, and the second sensing amplification structure is connected with the other of the adjacent storage arrays through a second complementary bit line; wherein one of the first bit line or the first complementary bit line is disposed in a first interconnect layer and at least a portion of the other is disposed in a second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; the equalizing structure is directly connected with the first complementary bit line and the second bit line and is used for pre-charging the first bit line, the first complementary bit line, the first sensing amplifying structure, the second bit line, the second complementary bit line and the second sensing amplifying structure; wherein the equalizing structure is disposed between the first sense amplifier structure and the second sense amplifier structure and directly connected with the first complementary bit line and the second bit line in the first interconnect layer.

Compared with the prior art, the equalizing structure is directly connected with the first bit line or the first complementary bit line and used for pre-charging the first bit line and the first complementary bit line, the equalizing structure is directly connected with the second bit line or the second complementary bit line and used for pre-charging the second bit line and the second complementary bit line, the equalizing structure is directly connected with the bit lines and used for pre-charging the bit lines, the situation that the bit lines can be pre-charged only by conducting a switching transistor in the pre-charging process is avoided, and therefore the charging speed of the bit lines is accelerated; further, at least a part of one of the first bit line or the first complementary bit line is disposed in the second interconnect layer, the other is disposed in the first interconnect layer, at least a part of one of the second bit line or the second complementary bit line is disposed in the second interconnect layer, the other is disposed in the first interconnect layer, and by the stacked arrangement of the first interconnect layer and the second interconnect layer, a structure of a required layout in each layer layout is reduced, thereby reducing a layout area of the readout circuit structure.

In addition, the first bit line is disposed in the first interconnect layer, at least a portion of the first complementary bit line is disposed in the second interconnect layer, the first complementary bit line is coupled with the first sense amplifying structure after passing through a region where the second sense amplifying structure is located in the second interconnect layer, at least a portion of the second bit line is disposed in the second interconnect layer, the second bit line is coupled with the second sense amplifying structure after passing through a region where the first sense amplifying structure is located in the first interconnect layer, and the second complementary bit line is disposed in the first interconnect layer. The first complementary bit line penetrates through the area where the second sensing amplifying structure is located and is coupled with the first sensing amplifying structure, namely the first complementary bit line does not need to occupy extra layout area to complete wiring, so that the layout area of the read circuit structure is reduced, the second bit line penetrates through the area where the first sensing amplifying structure is located and is coupled with the second sensing amplifying structure, namely the second bit line does not need to occupy extra layout area to complete wiring, so that the layout area of the read circuit structure is reduced.

In addition, the equalization structure includes: a first equalizing pipe, wherein the grid electrode is used for receiving a first equalizing signal, one of the source electrode or the drain electrode is connected with the first complementary bit line, and the other one of the source electrode or the drain electrode is used for receiving a first pre-charging voltage and is used for pre-charging the first bit line, the first complementary bit line and the first sensing amplifying structure to the first pre-charging voltage based on the first equalizing signal; and the grid of the second equalizing pipe is used for receiving a second equalizing signal, one of the source electrode or the drain electrode is connected with the second bit line, and the other one of the source electrode or the drain electrode is used for receiving a second pre-charging voltage and is used for pre-charging the second bit line, the second complementary bit line and the second sensing amplifying structure to the second pre-charging voltage based on the second equalizing signal.

The first equalization signal and the second equalization signal are the same equalization signal, and the first precharge voltage and the second precharge voltage are the same precharge voltage.

In addition, the drain electrode of the first equalizing pipe is connected with the drain electrode of the second equalizing pipe and is used for receiving the same pre-charging voltage.

In addition, a third sensing amplification structure and a fourth sensing amplification structure are also arranged in the structural layer; the third sensing amplification structure is connected with one of the adjacent storage arrays through a third bit line, the third sensing amplification structure is connected with the other of the adjacent storage arrays through a third complementary bit line, the fourth sensing amplification structure is connected with one of the adjacent storage arrays through a fourth bit line, and the fourth sensing amplification structure is connected with the other of the adjacent storage arrays through a fourth complementary bit line; wherein one of the third bit line or the third complementary bit line is disposed in the first interconnect layer and the other is at least partially disposed in the second interconnect layer; one of the fourth bit line or the fourth complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; the equalizing structure is directly connected with the third complementary bit line and the fourth bit line and is used for pre-charging the third bit line, the third complementary bit line, the third sensing amplifying structure, the fourth bit line, the fourth complementary bit line and the fourth sensing amplifying structure; wherein the equalization structure is directly connected with the third complementary bit line and the fourth bit line in the first interconnect layer.

In addition, the equalization structure further includes: a third equalizing pipe, which is arranged at one side of the first equalizing pipe in the extending direction of the word line, shares the same grid with the first equalizing pipe, one of the source electrode or the drain electrode is connected with a third complementary bit line, and the other one is used for receiving a first pre-charging voltage and pre-charging the third bit line, the third complementary bit line and the third sensing amplifying structure to the first pre-charging voltage based on the first equalizing signal; and the fourth equalizing tube is arranged on one side of the second equalizing tube in the extending direction of the word line, shares the same grid with the second equalizing tube, one of the source electrode or the drain electrode is connected with the fourth bit line, and the other one of the source electrode or the drain electrode is used for receiving a second pre-charging voltage and pre-charging the fourth bit line, the fourth complementary bit line and the fourth sensing amplifying structure to the second pre-charging voltage based on the second equalizing signal.

In addition, a first data reading module and a second data reading module are also arranged in the structural layer; a first data readout module comprising: a first input/output pipe, a third input/output pipe, a fifth input/output pipe and a seventh input/output pipe; the source electrode of the first input/output tube is connected with a first input/output line, the drain electrode of the first input/output tube is connected with a first bit line, the source electrode of the third input/output tube is connected with a third input/output line, the drain electrode of the third input/output tube is connected with a second bit line, the source electrode of the fifth input/output tube is connected with a fifth input/output line, the drain electrode of the fifth input/output tube is connected with a third bit line, the source electrode of the seventh input/output tube is connected with a seventh input/output line, and the drain electrode of the seventh input/output tube is connected with a fourth bit line; the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array; the grid electrode of the first input/output tube, the grid electrode of the third input/output tube, the grid electrode of the fifth input/output tube and the grid electrode of the seventh input/output tube are connected together and used for receiving the column selection signal and conducting the first input/output tube, the third input/output tube, the fifth input/output tube and the seventh input/output tube based on the column selection signal; the second data readout module comprises a second input/output tube, a fourth input/output tube, a sixth input/output tube and an eighth input/output tube; the source electrode of the second input/output tube is connected with a second input/output line, the drain electrode of the second input/output tube is connected with a first complementary bit line, the source electrode of the fourth input/output tube is connected with a fourth input/output line, the drain electrode of the fourth input/output tube is connected with the second complementary bit line, the source electrode of the sixth input/output tube is connected with a sixth input/output line, the drain electrode of the sixth input/output tube is connected with a third complementary bit line, the source electrode of the eighth input/output tube is connected with an eighth input/output line, and the drain electrode of the eighth input/output tube is connected with the fourth complementary bit line; the first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent bit lines in the same memory array; and the grid electrode of the second input/output tube, the grid electrode of the fourth input/output tube, the grid electrode of the sixth input/output tube and the grid electrode of the eighth input/output tube are connected together, and are used for receiving the column selection signal and conducting the second input/output tube, the fourth input/output tube, the sixth input/output tube and the eighth input/output tube based on the column selection signal.

In addition, the first sensing amplifying structure includes: the sense amplifying module is connected with a first bit line through a read bit line and connected with a first complementary bit line through a complementary read bit line, and is used for sensing the voltage of a memory cell of the memory array and outputting logic 1 or 0 corresponding to the voltage; the isolation module is connected between the complementary read bit line and the first complementary bit line, connected between the read bit line and the first bit line, and used for isolating signal interaction among the first bit line, the first complementary bit line, the read bit line and the complementary read bit line according to an isolation signal; and the offset elimination module is connected between the read bit line and the first complementary bit line, is connected between the complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS tubes or PMOS tubes in the sensing amplification module according to the offset elimination signal.

In addition, the sense amplifying module includes: the gate of the first sensing amplification N tube is connected with a first bit line, the drain of the first sensing amplification N tube is connected with a complementary read bit line, the source of the first sensing amplification N tube is connected with a second signal end, and when the sensing amplification module is in an amplification stage, the second signal end is electrically connected with a voltage corresponding to a logic 0; a grid electrode of the second sensing amplification N tube is connected with the first complementary bit line, a drain electrode of the second sensing amplification N tube is connected with the read bit line, and a source electrode of the second sensing amplification N tube is connected with a second signal end; the gate of the first sense amplification P tube is connected with the read bit line, the drain of the first sense amplification P tube is connected with the complementary read bit line, the source of the first sense amplification P tube is connected with the first signal end, and when the sense amplification module is in an amplification stage, the first signal end is electrically connected with the voltage corresponding to the logic 1; and the grid electrode of the second sense amplifying P tube is connected with the complementary reading bit line, the drain electrode of the second sense amplifying P tube is connected with the reading bit line, and the source electrode of the second sense amplifying P tube is connected with the first signal end.

In addition, the extension directions of the grid structure of the first sensing amplification N tube, the grid structure of the second sensing amplification N tube, the grid structure of the first sensing amplification P tube and the grid structure of the second sensing amplification P tube are the same, the extension directions of the grid structure of the MOS tube in the isolation module and the grid structure of the MOS tube in the offset elimination module are the same, and the extension directions of the grid structure of the first sensing amplification N tube and the grid structure of the MOS tube in the isolation module are perpendicular to each other.

In addition, the first sensing amplification P pipe, the second sensing amplification P pipe, the isolation module and the offset elimination module are arranged between the first sensing amplification N pipe and the second sensing amplification N pipe.

In addition, the isolation module includes: the grid electrode of the first isolation tube is used for receiving an isolation signal, the source electrode of the first isolation tube is connected with a first bit line, and the drain electrode of the first isolation tube is connected with a read bit line; and the grid of the second isolation tube is used for receiving an isolation signal, the source of the second isolation tube is connected with the first complementary bit line, and the drain of the second isolation tube is connected with the complementary reading bit line.

In addition, the offset canceling module includes: the grid electrode of the first offset eliminating tube is used for receiving an offset eliminating signal, the source electrode of the first offset eliminating tube is connected with a first bit line, and the drain electrode of the first offset eliminating tube is connected with a complementary reading bit line; and the grid of the second offset eliminating tube is used for receiving the offset eliminating signal, the source of the second offset eliminating tube is connected with the first complementary bit line, and the drain of the second offset eliminating tube is connected with the sensing bit line.

In addition, the source electrode of the first isolation tube is communicated with the source electrode of the first offset elimination tube and is connected with a first bit line; the source electrode of the second isolation tube is connected with the source electrode of the second offset elimination tube and is connected with the first complementary bit line.

Drawings

Fig. 1 and fig. 2 are circuit diagrams of a readout circuit structure provided in an embodiment of the present application;

fig. 3 and fig. 4 are layouts of a readout circuit structure provided in an embodiment of the present application;

fig. 5 is a layout of a balanced structure provided in the embodiment of the present application;

fig. 6 is a structural layer layout of another balanced structure provided in the embodiment of the present application.

Detailed Description

As is known in the art, the performance of the prior art DRAM still remains to be improved.

The applicant finds that the existing sense amplifier with the offset compensation function includes the conduction process of the switching transistor in the process of precharging the bit line and the complementary bit line, so that the charging speed of the bit line and the complementary bit line is not fast enough, and as the size of the transistor is further reduced, the saturation current of the switching transistor is reduced, which is more serious and is not beneficial to improving the reading and writing performance of the memory.

To solve the above technical problem, an embodiment of the present invention provides a sensing circuit structure disposed in a gap of a memory array, including: the structure layer, the first interconnection layer and the second interconnection layer are stacked on the top of the structure layer; the structural layer is provided with a first sensing amplification structure, a second sensing amplification structure and a balance structure; the first sensing amplifying structure is connected with one of the adjacent storage arrays through a first bit line, the first sensing amplifying structure is connected with the other of the adjacent storage arrays through a first complementary bit line, the second sensing amplifying structure is connected with one of the adjacent storage arrays through a second bit line, and the second sensing amplifying structure is connected with the other of the adjacent storage arrays through a second complementary bit line; wherein one of the first bit line or the first complementary bit line is disposed in a first interconnect layer and at least a portion of the other is disposed in a second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer and at least a portion of the other is disposed in the second interconnect layer; the equalizing structure is directly connected with the first complementary bit line and the second bit line and is used for pre-charging the first bit line, the first complementary bit line, the first sensing amplifying structure, the second bit line, the second complementary bit line and the second sensing amplifying structure; wherein the equalizing structure is disposed between the first sense amplifier structure and the second sense amplifier structure and directly connected with the first complementary bit line and the second bit line in the first interconnect layer.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and referred to each other without contradiction.

Fig. 1 and fig. 2 are circuit diagrams of the readout circuit structure provided in this embodiment, fig. 3 and fig. 4 are layout diagrams of the readout circuit structure provided in this embodiment, fig. 5 is a layout diagram of an equalization structure provided in this embodiment, fig. 6 is a layout diagram of a structure layer of another equalization structure provided in this embodiment, and the readout circuit structure provided in this embodiment is further described in detail with reference to the following drawings:

it should be noted that, because the circuit diagram and the layout of the read-out circuit structure are large, in order to clearly embody the read-out circuit structure to be protected in this embodiment, the circuit diagram and the layout are split during drawing, that is, fig. 1 and fig. 2 are merged into the circuit diagram of the read-out circuit structure provided in this embodiment, and the merging manner is merging the bottom of fig. 1 and the top of fig. 2; fig. 3 and fig. 4 are combined into a layout of the readout circuit structure provided in the present embodiment, and the combination manner is that the bottom of fig. 3 and the top of fig. 4 are combined.

Referring to fig. 1 to 4, a sensing circuit structure, disposed in a gap between adjacent memory arrays, includes:

the memory array 101 has n rows and m columns of memory cells, each memory cell is used for storing 1bit data, that is, a memory array 101 can store n × mbit data, and in the data reading process, the memory cells are gated to read out the memory data in the memory cells, or the memory cells are written with data.

The structure layer is a layout on the right side in the figure, the first interconnection layer is a layout on the middle part in the figure, and the second interconnection layer is a layout on the left side in the figure.

In this embodiment, the structural layer is provided with a first sensing amplification structure, a second sensing amplification structure, a first equalization structure and a second equalization structure; the first interconnection layer is used for arranging a bit line or a complementary bit line which is electrically connected with the inner part of the sensing amplifying structure and is closer to the adjacent memory arrays; the second interconnection layer is used for connecting the sensing amplifying structure with the bit line or the complementary bit line of the farther one between the adjacent memory arrays.

As can be seen from fig. 1 and 2 in conjunction with fig. 3 and 4, in the bit line extending direction, the first sense amplifying structure and the second sense amplifying structure are disposed adjacent to each other, and are used for sensing the voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage; the first sensing amplifying structure is connected with one memory array of the adjacent memory arrays through a first bit line BL1, the first sensing amplifying structure is connected with the other memory array of the adjacent memory arrays through a first complementary bit line BLB1, the second sensing amplifying structure is connected with one memory array of the adjacent memory arrays through a second bit line BL2, and the second sensing amplifying structure is connected with the other memory array of the adjacent memory arrays through a second complementary bit line BLB2.

For the first bit line BL1, the second bit line BL2, the first complementary bit line BLB1, and the second complementary bit line BLB2, one of the first bit line BL1 or the first complementary bit line BLB1 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the second bit line BL2 or the second complementary bit line BLB2 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer.

Specifically, in the present embodiment, the first bit line BL1 is disposed in the first interconnect layer, at least a portion of the first complementary bit line BLB1 is disposed in the second interconnect layer, the first complementary bit line BLB1 is coupled to the first sense amplifying structure after passing through a region where the second sense amplifying structure is located in the second interconnect layer, the second bit line BL2 is at least partially disposed in the second interconnect layer, the second bit line BL2 is coupled to the second sense amplifying structure after passing through a region where the first sense amplifying structure is located in the second interconnect layer, and the second complementary bit line BLB2 is disposed in the first interconnect layer.

The first complementary bit line BLB1 penetrates through the region where the second sensing amplifying structure is located to be coupled with the first sensing amplifying structure, namely the first complementary bit line BLB1 does not need to occupy extra layout area to complete wiring, and therefore layout area of the reading circuit structure is reduced, the second bit line BL2 penetrates through the region where the first sensing amplifying structure is located to be coupled with the second sensing amplifying structure, namely the second bit line BL2 does not need to occupy extra layout area to complete wiring, and therefore layout area of the reading circuit structure is reduced.

The equalizing structure is directly connected to the first complementary bit line BLB1 and the second bit line BL2 for precharging the first bit line BL1, the first complementary bit line BLB1, the first sense amplifying structure, the second bit line BL2, the second complementary bit line BLB2, and the second sense amplifying structure.

In the present embodiment, the equalizing structure is disposed between the first and second sense amplifying structures, and is directly connected with the first and second complementary bit lines BLB1 and BL2 in the first interconnect layer.

Wherein the equalization structure comprises a first equalization pipe < N1> and a second equalization pipe < N2>.

First equalizing pipe<N1>The gate of (3) is used for receiving a first equalizing signal EQ1, one of the source or the drain is connected to the first complementary bit line BLB1, and the other is used for receiving a first pre-charge voltage V ₁ For precharging the first bit line BL1, the first complementary bit line BLB1 and the first sense amplifying structure to a first precharge voltage V based on the first equalization signal EQ1 ₁ (ii) a In this embodiment, the first equalizing pipe<N1>A source connected to the first complementary bit line BLB1, and a drain for receiving a first precharge voltage V ₁ For precharging the first bit line BL1, the first complementary bit line BLB1 and the first sense amplifying structure to the first based on the first equalizing signal EQ1A pre-charging voltage V ₁ 。

Second equalizing pipe<N2>A gate for receiving a second equalization signal EQ2, a source or a drain connected to a second bit line BL2, and the other for receiving a second precharge voltage V ₂ For precharging the second bit line BL2, the second complementary bit line BLB2 and the second sense amplifying structure to the second precharge voltage V based on the second equalization signal EQ2 ₂ (ii) a In this embodiment, the second equalizing tube<N2>Has a source connected to a second bit line BL2 and a drain for receiving a second precharge voltage V ₂ For precharging the second bit line BL2, the second complementary bit line BLB2 and the second sense amplifying structure to the second precharge voltage V based on the second equalizing signal EQ2 ₂ 。

In the above description, the connection mode of the specific "source" and the specific "drain" is not limited to the present embodiment, and in other embodiments, the connection mode of the "drain" instead of the "source" may be adopted, and the connection mode of the "source" instead of the "drain" may also be adopted.

The bit line/the complementary bit line are directly connected through the equalizing tube and are directly charged, so that the bit line/the complementary bit line can be prevented from being precharged only by switching on the switching transistor in the precharging process, and the charging speed of the bit line and the complementary bit line is accelerated.

It should be noted that, the above-mentioned "first precharge voltage V ₁ AND second precharge voltage V ₂ "i.e., the voltages required for precharging the memory bit line and the complementary bit line in the precharge stage, the specific voltage is set according to the precharge voltage required for the normal operation of the memory, and the embodiment does not constitute the pair of" the first precharge voltage V ₁ And second precharge voltage V ₂ "definition of numerical value".

In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, i.e., the same control signal is used for precharging the bit line and the complementary bit line. A first pre-charge voltage V ₁ And a second precharge voltage V ₂ For the same pre-charging voltage V _BLP (ii) a In the present embodiment, the precharge voltage V _BLP ＝1/2V _DD Wherein V is _DD Is the chip internal power supply voltage; in other embodiments, the precharge voltage V _BLP The setting can be carried out according to specific application scenes.

Further, in this embodiment, the first equalizing pipe<N1>And a second equalizing pipe<N2>For receiving the same precharge voltage V _BLP Through a first equalizing tube<N1>And a second equalizing pipe<N2>Can reduce the first equalizing tube<N1>And a second equalizing tube<N2>The pitch is set so as to reduce the layout area of the read circuit structure.

In the present embodiment, in order to clearly distinguish the first memory array from the second memory array, in the following description, the memory array in which the first sense amplifying structure is connected through the first bit line BL1 is referred to as a "first memory array"; the memory array in which the second sense amplifying structure is connected through the second complementary bit line BLB2 is referred to as a "second memory array".

In addition, in the extending direction of the word line, there is not only one group of sense amplifying structures between adjacent memory arrays, and the present embodiment is described in detail by taking a layout structure of 2 × 2 as an example, which is specifically as follows:

in this embodiment, a third sense amplifying structure, a fourth sense amplifying structure, a third equalizing structure and a fourth equalizing structure are further disposed in the structural layer.

In the extending direction of the bit line, the third sensing amplifying structure and the fourth sensing amplifying structure are adjacently arranged, and are used for sensing the voltage of the storage unit and outputting logic 1 or 0 corresponding to the voltage; in the extending direction of the word line, the third sensing amplifying structure and the first sensing amplifying structure are adjacently arranged, and the fourth sensing amplifying structure and the second sensing amplifying structure are adjacently arranged.

The third sense amplifying structure is connected with the first memory array through a third bit line BL3, the second memory array through a third complementary bit line BLB3, and the fourth sense amplifying structure is connected with the first memory array through a fourth bit line BL4 and the second memory array through a fourth complementary bit line BLB4.

For the third bit line BL3, the fourth bit line BL4, the third complementary bit line BLB3, and the fourth complementary bit line BLB4, one of the third bit line BL3 or the third complementary bit line BLB3 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the fourth bit line BL4 or the fourth complementary bit line BLB4 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer.

It should be noted that the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 are four adjacent bit lines in the same memory array; the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4 are four adjacent bit lines in the same memory array.

Specifically, in the present embodiment, the third bit line BL3 is disposed in the first interconnect layer, at least a portion of the third complementary bit line BLB3 is disposed in the second interconnect layer, the third complementary bit line BLB3 is coupled with the third sense amplifying structure after passing through a region where the fourth sense amplifying structure is located in the second interconnect layer, the fourth bit line BL4 is disposed at least partially in the second interconnect layer, the fourth bit line BL4 is coupled with the fourth sense amplifying structure after passing through a region where the third sense amplifying structure is located in the second interconnect layer, and the fourth complementary bit line BLB4 is disposed in the first interconnect layer.

The third complementary bit line BLB3 penetrates through the area where the second sensing amplifying structure is located to be coupled with the first sensing amplifying structure, namely the third complementary bit line BLB3 does not need to occupy extra layout area to complete wiring, so that the layout area of the reading circuit structure is reduced, the fourth bit line BL4 penetrates through the area where the first sensing amplifying structure is located to be coupled with the second sensing amplifying structure, namely the fourth bit line BL4 does not need to occupy extra layout area to complete wiring, so that the layout area of the reading circuit structure is reduced.

The equalization structure also directly connects the third complementary bitline BLB3 and the fourth bitline BL4 for precharging the third bitline BL3, the third complementary bitline BLB3, the third sense amplifying structure, the fourth bitline BL4, the fourth complementary bitline BLB4, and the fourth sense amplifying structure.

In this embodiment, the equalization structure is also directly connected with the third complementary bit line BLB3 and the fourth bit line BL4 in the first interconnect layer.

Specifically, the equalizing structure further comprises a third equalizing pipe < N3> and a fourth equalizing pipe < N4>, in the extending direction of the word line, the third equalizing pipe < N3> is arranged on one side of the first equalizing pipe < N1> and shares the same grid with the first equalizing pipe < N1>, and the fourth equalizing pipe < N4> is arranged on one side of the second equalizing pipe < N2> and shares the same grid with the second equalizing pipe < N2>.

Third equalizing pipe<N3>A gate for receiving a first equalizing signal EQ1, a source or a drain connected to a third complementary bit line BLB3, and the other for receiving a first precharge voltage V ₁ For precharging the third bit line BL3, the third complementary bit line BLB3 and the third sense amplifying structure to the first precharge voltage V based on the first equalizing signal EQ1 ₁ (ii) a In this embodiment, the third equalizing pipe<N3>Source connected to third complementary bit line BLB3, and drain for receiving first precharge voltage V ₁ For precharging the third bit line BL3, the third complementary bit line BLB3 and the third sense amplifying structure to the first precharge voltage V based on the first equalizing signal EQ1 ₁ 。

Fourth equalizing tube<N4>A gate for receiving a second equalization signal EQ2, a source or a drain connected to a fourth bit line BL4, and the other for receiving a second precharge voltage V ₂ For precharging the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sense amplifying structure to the second precharge voltage V based on the second equalization signal EQ2 ₂ (ii) a In this embodiment, a fourth equalizing pipe<N4>Has a source connected to a fourth bit line BL4 and a drain for receiving a second precharge voltage V ₂ For precharging the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sense amplifying structure to the second precharge voltage V based on the second equalizing signal EQ2 ₂ 。

In the above description, the connection mode of the specific "source" and the specific "drain" is not limited to the present embodiment, and in other embodiments, the connection mode of the "drain" instead of the "source" may be adopted, and the connection mode of the "source" instead of the "drain" may also be adopted.

The bit line/complementary bit line is directly connected through the equalizing tube to directly charge the bit line and the complementary bit line, so that the bit line/complementary bit line can be prevented from being precharged only by switching on the switching transistor in the precharging process, and the charging speed of the bit line and the complementary bit line is accelerated.

It should be noted that, the above-mentioned "first precharge voltage V ₁ AND second precharge voltage V ₂ "i.e., the voltages required for precharging the memory bit line and the complementary bit line in the precharge stage, the specific voltage is set according to the precharge voltage required for the normal operation of the memory, and the embodiment does not constitute the pair of" the first precharge voltage V ₁ And second precharge voltage V ₂ "definition of numerical value".

In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, i.e., the same control signal is used to precharge the bitline and the complementary bitline. A first pre-charge voltage V ₁ And a second precharge voltage V ₂ For the same pre-charging voltage V _BLP (ii) a In the present embodiment, the precharge voltage V _BLP ＝1/2V _DD Wherein V is _DD Is the chip internal supply voltage; in other embodiments, the precharge voltage V _BLP The setting can be carried out according to specific application scenes.

Further, in the present embodiment, a third equalizing pipe<N3>Drain electrode of and fourth equalizing tube<N4>For receiving the same precharge voltage V _BLP Through a third equalizing pipe<N3>Drain electrode of and fourth equalizing tube<N4>Is connected to the drain of the first equalizing pipe, the third equalizing pipe can be reduced<N3>And a fourth equalizing tube<N4>The set pitch, thereby reducing the layout area of the read-out circuit structure.

With continued reference to fig. 1 and 2, the sensing circuit arrangement further includes a first data sensing block comprising: a first input/output pipe, a third input/output pipe, a fifth input/output pipe and a seventh input/output pipe.

One of the source electrode or the drain electrode of the first input/output tube is directly connected with the first input/output tube, the other one of the source electrode or the drain electrode of the first input/output tube is connected with the first bit line, the grid electrode of the first input/output tube is used for receiving a column selection signal, and the first input/output tube is conducted based on the column selection signal, so that the first input/output tube is electrically connected with the first bit line, and an electric signal carried in the first bit line is output through the first input/output tube; in this embodiment, the source of the first input/output transistor is connected to the first input/output line, and the drain is connected to the first bit line.

One of the source electrode or the drain electrode of the third input/output tube is directly connected with the third input/output tube, the other one of the source electrode or the drain electrode of the third input/output tube is connected with the second bit line, the grid electrode of the third input/output tube is used for receiving the column selection signal and conducting the third input/output tube based on the column selection signal, so that the third input/output tube is electrically connected with the second bit line, and the electric signal carried in the second bit line is output through the third input/output tube; in this embodiment, the source of the third input/output transistor is connected to the third input/output line, and the drain is connected to the second bit line.

One of the source electrode or the drain electrode of the fifth input/output tube is directly connected with the fifth input/output tube, the other one of the source electrode or the drain electrode of the fifth input/output tube is connected with the third bit line, the grid electrode of the fifth input/output tube is used for receiving the column selection signal, the fifth input/output tube is conducted based on the column selection signal, the fifth input/output tube is electrically connected with the third bit line, and therefore the electric signal carried in the third bit line is output through the fifth input/output tube; in this embodiment, the source of the fifth input/output transistor is connected to the fifth input/output line, and the drain is connected to the third bit line.

One of the source electrode or the drain electrode of the seventh input/output tube is directly connected with the seventh input/output tube, the other one of the source electrode or the drain electrode of the seventh input/output tube is connected with the fourth bit line, the grid electrode of the seventh input/output tube is used for receiving the column selection signal, the seventh input/output tube is conducted based on the column selection signal, the seventh input/output tube is electrically connected with the fourth bit line, and therefore the electric signal carried in the fourth bit line is output through the seventh input/output tube; in this embodiment, the source of the seventh input/output transistor is connected to the seventh input/output line, and the drain is connected to the fourth bit line.

It should be noted that, in the above description, the connection manner of the specific "source" and the specific "drain" does not constitute a limitation to this embodiment, and in other embodiments, the connection manner of the "drain" instead of the "source" may be adopted, and the connection manner of the "source" instead of the "drain" may also be adopted.

A second data readout module, the second data readout module comprising: a second input/output pipe, a fourth input/output pipe, a sixth input/output pipe and an eighth input/output pipe.

One of the source electrode or the drain electrode of the second input/output tube is directly connected with the second input/output tube, the other one of the source electrode or the drain electrode of the second input/output tube is connected with the first complementary bit line, the grid electrode of the second input/output tube is used for receiving the column selection signal, and the second input/output tube is conducted based on the column selection signal, so that the second input/output tube is electrically connected with the first complementary bit line, and the electric signal carried in the first complementary bit line is output through the second input/output tube; in this embodiment, the source of the second input/output transistor is connected to the second input/output line, and the drain is connected to the first complementary bit line.

One of a source electrode or a drain electrode of the fourth input/output tube is directly connected with the fourth input/output line, the other one of the source electrode or the drain electrode of the fourth input/output tube is connected with the second complementary bit line, a grid electrode of the fourth input/output tube is used for receiving the column selection signal, the fourth input/output tube is conducted based on the column selection signal, the fourth input/output line is electrically connected with the second complementary bit line, and therefore the electric signal carried in the second complementary bit line is output through the fourth input/output line; in this embodiment, the source of the fourth input/output transistor is connected to the fourth input/output line, and the drain is connected to the second complementary bit line.

One of the source electrode or the drain electrode of the sixth input/output tube is directly connected with the sixth input/output line, the other one of the source electrode or the drain electrode of the sixth input/output tube is connected with the third complementary bit line, the grid electrode of the sixth input/output tube is used for receiving the column selection signal, and the sixth input/output tube is conducted based on the column selection signal, so that the sixth input/output line is electrically connected with the third complementary bit line, and the electric signal carried in the third complementary bit line is output through the sixth input/output line; in this embodiment, the source of the sixth input/output transistor is connected to the sixth input/output line, and the drain is connected to the third complementary bit line.

One of the source electrode or the drain electrode of the eighth input/output tube is directly connected with the eighth input/output line, the other one of the source electrode or the drain electrode of the eighth input/output tube is connected with the fourth complementary bit line, the grid electrode of the eighth input/output tube is used for receiving the column selection signal, the eighth input/output tube is conducted based on the column selection signal, the eighth input/output line is electrically connected with the fourth complementary bit line, and therefore the electric signal carried in the fourth complementary bit line is output through the eighth input/output line; in this embodiment, the source of the eighth I/O line is connected to the eighth I/O line, and the drain is connected to the fourth complementary bit line.

It should be noted that, in the above description, the connection manner of the specific "source" and the specific "drain" does not constitute a limitation to this embodiment, and in other embodiments, the connection manner of the "drain" instead of the "source" may be adopted, and the connection manner of the "source" instead of the "drain" may also be adopted.

Referring to fig. 1, for the first sense amplifying structure and the third sense amplifying structure, the first sense amplifying structure is taken as an example and is described in detail below, and the first sense amplifying structure includes:

and a sense amplifying block connected to the first bit line BL1 through the sense bit line SABL and connected to the first complementary bit line BLB1 through the complementary sense bit line SABLB, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, a sense amplifier module includes: the first sense amplifying N transistor < N1400>, the grid electrode is connected with a first bit line BL1, the drain electrode is connected with a complementary reading bit line SABLB, the source electrode is connected with a second signal end NCS, and when the sense amplifying module is in an amplifying stage, the second signal end NCS is electrically connected with a voltage corresponding to logic 0; a second sense amplifier N transistor < N1405>, a gate connected to the first complementary bit line BLB1, a drain connected to the sense bit line SABL, and a source connected to the second signal terminal NCS; when the sensing amplification module is in an amplification stage, the first signal end PCS is electrically connected with voltage corresponding to logic 1; and the grid electrode of the second sensing amplifying P tube < P1400> is connected with a complementary reading bit line SABLB, the drain electrode of the second sensing amplifying P tube < P1400>, the reading bit line SABL is connected with the drain electrode of the second sensing amplifying P tube, and the source electrode of the second sensing amplifying P tube < P1400> is connected with the first signal terminal PCS.

And an isolation module connected between the complementary sensing bit line SABLB and the first complementary bit line BLB1, and connected between the sensing bit line SABL and the first bit line BL1, for isolating the first bit line BL1, the first complementary bit line BLB1 and signal interaction between the sensing bit line SABL and the complementary sensing bit line SABLB according to an isolation signal ISO.

Specifically, an isolation module includes: a first isolation transistor < N1402>, a gate for receiving an isolation signal ISO, a source connected to the first bit line BL1, a drain connected to the sensing bit line SABL, and a second isolation transistor < N1403>, a gate for receiving the isolation signal ISO, a source connected to the first complementary bit line BLB1, and a drain connected to the complementary sensing bit line SABLB.

And the offset elimination module is connected between the sensing bit line SABL and the first complementary bit line BLB1, and connected between the complementary sensing bit line SABLB and the first bit line BL1, and is used for adjusting the source-drain conduction difference between the NMOS or the PMOS tubes in the sensing amplification module according to the offset elimination signal OC.

It should be noted that the above-mentioned "source-drain conduction difference" refers to: the first and second sense-amplifying N-tubes < N1400> and < N1405> and the first and second sense-amplifying P-tubes < P1401> and < P1400> may have different threshold voltages from each other due to variations in manufacturing processes, temperature, etc. In this case, the sense amplifying module may cause offset noise due to a difference between threshold voltages of the first and second sense amplifying P-tubes < P1401> and < P1400> and the first and second sense amplifying N-tubes < N1400> and < N1405 >.

Specifically, the offset canceling module includes: a first offset cancellation transistor < N1401>, having a gate for receiving an offset cancellation signal OC, a source connected to the first bit line BL1, and a drain connected to the complementary sensing bit line SABLB; a second offset cancellation transistor < N1404>, a gate for receiving an offset cancellation signal OC, a source connected to the first complementary bit line BLB1, and a drain connected to the sense bit line SABL.

It is understood by those skilled in the art that the third sense amplifying structure has the same structure as the first sense amplifying structure, and the above description is also applicable after performing feature replacement of the corresponding structure. Specifically, the corresponding structure includes: the first bit line BL1 corresponds to BL3, the first complementary bit line BLB1 corresponds to BLB3, the first equalizing pipe < N1> corresponds to < N5>, the third equalizing pipe < N3> corresponds to < N7>, the first sense amplifier N pipe < N1400> corresponds to < N1410>, the second sense amplifier N pipe < N1405> corresponds to < N1415>, the first sense amplifier P pipe < P1401> corresponds to < P1411>, the second sense amplifier P pipe < P1400> corresponds to < P1410>, the first isolation pipe < N1402> corresponds to < N1412>, the second isolation pipe < N1403> corresponds to < N1413>, the first offset amplifier N < N1401> corresponds to < N1411> and the second offset amplifier < N > corresponds to < N1414>.

For the first data reading module, the source of the first input/output tube is connected to the first input/output line I/O1, the drain is directly connected to the first bit line BL1, the gate is configured to receive the column selection signal CY, the source of the third input/output tube is connected to the third input/output line I/O3, the drain is directly connected to the second bit line BL2, the gate is configured to receive the column selection signal CY, the source of the fifth input/output tube is connected to the fifth input/output line I/O5, the drain is directly connected to the third bit line BL3, the gate is configured to receive the column selection signal CY, the source of the seventh input/output tube is connected to the seventh input/output line I/O7, the drain is directly connected to the fourth bit line BL4, and the gate is configured to receive the column selection signal CY.

The first input/output line, the third input/output line, the fifth input/output line, and the seventh input/output line are turned on by the same column selection signal CY, so that the level signal transmitted in the first bit line BL1 is derived by the first input/output line I/O1, the level signal transmitted in the second bit line BL2 is derived by the third input/output line I/O3, the level signal transmitted in the third bit line BL3 is derived by the fifth input/output line I/O5, and the level signal transmitted in the fourth bit line BL4 is derived by the seventh input/output line I/O7.

Referring to fig. 2, for the second sense amplifying structure and the fourth sense amplifying structure, the second sense amplifying structure is taken as an example and is described in detail below, and the second sense amplifying structure includes:

and a sense amplifying block connected to the second bit line BL2 through the sense bit line SABL and connected to the second complementary bit line BLB2 through the complementary sense bit line SABLB, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, a sense amplifier module includes: a third sense amplifying N transistor < N1425>, the gate is connected to the second bit line BL2, the drain is connected to the complementary read bit line SABLB, the source is connected to the second signal terminal NCS, and when the sense amplifying module is in an amplifying stage, the second signal terminal NCS is electrically connected to a voltage corresponding to logic 0; a fourth sense amplifier N transistor < N1420>, having a gate connected to the second complementary bitline BLB2, a drain connected to the readout bitline SABL, and a source connected to the second signal terminal NCS; a third sense amplifying P-transistor < P1421>, a gate is connected to a readout bit line SABL, a drain is connected to a complementary readout bit line SABLB, a source is connected to a first signal terminal PCS, and when the sense amplifying module is in an amplifying stage, the first signal terminal PCS is electrically connected to a voltage corresponding to a logic 1; the fourth sense amplifier P pipe < P1420>, the gate is connected to the complementary sense bitline SABLB, the drain is connected to the sense bitline SABL, and the source is connected to the first signal terminal PCS.

And an isolation module connected between the complementary sensing bit line SABLB and the second complementary bit line BLB2, and connected between the sensing bit line SABL and the second bit line BL2, for isolating the second bit line BL2, the second complementary bit line BLB2 from signal interaction between the sensing bit line SABL and the complementary sensing bit line SABLB according to an isolation signal ISO.

Specifically, an isolation module includes: a first isolation transistor < N1423>, a gate for receiving an isolation signal ISO, a source connected to the second bit line BL2, a drain connected to the sense bit line SABL, and a second isolation transistor < N1422>, a gate for receiving an isolation signal ISO, a source connected to the second complementary bit line BLB2, and a drain connected to the complementary sense bit line SABLB.

And the offset elimination module is connected between the read bit line SABL and the second complementary bit line BLB2, and connected between the complementary read bit line SABLB and the second bit line BL2, and is used for adjusting the source-drain conduction difference between the NMOS tubes or the PMOS tubes in the sensing amplification module according to the offset elimination signal OC.

It should be noted that the above-mentioned "source-drain conduction difference" refers to: the third and fourth sense amp Npipe < N1425> and N1420> and the third and fourth sense amp pT < P1421> and P1420> may have different threshold voltages from each other due to variations in manufacturing processes, temperatures, etc. In this case, the sense amplifying module may cause offset noise due to a difference between threshold voltages of the third and fourth sense amplifying P-tubes < P1421> and P1420> and the third and fourth sense amplifying N-tubes < N1445> and N1420 >.

Specifically, the offset cancellation module includes: a third offset cancellation transistor < N1424>, having a gate for receiving an offset cancellation signal OC, a source connected to the second bit line BL2, and a drain connected to the complementary sensing bit line SABLB; a fourth offset cancellation transistor < N1421>, having a gate for receiving the offset cancellation signal OC, a source connected to the second complementary bit line BLB2, and a drain connected to the sensing bit line SABL.

It is understood by those skilled in the art that the structure of the fourth sense amplifying structure is the same as that of the second sense amplifying structure, and the above description is also applicable after performing feature replacement of the corresponding structure. Specifically, the corresponding structure includes: the second bit line BL2 corresponds to BL4, the second complementary bit line BLB2 corresponds to BLB4, the second equalizing pipe < N2> corresponds to < N6>, the fourth equalizing pipe < N4> corresponds to < N8>, the third sense amp N pipe < N1425> corresponds to < N1435>, the fourth sense amp N pipe < N1420> corresponds to < N1430>, the third sense amp P pipe < P1421> corresponds to < P1431>, the fourth sense amp P pipe < P1420> corresponds to < P1430>, the third isolation pipe < N1423> corresponds to < N1433>, the fourth isolation pipe < N1422> corresponds to < N1432>, the third offset cancel pipe < N1424> corresponds to < N1434>, and the fourth offset cancel pipe < N1421> corresponds to N < 1431>.

For the second data readout module, the source of the second input/output tube is connected to the second input/output line I/O2, the drain is directly connected to the first complementary bit line BLB1, the gate is used for receiving the column selection signal CY, the source of the fourth input/output tube is connected to the fourth input/output line I/O4, the drain is directly connected to the second complementary bit line BLB2, the gate is used for receiving the column selection signal CY, the source of the sixth input/output tube is connected to the sixth input/output line I/O6, the drain is directly connected to the third complementary bit line BLB3, the gate is used for receiving the column selection signal CY, the source of the eighth input/output tube is connected to the eighth input/output line I/O8, the drain is directly connected to the fourth complementary bit line BLB4, and the gate is used for receiving the column selection signal CY.

The second input/output line, the fourth input/output line, the sixth input/output line, and the eighth input/output line are turned on by the same column selection signal CY, so that the level signal transmitted in the first complementary bit line BLB1 is derived through the second input/output line I/O2, the level signal transmitted in the second complementary bit line BLB2 is derived through the fourth input/output line I/O4, the level signal transmitted in the third complementary bit line BLB3 is derived through the sixth input/output line I/O6, and the level signal transmitted in the fourth complementary bit line BLB4 is derived through the eighth input/output line I/O8.

Referring to fig. 3, the left side is layout of the second interconnection layer, the middle is layout of the first interconnection layer, the right side is layout of the structural layer, and regions with the same number represent layout of different layers which need electrical connection, wherein the oblique frame region is layout of the active layer, the white frame region is layout of the gate layer, and the shadow region is layout of the contact layer.

The first sense amplifying structure is taken as an example for description, and the third sense amplifying structure can be compared according to the drawings, and the description of the embodiment is omitted. For the structural layer layout, the following steps are performed from top to bottom in sequence:

the device comprises a first data reading module, a first sensing amplification N pipe < N1425>, a first isolation and offset elimination integrated module, a second sensing amplification P pipe < P1400>, a first sensing amplification P pipe < P1401>, a second isolation and offset elimination integrated module, a second sensing amplification N pipe < N1405> and a partial equalization structure.

For the first data sensing block, the gates of the first, third, fifth and seventh input/output transistors < N1001> and < N1003> are connected together for receiving the same column selection signal CY, in particular to the first interconnect layer through contact 109, and to the second interconnect layer through contact 201 in the first interconnect layer for receiving the column selection signal CY. That is, the read circuit structure of this embodiment can read data stored in 4 consecutive memory cells through 4 consecutive bit lines arranged in parallel according to the same column selection signal; it should be noted that in a specific application, the number of input/output tubes controlled by the same column selection signal can also be set according to the actual requirement, i.e. the number of data to be read by the same column selection signal.

In addition, as can be seen from the figure, the first input/output pipe < N1001>, the third input/output pipe < N1003>, the fifth input/output pipe < N1005> and the seventh input/output pipe < N1007> are arranged in a staggered manner, wherein the contact regions 105, 106, 107 and 108 between the "H" type gates are respectively used for connecting the first bit line BL1, the second bit line BL2, the third bit line BL3 and the fourth bit line BL4. Contact regions 101, 102, 103 and 104 outside the "H" type gates are used to connect to I/O1, I/O3, I/O5 and I/O7, respectively, at the first interconnect level.

Further, in the direction in which the word lines extend, the pitches between the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 to which the first data sensing module 114 is connected are equal.

For the first sense amplifier N-transistor < N1400>, the gate is connected to the first interconnect layer through contact regions 110 and 116, the first bit line BL1 is connected to the first interconnect layer at the first interconnect layer, the source is connected to the first interconnect layer through contact region 118, the first complementary read bit line SABLB1 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through contact region 112, the second interconnect layer is connected to the second interconnect layer through contact region 204 at the first interconnect layer for contacting the second control signal NCS, and the second control signal NCS is used to provide a low level signal during the read phase.

For a first isolation and offset cancellation integrated module, including a first offset cancellation pipe < N1401> and a first isolation pipe < N1402>, the first offset cancellation pipe < N1401> and the first isolation pipe < N1402> share a source, the source is connected to a first interconnect layer through a contact region 120, the first bit line BL1 is connected to the first interconnect layer at the first interconnect layer, the first offset cancellation pipe < N1401> drain is connected to the first interconnect layer through a contact region 118, the first complementary sensing bit line SABLB1 is connected to the first interconnect layer at the first interconnect layer, the first isolation pipe < N1402> drain is connected to the first interconnect layer through a contact region 122, and the first sensing bit line SABL1 is connected to the first interconnect layer.

For the second sense amplifier pipe < P1400>, the gate is connected to the first interconnect layer through contact regions 124 and 129, the first complementary sense bitline SABLB1 is connected to the first interconnect layer at the first interconnect layer, the source is connected to the first interconnect layer through contact region 126, the first sense bitline SABL1 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through contact region 127, the second interconnect layer is connected to the first interconnect layer through contact region 206 at the first interconnect layer, the first control signal PCS is received at the second interconnect layer, and the first control signal PCS is used to provide a high level signal during the sensing phase.

For the first sense amplification P-transistor < P1401>, the gate is connected to the first interconnect layer through contact regions 130 and 135, the first readout bit line SABL1 is connected to the first interconnect layer, the source is connected to the first interconnect layer through contact region 132, the first complementary readout bit line SABLB1 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through contact region 131, the first interconnect layer is connected to the second interconnect layer through contact region 207, and the first control signal PCS is received at the second interconnect layer.

For the second isolation and offset cancellation integrated module, including a second isolation pipe < N1403> and a second offset cancellation pipe < N1404>, the second isolation pipe < N1403> and the second offset cancellation pipe < N1404> share a source, the source is connected to the first interconnect layer through a contact region 139, the first complementary bit line BLB1 is connected to the first interconnect layer at the first interconnect layer, the second isolation pipe < N1403> drain is connected to the first interconnect layer through a contact region 137, the first complementary read bit line SABLB1 is connected to the first interconnect layer at the first interconnect layer, the second offset cancellation pipe < N1404> drain is connected to the first interconnect layer through a contact region 141, and the first read bit line SABL1 is connected to the first interconnect layer.

For the second sense amplifier N transistor < N1405>, the gate is connected to the first interconnect layer through contact regions 143 and 148, the first complementary bit line BLB1 is connected to the first interconnect layer, the source is connected to the first interconnect layer through contact region 145, the first readout bit line SABL1 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through contact region 146, the second interconnect layer is connected to the first interconnect layer through contact region 209, the second interconnect layer is for contacting the second control signal NCS, and the second control signal NCS is for providing a low level signal during the readout phase.

Referring to fig. 4, the left side is layout of the second interconnection layer, the middle is layout of the first interconnection layer, the right side is layout of the structural layer, and regions with the same number represent layout of different layers which need electrical connection, wherein the oblique frame region is layout of the active layer, the white frame region is layout of the gate layer, and the shadow region is layout of the contact layer.

The second sense amplifying structure is taken as an example for description, and for the fourth sense amplifying structure, the comparison can be performed according to the drawings, and the description is omitted in this embodiment. For the structural layer layout, the following steps are performed from top to bottom in sequence: the device comprises a partial equalization structure, a fourth sense amplification N pipe < N1425>, a fourth isolation and offset elimination integrated module, a third sense amplification P pipe < P1421>, a fourth sense amplification P pipe < P1420>, a third isolation and offset elimination integrated module and a third sense amplification N pipe < N1420> second data reading module.

For the fourth sense amplification N-transistor < N1425>, the gate is connected to the first interconnect layer through contact regions 342 and 347, the second bit line BL2 is connected to the first interconnect layer at the first interconnect layer, the source is connected to the first interconnect layer through contact region 345, the second complementary readout bit line SABLB2 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through contact region 344, the second interconnect layer is connected to the first interconnect layer through contact region 408 at the first interconnect layer, the second interconnect layer is configured to contact the second control signal NCS, and the second control signal NCS is configured to provide a low level signal during the readout phase.

For the fourth isolation and offset cancellation integrated module, for the second isolation and offset cancellation integrated module, the fourth isolation pipe < N1423> and the fourth offset cancellation pipe < N1424> share a source, the source is connected to the first interconnect layer through the contact region 338, the second bit line BL2 is connected to the first interconnect layer at the first interconnect layer, the fourth isolation pipe < N1423> drain is connected to the first interconnect layer through the contact region 336, the second sensing bit line SABL2 is connected to the first interconnect layer at the first interconnect layer, and the second complementary sensing bit line SABLB2 is connected to the first interconnect layer at the first interconnect layer.

For the third sense amplifying pipe < P1421>, the gate is connected to the first interconnect layer through the contact region 334, the second complementary sense bitline SABLB2 is connected to the first interconnect layer at the first interconnect layer, the source is connected to the first interconnect layer through the contact region 331, the second sense bitline SABL2 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through the contact region 332, the second interconnect layer is connected to the first interconnect layer through the contact region 407 at the first interconnect layer, and the first control signal PCS is received at the second interconnect layer.

For the fourth sense amplification P-transistor < P1420>, the gate is connected to the first interconnect layer through the contact region 323, the second sense bitline SABL2 is connected at the first interconnect layer, the source is connected to the first interconnect layer through the contact region 326, the second complementary sense bitline SABLB2 is connected at the first interconnect layer, the drain is connected to the first interconnect layer through the contact region 325, the second interconnect layer is connected at the first interconnect layer through the contact region 405, the first control signal PCS for providing a high level signal at the sensing stage is received at the second interconnect layer.

For the third isolation and offset cancellation integrated module, including a third offset cancellation pipe < N1421> and a third isolation pipe < N1422>, the third offset cancellation pipe < N1421> and the third isolation pipe < N1422> share a source, the source is connected to the first interconnect layer through a contact region 319, the second complementary bit line BLB2 is connected to the first interconnect layer at the first interconnect layer, the drain of the third offset cancellation pipe < N1421> is connected to the first interconnect layer through a contact region 317, the second sensing bit line SABL2 is connected to the first interconnect layer at the first interconnect layer, the drain of the third isolation pipe < N1422> is connected to the first interconnect layer through a contact region 321, and the second complementary bit line SABLB2 is connected to the first interconnect layer.

For the third sense amplifier N-transistor < N1420>, the gate is connected to the first interconnect layer through contact regions 310 and 315, the second complementary bitline BLB2 is connected to the first interconnect layer, the source is connected to the first interconnect layer through contact region 312, the second sensing bitline SABL2 is connected to the first interconnect layer at the first interconnect layer, the drain is connected to the first interconnect layer through contact region 313, the second interconnect layer is connected to the first interconnect layer through contact region 404, the second interconnect layer is used for contacting the second control signal NCS, and the second control signal NCS is used for providing a low level signal during the sensing phase.

For the second data sensing block, the gates of the second input/output line < N1002>, the fourth input/output line < N1004>, the sixth input/output line < N1006> and the eighth input/output line < N1008> are connected together for receiving the same column selection signal CY, in particular to the first interconnect layer via contact area 309, and to the second interconnect layer via contact 201 in the first interconnect layer for receiving the column selection signal CY. That is, the sensing circuit structure of the present embodiment can sense data stored in 4 consecutive memory cells through 4 consecutive complementary bit lines arranged in parallel according to the same column selection signal; it should be noted that in a specific application, the number of input/output tubes controlled by the same column selection signal can also be set according to the actual requirement, i.e. the number of data to be read by the same column selection signal.

In addition, as can be seen, the second input/output pipe < N1002>, the fourth input/output pipe < N1004>, the sixth input/output pipe < N1006> and the eighth input/output pipe < N1008> are arranged in a staggered manner, wherein the contact regions between the "H" type gates are respectively used for connecting the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3 and the fourth complementary bit line BLB4. Contact regions 301, 302, 303 and 304 outside the "H" type gates are used to connect to I/O2, I/O4, I/O6 and I/O8, respectively, at the first interconnect level.

Further, in the direction in which the word lines extend, the pitches between the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4 to which the second data sensing module 124 is connected are equal.

For the partial equalization structures in fig. 3 and 4, the merged structure refers to fig. 5, which is as follows:

first equalizing pipe<N1>The source is connected to a first interconnect layer via contact region 152, in which it is connected to a second interconnect layer via contact region 212, in which it receives a precharge voltage V _BLP (ii) a The drain is connected to a first interconnect layer, in which it is connected to a first complementary bit line BLB1, through a contact region 150, i.e. a first equalization structure<N1>For precharging the first complementary bit line BLB 1. For the first complementary bit line BLB1, referring to fig. 4, the first complementary bit line BLB1 located in the first interconnect layer is connected to the second interconnect layer through the contact regions 404 and 412, and is routed in the second interconnect layer, thereby reducing the layout area of the sensing circuit structure.

Second equalizing tube<N2>The source is connected to the first interconnect layer through contact region 352, in which it is connected to the second interconnect layer through contact region 412, in which it receives the precharge voltage V _BLP (ii) a The drain is connected to a first interconnect layer, in which it is connected to a second bit line BL2, i.e. a second equalization structure, through a contact region 350<N2>For precharging the second bit line BL 2. As for the second bit line BL2, referring to fig. 3, the second bit line BL2 located in the first interconnect layer is connected to the second interconnect layer through contact regions 204 and 212, and is routed in the second interconnect layer, thereby reducing the layout area of the sensing circuit structure.

The first equalizing pipe < N1> and the second equalizing pipe < N2> share the same source, that is, the contact region 152 and the contact region 352 are the same contact region, and the contact region 212 and the contact region 412 on the first interconnection layer are the same contact region. The first equalizing pipe < N1> and the second equalizing pipe < N2> share the source electrode, namely the first equalizing pipe < N1> and the second equalizing pipe < N2> share the active area, so that the distance between the first equalizing pipe < N1> and the second equalizing pipe < N2> is reduced, and the layout area of the reading circuit structure is further reduced.

Further, referring to fig. 6, the first equalizing pipe < N1> gate and the second equalizing pipe < N2> gate are connected for receiving the same equalizing signal to realize the pre-charging of the first sensing amplifying structure and the second sensing amplifying structure.

Compared with the prior art, the equalizing structure is directly connected with the first bit line or the first complementary bit line and used for pre-charging the first bit line and the first complementary bit line, the equalizing structure is directly connected with the second bit line or the second complementary bit line and used for pre-charging the second bit line and the second complementary bit line, the equalizing structure is directly connected with the third bit line or the third complementary bit line and used for pre-charging the third bit line and the third complementary bit line, the equalizing structure is directly connected with the fourth bit line or the fourth complementary bit line and used for pre-charging the fourth bit line and the fourth complementary bit line, the equalizing structure is directly connected with the bit lines and directly pre-charges the bit lines, the situation that the bit lines can be pre-charged only by the conduction of the switching transistor in the pre-charging process is avoided, and therefore the charging speed of the bit lines is accelerated; further, at least a part of one of the first bit line or the first complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, at least a part of one of the second bit line or the second complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, at least a part of one of the third bit line or the third complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, at least a part of one of the fourth bit line or the fourth complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, and by the stacked arrangement of the first interconnect layer and the second interconnect layer, a required structure in each layer layout is reduced, thereby reducing a layout area of the readout circuit structure.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.

Claims (15)

1. A sensing circuit structure disposed in a gap between adjacent memory arrays, comprising:

the structure layer, the first interconnection layer and the second interconnection layer are stacked on the top of the structure layer;

the structural layer is provided with a first sensing amplification structure, a second sensing amplification structure and a balance structure;

the first sensing amplifying structure is connected with one of the adjacent storage arrays through a first bit line, the first sensing amplifying structure is connected with the other of the adjacent storage arrays through a first complementary bit line, the second sensing amplifying structure is connected with one of the adjacent storage arrays through a second bit line, and the second sensing amplifying structure is connected with the other of the adjacent storage arrays through a second complementary bit line;

wherein one of the first bit line or the first complementary bit line is disposed in the first interconnect layer and at least a portion of the other is disposed in the second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer;

the equalizing structure directly connects the first complementary bit line and the second bit line for precharging the first bit line, the first complementary bit line, the first sense amplifying structure, the second bit line, the second complementary bit line, and the second sense amplifying structure;

wherein the equilibrate structure is disposed between the first and second sense amplifier structures and is directly connected with the first and second complementary bit lines in the first interconnect layer.

2. The sensing circuit structure of claim 1, wherein the first bit line is disposed in the first interconnect layer, at least a portion of the first complementary bit line is disposed in the second interconnect layer, the first complementary bit line is coupled to the first sense amplifying structure after passing through a region of the second sense amplifying structure in the second interconnect layer, at least a portion of the second bit line is disposed in the second interconnect layer, the second bit line is coupled to the second sense amplifying structure after passing through a region of the first sense amplifying structure in the first interconnect layer, and the second complementary bit line is disposed in the first interconnect layer.

3. A sensing circuit structure of claim 2, wherein the equalization structure comprises:

a first equalizing pipe, wherein a gate of the first equalizing pipe is used for receiving a first equalizing signal, one of a source or a drain of the first equalizing pipe is connected with the first complementary bit line, and the other one of the source or the drain of the first equalizing pipe is used for receiving a first pre-charging voltage, and the first bit line, the first complementary bit line and the first sensing amplifying structure are pre-charged to the first pre-charging voltage based on the first equalizing signal;

a second equalizing pipe, wherein a gate of the second equalizing pipe is used for receiving a second equalizing signal, one of a source or a drain of the second equalizing pipe is connected with the second bit line, and the other one of the source or the drain of the second equalizing pipe is used for receiving a second pre-charging voltage, and the second equalizing pipe is used for pre-charging the second bit line, the second complementary bit line and the second sensing amplifying structure to the second pre-charging voltage based on the second equalizing signal.

4. A sensing circuit structure of claim 3, wherein the first equalization signal and the second equalization signal are the same equalization signal, and the first precharge voltage and the second precharge voltage are the same precharge voltage.

5. The sensing circuit structure of claim 4, wherein the drain of the first equalizing tube and the drain of the second equalizing tube are connected to receive the same pre-charge voltage.

6. A sensing circuit structure of claim 3, comprising:

the structural layer is also provided with a third sensing amplification structure and a fourth sensing amplification structure;

the third sensing amplification structure is connected with one of the adjacent storage arrays through a third bit line, the third sensing amplification structure is connected with the other of the adjacent storage arrays through a third complementary bit line, the fourth sensing amplification structure is connected with one of the adjacent storage arrays through a fourth bit line, and the fourth sensing amplification structure is connected with the other of the adjacent storage arrays through a fourth complementary bit line;

wherein one of the third bit line or the third complementary bit line is disposed in the first interconnect layer and the other is at least partially disposed in the second interconnect layer; one of the fourth bit line or the fourth complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer;

the equalizing structure directly connects the third complementary bit line and the fourth bit line for precharging the third bit line, the third complementary bit line, the third sense amplifying structure, the fourth bit line, the fourth complementary bit line, and the fourth sense amplifying structure;

wherein the equalization structure is directly connected with the third complementary bit line and the fourth bit line in the first interconnect layer.

7. A sensing circuit structure of claim 6, wherein the equalization structure further comprises:

a third equalizing pipe, disposed on one side of the first equalizing pipe in a word line extending direction, sharing the same gate with the first equalizing pipe, one of a source or a drain being connected to the third complementary bit line, and the other being configured to receive the first precharge voltage, and configured to precharge the third bit line, the third complementary bit line, and the third sense amplifying structure to the first precharge voltage based on the first equalizing signal;

and a fourth equalizing pipe, disposed on one side of the second equalizing pipe in a word line extending direction, sharing the same gate with the second equalizing pipe, one of a source or a drain being connected to the fourth bit line, and the other being configured to receive the second precharge voltage, and configured to precharge the fourth bit line, the fourth complementary bit line, and the fourth sense amplifying structure to the second precharge voltage based on the second equalizing signal.

8. The sensing circuit structure of claim 6, wherein the structural layer further comprises a first data sensing module and a second data sensing module;

a first data readout module comprising: a first input/output pipe, a third input/output pipe, a fifth input/output pipe and a seventh input/output pipe;

the source electrode of the first input/output tube is connected with a first input/output line, the drain electrode of the first input/output tube is connected with a first bit line, the source electrode of the third input/output tube is connected with a third input/output line, the drain electrode of the third input/output tube is connected with a second bit line, the source electrode of the fifth input/output tube is connected with a fifth input/output line, the drain electrode of the fifth input/output tube is connected with a third bit line, the source electrode of the seventh input/output tube is connected with a seventh input/output line, and the drain electrode of the seventh input/output tube is connected with a fourth bit line;

the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array;

the grid electrode of the first input/output tube, the grid electrode of the third input/output tube, the grid electrode of the fifth input/output tube and the grid electrode of the seventh input/output tube are connected together, and are used for receiving a column selection signal and conducting the first input/output tube, the third input/output tube, the fifth input/output tube and the seventh input/output tube based on the column selection signal;

the second data read-out module comprises a second input/output tube, a fourth input/output tube, a sixth input/output tube and an eighth input/output tube;

the source electrode of the second input/output tube is connected with a second input/output line, the drain electrode of the second input/output tube is connected with a first complementary bit line, the source electrode of the fourth input/output tube is connected with a fourth input/output line, the drain electrode of the fourth input/output tube is connected with a second complementary bit line, the source electrode of the sixth input/output tube is connected with a sixth input/output line, the drain electrode of the sixth input/output tube is connected with a third complementary bit line, the source electrode of the eighth input/output tube is connected with an eighth input/output line, and the drain electrode of the eighth input/output tube is connected with a fourth complementary bit line;

the first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent bit lines in the same memory array;

and the grid electrode of the second input/output tube, the grid electrode of the fourth input/output tube, the grid electrode of the sixth input/output tube and the grid electrode of the eighth input/output tube are connected together, and are used for receiving the column selection signal and conducting the second input/output tube, the fourth input/output tube, the sixth input/output tube and the eighth input/output tube based on the column selection signal.

9. The readout circuit structure of claim 1, wherein the first sense amplifying structure comprises:

a sense amplifying module connected to the first bit line through a sense bit line and to the first complementary bit line through a complementary sense bit line, for sensing a voltage of a memory cell of the memory array and outputting a logic 1 or 0 corresponding to the voltage;

the isolation module is connected between the complementary read bit line and the first complementary bit line, is connected between the read bit line and the first bit line, and is used for isolating signal interaction between the first bit line and the first complementary bit line and the read bit line and the complementary read bit line according to an isolation signal;

and the offset elimination module is connected between the read bit line and the first complementary bit line, is connected between the complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS tubes or PMOS tubes in the sensing amplification module according to an offset elimination signal.

10. The readout circuit structure of claim 9, wherein the sense amplification module comprises:

a gate of the first sense amplifying N transistor is connected with the first bit line, a drain of the first sense amplifying N transistor is connected with the complementary read bit line, a source of the first sense amplifying N transistor is connected with a second signal end, and when the sense amplifying module is in an amplifying stage, the second signal end is electrically connected with a voltage corresponding to a logic 0;

a grid electrode of the second sensing amplification N tube is connected with the first complementary bit line, a drain electrode of the second sensing amplification N tube is connected with the read bit line, and a source electrode of the second sensing amplification N tube is connected with the second signal end;

a gate of the first sense amplifying P transistor is connected with the read bit line, a drain of the first sense amplifying P transistor is connected with the complementary read bit line, a source of the first sense amplifying P transistor is connected with a first signal end, and when the sense amplifying module is in an amplifying stage, the first signal end is electrically connected with a voltage corresponding to a logic 1;

and the grid electrode of the second sensing amplification P tube is connected with the complementary read bit line, the drain electrode of the second sensing amplification P tube is connected with the read bit line, and the source electrode of the second sensing amplification P tube is connected with the first signal end.

11. The readout circuit structure of claim 10, wherein the gate structures of the first sense amplifying N transistor, the second sense amplifying N transistor, the first sense amplifying P transistor and the second sense amplifying P transistor extend in the same direction, the gate structures of the MOS transistors in the isolation module and the offset cancellation module extend in the same direction, and the gate structures of the first sense amplifying N transistor and the MOS transistors in the isolation module extend in the direction perpendicular to each other.

12. The readout circuit structure of claim 10, wherein the first sense amplifier P-transistor, the second sense amplifier P-transistor, the isolation module, and the offset cancellation module are disposed between the first sense amplifier N-transistor and the second sense amplifier N-transistor.

13. The sensing circuit structure of claim 9, wherein the isolation module comprises:

the grid electrode of the first isolation tube is used for receiving the isolation signal, the source electrode of the first isolation tube is connected with the first bit line, and the drain electrode of the first isolation tube is connected with the read bit line;

and the grid of the second isolation tube is used for receiving the isolation signal, the source of the second isolation tube is connected with the first complementary bit line, and the drain of the second isolation tube is connected with the complementary reading bit line.

14. A sensing circuit structure of claim 13, wherein the offset cancellation block comprises:

a first offset cancellation tube, wherein a grid electrode is used for receiving the offset cancellation signal, a source electrode is connected with the first bit line, and a drain electrode is connected with the complementary reading bit line;

and the grid of the second offset elimination tube is used for receiving the offset elimination signal, the source of the second offset elimination tube is connected with the first complementary bit line, and the drain of the second offset elimination tube is connected with the read bit line.

15. A sensing circuit structure of claim 14, wherein the source of the first isolation tube and the source of the first offset cancel tube are in communication and connect the first bit line; and the source electrode of the second isolation tube is connected with the source electrode of the second offset elimination tube and is connected with the first complementary bit line.

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