CN115542808A - Controller with FPGA chip, operation method thereof and rail transit equipment - Google Patents

Abstract

The invention discloses a controller with an FPGA chip, an operation method thereof and rail transit equipment, and relates to the technical field of rail transit vehicle-mounted equipment, wherein the controller with the FPGA chip comprises the following components: the system comprises a DSP chip, an FPGA chip, a solid-state memory and a dynamic memory; the DSP chip is in communication connection with the dynamic memory, an I/O pin of the DSP chip is electrically connected with a PROB pin of the FPGA chip, the solid-state memory comprises a FLASH memory, the DSP chip and the FPGA chip are respectively electrically connected with the solid-state memory through an SPI interface or a QSPI interface, and the DSP chip is also provided with a data input interface; the DSP chip is used for receiving a program through the data input interface, storing the program in the dynamic memory and controlling the potential of a PROB pin of the FPGA chip; the DSP chip is used for writing the program in the dynamic memory into the solid-state memory when the PROB pin of the FPGA chip is at a low potential; and so on. The method and the device can realize remote updating of the FPGA program and decoupling starting of the FPGA and the DSP.

Description

Controller with FPGA chip, operation method thereof and rail transit equipment

Technical Field

The invention relates to the technical field of rail transit vehicle-mounted equipment, in particular to a controller with an FPGA chip, an operation method of the controller and rail transit equipment.

Background

The configuration modes of the current controller with the FPGA are generally divided into a master mode and a slave mode. In the master mode, the FPGA is mainly used as a master, and a PROM or FLASH memory chip is configured outside the FPGA, and when the PROM or FLASH memory chip is powered on, the FPGA needs to actively read a program from the PROM or FLASH memory chip and then perform automatic configuration. The programming and updating of the FPGA need to use a special simulator, configuration is carried out through a JTAG interface, and power-on and boot are needed again after the completion. The main mode has disadvantages in that: 1. a special simulator must be used, and field after-sales personnel do not have enough equipment; 2. because the traction converter controllers are all installed below the vehicle body and are located in the closed case, the FPGA program is very inconvenient to upgrade, or the FPGA program cannot be upgraded on site due to structural and space limitations, the controller can only be detached to upgrade under a specific environment, and the operation is very complicated. 3. After the programming is finished, the power must be supplied again, and a new program can be loaded and operated. For the slave mode: the FPGA is used as a slave, the defect that a JTAG simulator is needed when the FPGA is used as a master mode is abandoned, a program can be remotely programmed, and the complicated steps of disassembling and upgrading the controller are avoided. In the mode, the DSP on the board card is used as a main part, the FPGA program is transmitted to the DSP through the upper computer, the DSP receives the program and then caches the program on the RAM, the program is stored on the external FLASH after verification information is added, the DSP reads the FPGA program from NANDFALSH and verifies the FPGA program every time the DSP is powered on, and the FPGA program is used for configuring the FPGA after the verification is successful. In the mode, the DSP is the core of the whole system, and the program configuration time sequence and the program upgrading logic of the FPGA are realized by the application program of the DSP. The disadvantages of this mode are: 1. the FPGA can be started only after the DSP is normally started; 2. the FPGA data is stored in a FLASH controlled by a DSP, the DSP is required to carry the data to a memory and then convert the data into the data with the corresponding format to be burnt and written into the FPGA when the data is started every time, and the data transferring steps are multiple and complicated; 3. the whole system is long in starting time, and a peripheral circuit connected with the FPGA is in an abnormal working state after being powered on.

Disclosure of Invention

In order to overcome the above defects in the prior art, embodiments of the present invention provide a controller with an FPGA chip, an operating method thereof, and a rail transit device, which solve the problems that a specific device is required in a master mode and other control chips (DSPs) are highly dependent in a slave mode, and can realize remote update of an FPGA program and also realize decoupling start of an FPGA and a DSP.

The embodiment of the invention has the following specific technical scheme:

a controller having an FPGA chip, comprising:

the system comprises a DSP chip, an FPGA chip, a solid-state memory and a dynamic memory; the DSP chip is in communication connection with the dynamic memory, an I/O pin of the DSP chip is electrically connected with a PROB pin of the FPGA chip, the solid-state memory comprises a FLASH memory, the DSP chip and the FPGA chip are respectively electrically connected with the solid-state memory through an SPI interface or a QSPI interface, and the DSP chip is also provided with a data input interface;

the DSP chip is used for receiving a program through the data input interface, storing the program in the dynamic memory and controlling the potential of a PROB pin of the FPGA chip; the DSP chip is used for writing the program in the dynamic memory into the solid-state memory when a PROB pin of the FPGA chip is at a low potential; and the FPGA chip is used for loading the program from the solid-state memory and starting the program when a PROB pin of the FPGA chip is at a high potential.

Preferably, the I/O pin of the DSP chip is electrically connected to the INIT _ B pin and the DONE pin of the FPGA chip;

the DSP chip is connected with an SPI bus of the solid-state memory through the SPI bus; the DSP chip, the FPGA chip and the solid-state memory are connected in a daisy chain mode.

Preferably, the DSP chip is configured to set the potential of the PROB pin of the FPGA chip to a high potential after the program in the dynamic memory is written in the solid-state memory.

Preferably, the FPGA chip is configured to set the DONE pin to a high potential after loading the program from the solid-state memory and starting the program.

A rail transit apparatus, comprising: a rail transit traction converter comprises a controller with an FPGA chip as described in any one of the above.

An operation method of a controller with an FPGA chip, which adopts the controller with the FPGA chip as any one of the above, comprises the following steps:

the DSP chip receives a program and stores the program in the dynamic memory;

after the program is stored in the dynamic memory, the DSP chip sets the potential of a PROB pin of the FPGA chip to be a low potential;

when the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory;

after the program is written into the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to be high potential;

and when the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

Preferably, when the potential of the PROB pin of the FPGA chip is a low potential, the FPGA chip is in a reset state; and when the potential of the PROB pin of the FPGA chip is high potential, the FPGA chip can be started.

Preferably, the operation method of the controller with the FPGA chip further includes the steps of:

before the DSP chip receives the program, the DSP chip receives an updating instruction of the upper computer, feeds back the state to the upper computer and changes the flag bit of the updating program into 1;

after the FPGA chip loads the program from the solid-state memory and is started smoothly, the FPGA chip changes the potential of a DONE pin into a high potential;

after the FPGA chip loads the program from the solid-state memory and is started smoothly, the DSP chip detects the potential of the DONE pin of the FPGA chip, and if the potential of the DONE pin of the FPGA chip is a high potential and the flag bit for updating the program is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number.

Preferably, if the potential of the PROB pin of the FPGA chip is a low potential and the flag bit of the update program is 1, the DSP chip writes the program in the dynamic memory into the solid-state memory again;

after the program is rewritten in the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to be a high potential, and when the PROB pin of the FPGA chip is under the high potential, the FPGA chip loads the program from the solid-state memory and starts.

Preferably, when the number of times that the DSP chip writes the program in the dynamic memory into the solid-state memory again reaches a preset number of times, the DSP chip outputs error information to the outside.

Preferably, the operation method of the controller with the FPGA chip further includes the steps of:

when the DSP chip does not receive an update instruction of an upper computer, the DSP chip detects the state of a DONE pin of the FPGA chip, and if the state of the DONE pin is a low potential, the DSP chip outputs information that the program is not stored in the solid-state memory;

and if the state of the DONE pin is high potential, the DSP chip reads the version number of a program in the FPGA chip and outputs version number information and/or information of successful start-up outwards.

The beneficial effect of this application is as follows:

the FPGA chip in the prior art can only be upgraded through a simulator under the condition of a master mode, and cannot be upgraded remotely. If a program in the FPGA chip is required to be upgraded remotely, the FPGA chip is required to be configured into a slave mode, a DSP chip or an MCU chip which is highly coupled with the starting of the FPGA chip is required outside, the program is required to be read from FLASH after being powered on every time, then the program is moved to an RAM, and then the program is burnt into the FPGA chip, so that the risk of data transmission is increased through a series of actions, the starting time of the whole system is prolonged, and the instability of the system during starting is increased. The application combines the two existing modes, utilizes the respective characteristics of the DSP chip and the FPGA chip, decouples the DSP chip and the FPGA chip, and reasonably avoids the defects in the prior art. That is to say, the data input interface of the DSP chip directly receives the program required by the FPGA chip which is remotely upgraded and stores the program in the dynamic memory, when the PROB pin of the FPGA chip is under the low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory, when the PROB pin of the FPGA chip is under the high potential, the FPGA chip can directly load the program from the external solid-state memory and start the program, and simultaneously, the DSP can also start the program applied by the DSP chip, so that a special simulator is not needed, the program upgrading efficiency is greatly improved, the upgrading cost is reduced, and the upgrading time is shortened. Secondly, the controller with the FPGA chip realizes the decoupling of the FPGA chip and the DSP chip in the starting process, and avoids the influence on the initial state of the system due to the starting time sequence. Finally, the method and the device can shorten the starting time of the controller with the FPGA chip and enhance the stability of the system. That is, in the prior art, when the slave mode is adopted by the FPGA chip, the time required for starting is boot of the DSP chip and the DSP chip guides the FPGA chip to start (including the DSP chip reading a program from the flash to the RAM, checking, and writing data in the RAM into the FPGA chip) and the DSP chip application program to start.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for facilitating the understanding of the present invention, and do not specifically limit the shapes, the proportional sizes, and the like of the respective members of the present invention. Those skilled in the art, having the benefit of the teachings of this invention, may choose from the various possible shapes and proportional sizes to implement the invention as a matter of case.

Fig. 1 is a schematic structural diagram of a controller having an FPGA chip according to an embodiment of the present invention.

FIG. 2 is a flow chart illustrating steps of a method for operating a controller having an FPGA chip according to an embodiment of the present invention.

Fig. 3 is a flow chart illustrating the principle of the DSP chip operation in the embodiment of the present invention.

Detailed Description

The details of the present invention can be more clearly understood in conjunction with the accompanying drawings and the description of the embodiments of the present invention. However, the specific embodiments of the present invention described herein are for the purpose of illustration only and are not to be construed as limiting the invention in any way. Any possible variations based on the present invention may be conceived by the skilled person in the light of the teachings of the present invention, and these should be considered to fall within the scope of the present invention.

In order to solve the problems that a specific device is needed in a master mode and other control chips (DSPs) are highly depended on in a slave mode, and the remote update of an FPGA program and the decoupling start of the FPGA and the DSPs can be realized, a controller with an FPGA chip is provided in the present application, fig. 1 is a schematic structural diagram of the controller with the FPGA chip in an embodiment of the present invention, and as shown in fig. 1, the controller with the FPGA chip may include: DSP chip, FPGA chip, solid state memory, dynamic memory.

Wherein, in the controller with the FPGA chip, the FPGA chip is configured as a master mode. The DSP chip is in communication connection with the dynamic memory, for example, the DSP chip and the dynamic memory can be connected through a data bus and an address bus to realize data transmission. The dynamic memory may employ SDRAM memory.

The solid-state memory is a FLASH memory, and the DSP chip and the FPGA chip are electrically connected with the solid-state memory through the SPI interface or the QSPI interface respectively. The I/O pin of the DSP chip is electrically connected with the PROB pin of the FPGA chip.

The DSP chip is also provided with a data input interface, can be used for being connected with an upper computer through the data input interface, and can be an RS232 serial port bus through the data input interface. For example, the upper computer can send the programs required by the FPGA to the DSP through the RS232 serial port bus. The DSP chip is used for receiving a program, namely the program required by the FPGA sent by the upper computer, and storing the program in the dynamic memory. Meanwhile, the DSP chip can be used for controlling the potential of the PROB pin of the FPGA chip. The potential of the PROB pin of the FPGA chip can comprise a high potential and a low potential, wherein the high potential is 1, and the low potential is 0.

In this application, the upper computer may be a CPU or a system-level controller of the control system. As a feasible, the interface between the upper computer and the DSP chip may also adopt a CAN bus or an ethernet.

It should be noted that when the potential of the PROB pin of the FPGA chip is a low potential, the FPGA chip is in a reset state, and at this time, the FPGA chip may not load the program therein from the solid-state memory. And when the potential of the PROB pin of the FPGA chip is high potential, the FPGA chip starts to load programs from an external memory.

And the DSP chip is used for writing the program in the dynamic memory into the solid-state memory when the PROB pin of the FPGA chip is at a low potential. After the program in the dynamic memory is written into the solid-state memory, the DSP chip controls the potential of the PROB pin of the FPGA chip to be changed into high potential. The FPGA chip is used for loading a program from the solid-state memory and starting when a PROB pin of the FPGA chip is at a high potential.

In addition, the I/O pin of the DSP chip can be electrically connected with the INIT _ B pin and the DONE pin of the FPGA chip. And when the FPGA chip loads a program from the solid-state memory and is started smoothly, the FPGA chip is used for changing the potential of the DONE pin into a high potential. The state interaction between the DSP chip and the FPGA chip can be realized through an INIT _ B pin, so that the DSP chip reads the configuration state of the FPGA chip.

The DSP chip is connected with the SPI bus of the solid-state memory through the SPI bus. Furthermore, the DSP chip, the FPGA chip and the solid-state memory are connected in a daisy chain mode.

The present application further provides an operation method of a controller with an FPGA chip, which uses any one of the above controllers with an FPGA chip, and fig. 2 is a flowchart illustrating steps of the operation method of the controller with an FPGA chip according to an embodiment of the present invention, as shown in fig. 2, the operation method may include the following steps:

s101: and the DSP chip receives an updating instruction of the upper computer, feeds back the state to the upper computer and changes the flag bit of the updating program into 1.

Fig. 3 is a schematic flow chart of the operation of the DSP chip in the embodiment of the present invention, as shown in fig. 3, in this step, as is feasible, after the DSP chip store or the system is reset, initialization may be performed first, the Flag of the update program is restored to 0, and the counter count is restored to 0. Before the DSP chip receives the program, the DSP chip reads whether the upper computer has an updating instruction or not, for example, the state of an RS232 serial port bus can be read, so as to detect whether the updating instruction exists or not. If the upper computer has an updating instruction, the DSP chip feeds back information to the upper computer, waits for and prepares to receive a program required by the FPGA, and changes the Flag of the updating program to 1.

S102: the DSP chip receives the program and stores the program in the dynamic memory.

In this step, after the upper computer receives the feedback information, the super terminal software, for example, an Xmodem protocol may be used to transmit a binary file (bin file) program generated by the FPGA development tool to the DSP through the RS232 serial port. The DSP chip receives the program and stores the program in the dynamic memory.

S103: after the program is stored in the dynamic memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a low potential.

As shown in fig. 3, after the program storage in the dynamic memory is completed, the DSP chip sets the potential of the PROB pin of the FPGA chip to a low potential, for example, to 0, at which time the FPGA chip becomes a reset state. As a possibility, the counter count is incremented by 1.

S104: and when the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory.

In this step, when the PROB pin of the FPGA chip is at a low potential, the DSP chip converts the program in the dynamic memory into fixed format data, and writes the data into the solid-state memory through the SPI bus.

S105: after the program is written into the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to be high potential.

In this step, after the program is written in the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential, that is, to 1, and at this time, the FPGA chip becomes capable of being started.

S106: and when the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads a program from the solid-state memory and starts.

In this step, as shown in fig. 3, when the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads a program from the solid-state memory and starts up.

S107: after the FPGA chip loads a program from the solid-state memory and is started smoothly, the FPGA chip changes the potential of the DONE pin into a high potential. If the program is loaded from the solid-state memory unsuccessfully on the FPGA chip, the potential of the DONE pin is still low potential.

S108: after the FPGA chip loads the program from the solid-state memory and is started smoothly, the DSP chip detects the potential of the DONE pin of the FPGA chip, and if the potential of the DONE pin of the FPGA chip is high potential and the flag bit of the update program is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number.

After the step S106 is executed, waiting for a period of time, the DSP chip detects the potential of the DONE pin of the FPGA chip, and if the potential of the DONE pin of the FPGA chip is a high potential and the flag bit of the update program is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number, for example, the version number may be output through an RS232 serial bus. At this time, it is demonstrated that the FPGA chip loading program is successfully started.

And if the potential of the PROB pin of the FPGA chip is low potential and the flag bit of the update program is 1, the DSP chip writes the program in the dynamic memory into the solid-state memory again. At this time, it is necessary to rewrite the program in the dynamic memory into the solid-state memory, which indicates that the FPGA chip is not loaded with the program smoothly or cannot be started. After the program is rewritten in the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to be a high potential, the counter count is added by 1 as feasible, and when the PROB pin of the FPGA chip is under the high potential, the FPGA chip loads the program from the solid-state memory and starts.

And circulating in this way, when the number of times that the DSP chip writes the program in the dynamic memory into the solid-state memory again reaches the preset number of times, namely the counter count reaches the preset number of times, for example, reaches 3 times, the DSP chip outputs error reporting information outwards. For example, the output can be through an RS232 serial port bus. At this time, it can be understood that the program sent by the upper computer is not the program of the model corresponding to the FPGA chip.

S109: when the DSP chip does not receive the updating instruction of the upper computer, the DSP chip detects the state of the DONE pin of the FPGA chip, and if the state of the DONE pin is low potential, the DSP chip outputs information that no program is stored in the solid-state memory to the outside. And if the state of the DONE pin is high potential, the DSP chip reads the version number of the program in the FPGA chip and outputs version number information and/or information of successful start-up outwards. This step may be performed selectively.

If the controller with the FPGA chip does not need to update the program, the DSP chip and the FPGA chip can be started independently after being electrified, so that the starting time of the system is shortened, and the stability of the system is improved.

The FPGA chip in the prior art can only be upgraded through a simulator under the condition of a master mode, and cannot be upgraded remotely. If a program in the FPGA chip is required to be upgraded remotely, the FPGA chip is required to be configured into a slave mode, a DSP chip or an MCU chip which is highly coupled with the starting of the FPGA chip is required outside, the program is required to be read from FLASH after being powered on every time, then the program is moved to an RAM, and then the program is burnt into the FPGA chip, so that the risk of data transmission is increased through a series of actions, the starting time of the whole system is prolonged, and the instability of the system during starting is increased. The application combines the two existing modes, utilizes the respective characteristics of the DSP chip and the FPGA chip, decouples the DSP chip and the FPGA chip, and reasonably avoids the defects in the prior art. That is to say, the data input interface of the DSP chip directly receives the program required by the FPGA chip which is remotely upgraded and stores the program in the dynamic memory, when the PROB pin of the FPGA chip is under the low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory, when the PROB pin of the FPGA chip is under the high potential, the FPGA chip can directly load the program from the external solid-state memory and start the program, and simultaneously, the DSP can also start the program applied by the DSP chip, so that a special simulator is not needed, the program upgrading efficiency is greatly improved, the upgrading cost is reduced, and the upgrading time is shortened. Secondly, the controller with the FPGA chip realizes the decoupling of the FPGA chip and the DSP chip in the starting process, and avoids the influence on the initial state of the system due to the starting time sequence. Finally, the method and the device can shorten the starting time of the controller with the FPGA chip and enhance the stability of the system. That is, in the prior art, when the slave mode is adopted by the FPGA chip, the time required for starting is boot of the DSP chip and the DSP chip guides the FPGA chip to start (including the DSP chip reading a program from the flash to the RAM, checking, and writing data in the RAM into the FPGA chip) and the DSP chip application program to start.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

While the present application has been described with examples, those of ordinary skill in the art will appreciate that there are numerous variations and permutations of the present application without departing from the spirit of the application, and it is intended that the appended claims encompass such variations and permutations without departing from the spirit of the application.

Claims (11)

1. A controller having an FPGA chip, comprising:

the system comprises a DSP chip, an FPGA chip, a solid-state memory and a dynamic memory; the DSP chip is in communication connection with the dynamic memory, an I/O pin of the DSP chip is electrically connected with a PROB pin of the FPGA chip, the solid-state memory comprises a FLASH memory, the DSP chip and the FPGA chip are respectively electrically connected with the solid-state memory through an SPI interface or a QSPI interface, and the DSP chip is also provided with a data input interface;

the DSP chip is used for receiving a program through the data input interface, storing the program in the dynamic memory and controlling the potential of a PROB pin of the FPGA chip; the DSP chip is used for writing the program in the dynamic memory into the solid-state memory when a PROB pin of the FPGA chip is at a low potential; the FPGA chip is used for loading the program from the solid-state memory and starting when a PROB pin of the FPGA chip is at a high potential.

2. The controller with the FPGA chip of claim 1, wherein the I/O pin of the DSP chip is further electrically connected with an INIT _ B pin and a DONE pin of the FPGA chip;

the DSP chip is connected with an SPI bus of the solid-state memory through the SPI bus; the DSP chip, the FPGA chip and the solid-state memory are connected in a daisy chain mode.

3. The controller with an FPGA chip of claim 1, wherein said DSP chip is configured to set a potential of a PROB pin of said FPGA chip to a high potential after said program in said dynamic memory is written into said solid-state memory.

4. The controller with an FPGA chip of claim 2, wherein said FPGA chip is configured to set said DONE pin to a high potential after said program is loaded from said solid state memory and started.

5. A rail transit apparatus characterized in that it comprises: rail transit traction inverter comprising a controller with an FPGA chip according to any of claims 1 to 4.

6. An operation method of a controller with an FPGA chip using the controller with the FPGA chip according to any one of claims 1 to 4, characterized by comprising the steps of:

the DSP chip receives a program and stores the program in the dynamic memory;

after the program is stored in the dynamic memory, the DSP chip sets the potential of a PROB pin of the FPGA chip to be a low potential;

when the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory;

after the program is written into the solid-state memory, the DSP chip sets the potential of a PROB pin of the FPGA chip to be high potential;

and when the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

7. The operating method of a controller with an FPGA chip as recited in claim 6, wherein when a potential of a PROB pin of the FPGA chip is a low potential, the FPGA chip is in a reset state; and when the potential of the PROB pin of the FPGA chip is high potential, the FPGA chip can be started.

8. The method of claim 6, further comprising the steps of:

before the DSP chip receives the program, the DSP chip receives an updating instruction of the upper computer, feeds back the state to the upper computer and changes the flag bit of the updating program into 1;

after the FPGA chip loads the program from the solid-state memory and is started smoothly, the FPGA chip changes the potential of a DONE pin into a high potential;

after the FPGA chip loads the program from the solid-state memory and is started smoothly, the DSP chip detects the potential of the DONE pin of the FPGA chip, and if the potential of the DONE pin of the FPGA chip is a high potential and the flag bit for updating the program is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number.

9. The method according to claim 8, wherein if the potential of the PROB pin of the FPGA chip is low and the flag bit for updating the program is 1, the DSP chip writes the program in the dynamic memory into the solid-state memory again;

after the program is rewritten in the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to be a high potential, and when the PROB pin of the FPGA chip is under the high potential, the FPGA chip loads the program from the solid-state memory and starts.

10. The method according to claim 9, wherein when the number of times the DSP chip rewrites the program in the dynamic memory into the solid-state memory reaches a preset number, the DSP chip outputs an error notification message to the outside.

11. The method of claim 9, further comprising the steps of:

when the DSP chip does not receive an update instruction of an upper computer, the DSP chip detects the state of a DONE pin of the FPGA chip, and if the state of the DONE pin is a low potential, the DSP chip outputs information that the program is not stored in the solid-state memory;

and if the state of the DONE pin is high potential, the DSP chip reads the version number of the program in the FPGA chip and outputs version number information and/or information of successful start-up outwards.

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