CN115483823A - Switching power factor corrector and AC/DC converter - Google Patents
Switching power factor corrector and AC/DC converter Download PDFInfo
- Publication number
- CN115483823A CN115483823A CN202211150839.4A CN202211150839A CN115483823A CN 115483823 A CN115483823 A CN 115483823A CN 202211150839 A CN202211150839 A CN 202211150839A CN 115483823 A CN115483823 A CN 115483823A
- Authority
- CN
- China
- Prior art keywords
- power factor
- resistor
- voltage
- inductor
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 49
- 239000003990 capacitor Substances 0.000 claims description 26
- 238000012545 processing Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims description 2
- 238000012937 correction Methods 0.000 abstract description 11
- 238000013461 design Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 230000001939 inductive effect Effects 0.000 description 8
- 238000004146 energy storage Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 101150096622 Smr2 gene Proteins 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Abstract
The present disclosure provides a switching power factor corrector and an AC/DC converter, wherein the switching power factor corrector includes a first boost circuit connected between a first alternating current input terminal and a first direct current output terminal, and a second boost circuit connected between a second alternating current input terminal and the first direct current output terminal, wherein the switching power factor corrector operates the first boost circuit and the second boost circuit is turned off in a positive half cycle of an alternating current input voltage received between the first alternating current input terminal and the second alternating current input terminal; during the negative half cycle of the AC input voltage, the second boost circuit is operated and the first boost circuit is turned off to provide a stable DC output voltage between the first DC output terminal and ground. Therefore, the power factor correction without a rectifier bridge can be realized, the power loss of the alternating current rectifier bridge is saved, the power factor is improved, the design difficulty of a control chip is reduced, the integration level of the whole system is improved, and the cost is effectively reduced.
Description
Technical Field
The disclosure relates to the technical field of switching power supplies, in particular to a switching power factor corrector and an AC/DC converter.
Background
In power electronics, AC/DC is called rectification, DC/AC is called inversion, AC/AC is called alternating current variable frequency transformation, and DC/DC is called direct current/direct current transformation. It is worth noting that in most electrical devices, the power source is directly from the AC power grid, but almost all circuits need to be powered by DC power, and therefore the AC/DC converter becomes an essential part of many electronic products. In order to convert ac to dc, various conversion methods have been designed, the simplest and most common of which is a bridge rectifier circuit, which is widely used in various switching power supplies.
The 220V AC power network supplies DC power after input rectification and filtering, which is a basic rectification technology widely applied in power electronic technology and electronic instruments. The conventional AC/DC converter is composed of a diode bridge type rectifying circuit and an electrolytic capacitor filter circuit as shown in fig. 1. The alternating current commercial power is rectified by a diode and filtered by a large capacitor to obtain relatively smooth direct current voltage, and then the direct current voltage is subjected to DC/DC conversion by a direct current converter to obtain required output voltage. A rectifier-capacitor filter circuit is a combination of a non-linear element and an energy storage element. The large-capacity capacitor is used for reducing output voltage ripples and can provide necessary energy storage for a load when a system is powered down. However, since the rectified input voltage charges the capacitor only at a moment higher than the capacitor voltage, the input current is spike-like and has a large number of harmonics, as shown in fig. 2. A large amount of current harmonic components flow back into the power grid to cause harmonic pollution to the power grid, and as a result, accidents such as noise, misoperation, overheating and even burning of power utilization equipment occur; also, losses in the power distribution system conductors and transformers are increased, and the normal operation of various radio and radar devices is severely disturbed. On the other hand, the "second order effect" is generated, i.e. the current flows through the line impedance causing harmonic voltage drops, which in turn causes distortion of the grid.
There are two main approaches to the solution of harmonic pollution: the harmonic compensation device is adopted to compensate harmonic waves, and a Power Factor Correction (PFC) circuit is introduced into the power electronic circuit. The adoption of the PFC technology is an active method, and can fundamentally eliminate harmonic sources.
A conventional single-phase active power factor correction circuit (APFC) employs a silicon rectifier bridge as a pre-stage AC/DC converter circuit. The conduction losses of the system include the conduction losses introduced by the two rectifier diodes. In high-power low-voltage PFC application, the on-state loss of the full bridge directly influences the working efficiency of the whole machine. To further improve the performance of high PFC rectifiers, more and more researchers are beginning to study PFC circuit topologies without rectifier bridges. Compared with the traditional silicon rectifier bridge single-phase APFC, the main circuit of the non-rectifier bridge topology only needs two power semiconductor devices to form a current circuit at any time, so that the conduction loss can be reduced, and the efficiency is further improved. Particularly under the condition of low voltage and large current, the bridgeless circuit has higher efficiency and better development prospect.
As shown in fig. 3a to 3c, several main techniques of the modern rectifying-bridge-free power factor correction technique are: 1) A conventional rectifying bridge-less BOOST power factor correction circuit (shown in fig. 3 a); 2) A common-drain bidirectional switch type rectifying bridge-free power factor correction circuit (shown in fig. 3 b); 3) Totem-pole type non-rectifying bridge power factor correction circuits (shown in fig. 3 c) and the like, and the main disadvantages of these circuits are: (1) Switching power is limited to operate only in Discontinuous Current Mode (DCM); (2) the common mode interference and the differential mode interference are large; (3) low conversion efficiency; (4) the control is complex and the sampling is difficult; (5) The circuit is complicated, the number of used components is too much, and (6) the manufacturing cost is high. Therefore, it is necessary to intensively study and propose a new method for improvement.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides a switching power factor corrector and an AC/DC converter, which can save power loss of an AC rectifier bridge, improve power factor, reduce design difficulty of a control chip, improve integration level of an overall system, and simultaneously effectively reduce cost thereof.
In one aspect the present disclosure provides a switching power factor corrector, comprising:
the first booster circuit is connected between the first alternating current input end and the first direct current output end; and
a second boost circuit connected between the second AC input terminal and the first DC output terminal,
wherein the switching power factor corrector receives an AC input voltage between a first AC input terminal and a second AC input terminal, provides a DC output voltage between a first DC output terminal and ground,
in the positive half cycle of the AC input voltage, the first boost circuit is operated and the second boost circuit is turned off,
in the negative half cycle of the AC input voltage, the second boost circuit is active and the first boost circuit is off.
Preferably, the aforementioned first booster circuit includes:
the first inductor and the first diode are connected between the first alternating current input end and the first direct current output end in series, and the second end of the first inductor is connected with the anode of the first diode;
and the second switch tube is connected between the second alternating current input end and the ground.
Preferably, the aforementioned second booster circuit includes:
the second inductor and the second diode are connected between the second alternating current input end and the first direct current output end in series, and the second end of the second inductor is connected with the anode of the second diode;
and the third switching tube is connected between the second end of the second inductor and the ground, and the fourth switching tube is connected between the first alternating current input end and the ground.
Preferably, the first switch tube is grounded via a first detection resistor, and when the first boost circuit operates, the first detection resistor provides a first inductor current signal flowing through the first inductor.
Preferably, the third switching tube is grounded via a second detection resistor, and when the second boost circuit operates, the second detection resistor provides a second inductor current signal flowing through the second inductor.
Preferably, the first switch tube and the third switch tube are grounded via a common detection resistor, and the detection resistor provides a first inductor current signal flowing through the first inductor when the first boost circuit operates, and provides a second inductor current signal flowing through the second inductor when the second boost circuit operates.
Preferably, the aforementioned switching power factor corrector further comprises:
an input capacitor connected between the first and second ac input terminals, configured to high-frequency filter the aforementioned ac input voltage;
an output capacitor connected between the first DC output terminal and ground.
Preferably, the aforementioned switching power factor corrector further comprises:
a control circuit configured to generate a switch control signal according to the detection signal, the first/second inductor current signal and the feedback voltage of the sampled DC output voltage, and generate a first control signal, a second control signal, a third control signal and a fourth control signal through processing the switch control signal to be correspondingly and sequentially provided to the control ends of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube,
the detection signal is used for representing the states of the positive half cycle and the negative half cycle of the operation of the alternating current input voltage.
Preferably, the aforementioned control circuit includes:
the detection unit is coupled to the first alternating current input end and the second alternating current input end and outputs the detection signal;
an output feedback unit configured to sample the aforementioned direct current output voltage and generate the aforementioned feedback voltage by voltage division;
the positive input end of the operational amplifier is connected with a preset reference voltage, the negative input end of the operational amplifier is connected with the output feedback unit and is connected with the feedback voltage, and the output end of the operational amplifier provides a first voltage signal;
a first comparator, a non-inverting input terminal of which is connected to the first voltage signal, an inverting input terminal of which is connected to ground through the detection resistor to obtain the current sensing signal, and an output terminal of which provides a second voltage signal;
a logic control unit configured to generate the aforementioned switch control signal according to the aforementioned detection signal and the aforementioned second voltage signal;
a driver configured to generate the aforementioned first control signal, second control signal, third control signal, and fourth control signal, respectively, according to processing of the aforementioned switch control signal.
Preferably, the aforementioned detection unit includes a first resistor, a second resistor, and a third resistor connected to each other, and a second comparator,
the first end of the first resistor is connected to the second alternating current input end, the second end of the first resistor is connected to the non-inverting input end of the second comparator through a third resistor, the first end of the second resistor is connected to the first alternating current input end, the second end of the second resistor and the second end of the first resistor are connected to the first end of the third resistor together, the inverting input end of the second comparator is grounded, and the output end of the second comparator is used for providing the detection signal.
Preferably, the output feedback unit includes a fourth resistor, a fifth resistor and a sixth resistor connected in series between the first dc output terminal and ground, and a connection node of the fifth resistor and the sixth resistor is used for providing the feedback voltage.
Preferably, the aforementioned control circuit further comprises:
and the high-pass filter comprises a seventh resistor and a first capacitor which are connected between the output end of the operational amplifier and the ground in series.
Preferably, the second control signal and the fourth control signal are a pair of complementary signals, a high level of the second control signal is used to maintain the on state of the second switch tube and the off state of the fourth switch tube, and a low level of the second control signal is used to maintain the off state of the second switch tube and the on state of the fourth switch tube.
Preferably, the ac input voltage operates in a positive half cycle, the second control signal maintains a high level state, and the first switch tube is turned on and off at a high frequency during the period, so as to provide power to the first dc output terminal through the first inductor;
the third switch tube is turned on and off at a high frequency during the period, so as to provide electric energy for the first dc output end through the second inductor.
Preferably, any one of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube is an N-channel metal oxide semiconductor field effect transistor.
In another aspect the present disclosure provides an AC/DC converter, comprising: a switching power factor corrector as hereinbefore described.
The beneficial effects of this disclosure are: the present disclosure provides a switching power factor corrector and an AC/DC converter, wherein the switching power factor corrector comprises a first boost circuit connected between a first alternating current input terminal and a first direct current output terminal, and a second boost circuit connected between a second alternating current input terminal and a first direct current output terminal, wherein the switching power factor corrector receives an alternating current input voltage between the first alternating current input terminal and the second alternating current input terminal, provides a direct current output voltage between the first direct current output terminal and ground, and during a positive half cycle of the alternating current input voltage, the first boost circuit operates and the second boost circuit is turned off; in the negative half cycle of the AC input voltage, the second boost circuit is active and the first boost circuit is off. The switching power factor corrector provided by the disclosure utilizes two boosting circuits to provide electric energy to an output end according to the alternate work of positive and negative half cycles of alternating current input voltage, does not interfere with each other and has the same working mode, perfectly solves the problem of inductive current shunt, realizes the circuit structure of rectifying power factor correction without a rectifier bridge, saves the power loss of the alternating current rectifier bridge, improves the power factor, not only reduces the design difficulty of a control chip, but also improves the integration level of the whole system, and effectively reduces the cost.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 shows a circuit schematic of a conventional AC/DC converter with a bridge rectifier circuit;
FIG. 2 is a schematic diagram showing waveforms of input voltage and input current of the conventional AC/DC converter shown in FIG. 1;
FIGS. 3a to 3c are schematic diagrams illustrating several prior art PFC circuits without rectifier bridge, respectively;
FIG. 4 is a schematic diagram of a bridge-less switching power factor corrector and a control circuit thereof according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of the control circuit of FIG. 4;
FIG. 6 shows a circuit schematic of a detection unit in the control circuit of FIG. 5;
FIG. 7 is a timing diagram illustrating the operation of various signals in the switching power factor corrector of FIG. 4;
FIG. 8 is a schematic diagram of the current path of the switching power factor corrector of FIG. 4 when the AC input voltage is operating in the positive half cycle;
fig. 9a and 9b are schematic diagrams of current paths of the switching power factor corrector shown in fig. 4 under the condition that the third switching tube Q3 is turned on and off when the alternating input voltage operates in a negative half period, respectively.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 4 shows a schematic diagram of a switching power factor corrector without a rectifier bridge and a control circuit thereof according to an embodiment of the present disclosure, fig. 5 shows a schematic diagram of a structure of the control circuit shown in fig. 4, and fig. 6 shows a schematic diagram of a circuit of a detection unit in the control circuit shown in fig. 5.
On the one hand, the embodiment of the disclosure provides a switching power factor corrector, which can be applied to an AC-to-DC switching power supply system, two boosting circuits are connected in parallel and work alternately to replace a traditional AC rectifier bridge, so that active power factor correction without the AC rectifier bridge is realized, and the switching power factor corrector is simple to control, low in loss and low in cost.
Specifically, referring to fig. 4, the switching power factor corrector 200 includes: an ac input circuit 201, an input capacitor Cin, a first boost circuit connected between a first ac input terminal a and a first dc output terminal c, and a second boost circuit connected between a second ac input terminal b and the first dc output terminal c,
the ac input circuit 201 is configured to provide the aforementioned ac input voltage V AC (ii) a The input capacitor Cin is connected in parallel between the first ac input terminal a and the second ac input terminal b of the ac input circuit 201, and is configured to couple an ac input voltage V AC Carrying out high-frequency filtering; the first booster circuit comprises a first inductor L1, a first switch tube Q1, a first diode D1 and a second switch tube Q2; the second boost circuit comprises a second inductor L2, a third switching tube Q3, a second diode D2 and a fourth switching tube Q4,
wherein the switching power factor corrector 200 has a first AC input terminal a and a second AC input terminalReceiving an AC input voltage V between the input terminals b AC A dc output voltage Vo is provided between the first dc output c and Ground (GND), at which ac input voltage V AC In the positive half cycle, the first boost circuit is operated and the second boost circuit is turned off; at the AC input voltage V AC During the negative half-cycle of (a), the second boost circuit is active and the first boost circuit is off.
Specifically, in the first boost circuit of the present embodiment, the first inductor L1 and the first diode D1 are connected in series between the first ac input terminal a and the first dc output terminal b, the second terminal of the first inductor L1 is connected to the anode of the first diode D1, the first switch Q1 is connected between the second terminal of the first inductor L1 and the ground, and the second switch Q2 is connected between the second ac input terminal b and the ground.
In the second boost circuit of the present embodiment, the second inductor L2 and the second diode D2 are connected in series between the second ac input terminal b and the first dc output terminal c, the second terminal of the second inductor L2 is connected to the anode of the second diode D2, the third switching tube Q3 is connected between the second terminal of the second inductor L2 and the ground, and the fourth switching tube Q4 is connected between the first ac input terminal a and the ground.
In this embodiment, the first switch Q1 and the third switch Q3 are grounded via a common detection resistor Rcs, and when the first boost circuit operates, the detection resistor Rcs provides a first inductor current signal Vcs1 flowing through the first inductor L1; when the second boost circuit operates, the sensing resistor Rcs provides a second inductor current signal Vcs2 flowing through the second inductor L2.
In this embodiment, the input capacitor Cin, the output capacitor Co, and the detection resistor Rcs are common to the two boosting circuits.
It should be noted that, in an alternative embodiment, the aforementioned first switch Q1 and the third switch Q3 are respectively connected to the ground through independent detection resistors, for example, the first switch Q1 is connected to the ground through a first detection resistor, and when the first boost circuit operates, the first detection resistor provides a first inductor current signal Vcs1 flowing through the first inductor L1; the third switch Q3 is grounded via a second detection resistor, which provides a second inductor current signal Vcs1 flowing through the second inductor L2 when the second boost circuit operates, which is not limited herein.
Referring to fig. 4 and 5, in the present embodiment, the aforementioned switching power factor corrector further includes a control circuit 210, the control circuit 210 is configured to generate a switching control signal PWM according to a detection signal V2, an inductive current signal Vcs (the inductive current signal Vcs is the aforementioned first inductive current signal Vcs1 when the first boost circuit operates, and the aforementioned second inductive current signal Vcs2 when the second boost circuit operates, hereinafter collectively shown as the inductive current signal Vcs), and a feedback voltage Vfb of the sampled dc output voltage Vo, and generate first to fourth control signals (S1 to S4) through processing of the switching control signal PWM to be correspondingly provided to the control terminals of the aforementioned first to fourth switching transistors (Q1 to Q4), wherein the detection signal V2 is used to represent the ac input voltage V2 AC Positive and negative half cycle states of operation.
Further, referring to fig. 5, the aforementioned control circuit 210 includes: a driver 211, a logic control unit 212, a detection unit 213, a first comparator 214, an operational amplifier 215, and an output feedback unit 216, wherein,
the detecting unit 213 is coupled to the first ac input terminal a and the second ac input terminal b, and outputs a detecting signal V2, wherein the detecting signal V2 is used to represent the ac input voltage V AC The positive and negative half cycle states of operation;
the output feedback unit 216 is configured to sample the dc output voltage Vo, and generate a feedback voltage Vfb by voltage division;
the operational amplifier 215 has a positive input terminal connected to a preset reference voltage Vref, a negative input terminal connected to the output feedback unit 216, and an output terminal providing a first voltage signal Vc;
the non-inverting input terminal of the first comparator 214 is connected to the first voltage signal Vc, the inverting input terminal obtains the current sensing signal Vcs through the connected detection resistor Rcs, and the output terminal provides the second voltage signal V1;
the logic control unit 212 is configured to generate the aforementioned switching control signal PWM according to the aforementioned detection signal V2 and the aforementioned second voltage signal V1;
the driver 211 is configured to generate the aforementioned first control signal S1, second control signal S2, third control signal S3 and fourth control signal S4, respectively, according to processing the aforementioned switching control signal PWM.
Further, referring to fig. 6, the aforementioned detection unit 213 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected to each other, and a second comparator 2131, wherein,
a first end of the first resistor R1 is connected to the second ac input end b, a second end of the first resistor R1 is connected to the non-inverting input end of the second comparator 2131 through the third resistor R3, a first end of the second resistor R2 is connected to the first ac input end a, a second end of the second resistor R2 and a second end of the first resistor R1 are connected to a first end of the third resistor R3, an inverting input end of the second comparator 2131 is grounded, and an output end of the second comparator 2131 is configured to provide the aforementioned detection signal V2.
It will be appreciated that the ac input voltage V in the above embodiments and shown in fig. 6 AC The positive and negative half-cycle detection circuit is only an exemplary schematic configuration, and in alternative embodiments, other circuit configurations are possible, which are intended to obtain a representation of the ac input voltage V AC The detection signal V2 may operate in positive and negative half periods, which is not limited herein. In the above embodiment, the AC input voltage V AC After passing through the first resistor R1, the second resistor R2 (as a starting resistor), and the third resistor R3 (as a current limiting resistor), the non-inverting input terminal of the second comparator 2131 still obtains an ac waveform completely synchronous with the input (in practical applications, for example, a voltage clamp circuit may be added, such as 2 diodes connected in parallel to ensure the safety of the second comparator 2131), and compares the ac waveform with the ground signal at the inverting input terminal, and when the ac waveform is high, the ac input voltage V is obtained AC Working in a positive half period, and outputting a high-level detection signal V2; at low time of AC input voltage V AC And the detection circuit works in the negative half period and outputs a low-level detection signal V2.
Further, the aforementioned output feedback unit 216 includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 connected in series between the first dc output terminal c and the ground, and a connection node of the fifth resistor R5 and the sixth resistor R6 is used for providing the aforementioned feedback voltage Vfb.
Further, the aforementioned control circuit 210 further includes a high-pass filter 217, and the high-pass filter 217 includes a seventh resistor R7 and a first capacitor C1 connected in series between the output terminal of the operational amplifier 215 and the ground.
Further, any one of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 is an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET, which may also be referred to as MOS Transistor for short).
In the above embodiment, MOSFETs are used as the boosting switching elements Q1 to Q4, but in other alternative embodiments, switching elements such as IGBTs and bipolar transistors may be used, and the present invention is not limited thereto.
Fig. 7 shows operation timing diagrams of respective signals in the switching power factor corrector shown in fig. 4, fig. 8 shows a schematic current path diagram of the switching power factor corrector shown in fig. 4 when the ac input voltage operates in a positive half cycle, and fig. 9a and 9b respectively show a schematic current path diagram of the switching power factor corrector shown in fig. 4 when the third switching tube Q3 is turned on and off when the ac input voltage operates in a negative half cycle.
Further, referring to fig. 7, the second control signal S2 and the fourth control signal S4 are a pair of complementary signals, and a high level of the second control signal S2 is used to maintain the on state of the second switch Q2 and the off state of the fourth switch Q4, and a low level of the second control signal S2 is used to maintain the off state of the second switch Q2 and the on state of the fourth switch Q4.
Further, the AC input voltage V AC During the positive half period, the second control signal S2 maintains a high level state, and the first switch Q1 is turned on and off at a high frequency during the period, so that the first inductor L1 is used for the above-mentioned operationThe first direct current output end c provides electric energy;
and the AC input voltage V AC During the negative half period, the fourth control signal S4 maintains a high level state, and the third switching tube Q3 is turned on and off at a high frequency during the period, so as to provide power to the first dc output terminal c through the second inductor L2.
In the power supply starting stage, when the output voltage Vo does not reach the potential of the feedback voltage Vfb (i.e. the preset reference voltage Vref) during starting, a starting circuit arranged in the power supply chip operates until the output voltage Vo reaches the potential of the feedback voltage Vfb, and at this time, the operational amplifier 215 adjusts the output voltage Vo to be reduced, so that the peak current of the main switching tube (Q1 or Q3) is reduced (or the switching frequency is reduced, which is related to the feedback control method selected by the chip), the duty ratio is reduced, and the stability of the output is maintained; when the output voltage Vo is low, the operational amplifier 215 adjusts its output voltage Vo to increase, causing the peak current of the main switch to increase (or increasing the switching frequency, related to the feedback control method selected by the chip), and the duty ratio to increase, thereby maintaining the stability of the output.
Specifically, in the normal operation state of the ac input voltage VAC in this embodiment, when the ac input voltage VAC is in a positive half cycle, the first boost circuit operates, the second boost circuit is turned off completely, that is, the third switching tube Q3 and the fourth switching tube Q4 are both in an off-state, and the second switching tube Q2 is in an on-state all the time, when the first switching tube Q1 is turned on, a current flows from the first ac input end a through the first inductor L1, the first switching tube Q1, the detection resistor Rcs, and the second switching tube Q2, and returns to the second ac input end b, and energy is stored in the first inductor L1, and the first inductor L1, the first switching tube Q1, the detection resistor Rcs, and the second switching tube Q2 form a current energy storage loop, as shown in fig. 8, at this time, through the isolation effect of the first diode D1, the output capacitor Co at the dc side output end supplies power to the load. When the first switch tube Q1 is turned off, the first inductor L1 generates an induced voltage, the energy stored in the first inductor L1 is discharged to the output terminal through the first diode D1, and simultaneously charges the output capacitor Co, and at this time, the first inductor L1, the first diode D1, the output capacitor Co, and the second switch tube Q2 form a current energy release loop, as shown in line1 in fig. 8.
When the ac input voltage VAC is in a negative half cycle, the second boost circuit operates, the first boost circuit is fully turned off, that is, the first switching tube Q1 and the second switching tube Q2 are both in an off-state, and the fourth switching tube Q4 is always in an on-state during this period, when the third switching tube Q3 is turned on, current flows from the first ac input end a through the second inductor L2, the third switching tube Q3, the detection resistor Rcs, and the fourth switching tube Q4 back to the second ac input end b, energy is stored in the second inductor L2, and the second inductor L2, the third switching tube Q3, the detection resistor Rcs, and the fourth switching tube Q4 form a current energy storage loop, as shown in fig. 9a, line3, at this time, through the isolation effect of the second diode D2, the output capacitor Co at the dc side output end supplies power to the load. When the third switch tube Q3 is turned off, the second inductor L2 generates an induced voltage, the energy stored in the second inductor L2 is discharged to the output terminal through the second diode D2, and simultaneously charges the output capacitor Co, and at this time, the second inductor L2, the second diode D2, the output capacitor Co, and the fourth switch tube Q4 form a current energy release loop, as shown in line4 in fig. 9 b.
Two voltage booster circuits according to the input AC input voltage V AC The positive half period and the negative half period work alternately without mutual interference and the working modes are completely the same, thus perfectly solving the problem of inductive current shunt. The input capacitor Cin, the output capacitor Co and the current detection resistor Rcs are shared devices of the two booster circuits, and during the alternate working period of the two booster circuits, continuous current pulses are generated on the input capacitor Cin, the output capacitor Co and the current detection resistor Rcs, which is the same as that of the common booster circuit. Thus, the two boost circuits can operate in Continuous Current Mode (CCM), discontinuous Current Mode (DCM), and critical continuous mode (CRM), respectively.
The switching power factor corrector 200 provided by the embodiment of the disclosure realizes active power factor correction without a rectifier bridge, saves power loss of an alternating current rectifier bridge, improves power factor, reduces pollution of a power supply system to a power grid, and makes contribution to energy and environmental protection.
In another aspect, the present disclosure provides an AC/DC converter that may include the switching power factor corrector 200 as described in the above embodiments.
The AC/DC converter can operate in Continuous Current Mode (CCM), discontinuous Current Mode (DCM), and critical continuous mode (CRM).
For a power supply system (AC/DC converter) applying the switching power factor corrector 200, the efficiency can be effectively improved, favorable conditions are created for high-frequency and high-density power of a power supply, the design difficulty of a control chip is reduced, the integration level of the whole system is improved, the application circuit is simplified, and the difficulty of mass production is reduced.
In summary, the switching power factor corrector 200 and the AC/DC converter provided by the embodiment of the present disclosure, wherein the switching power factor corrector 200 includes a first voltage boost circuit connected between a first AC input terminal a and a first DC output terminal c, and a second voltage boost circuit connected between a second AC input terminal b and the first DC output terminal c, the switching power factor corrector 200 receives an AC input voltage V between the first AC input terminal a and the second AC input terminal b AC A dc output voltage Vo is provided between the first dc output c and ground, at which ac input voltage V AC The first boost circuit is on and the second boost circuit is off during the positive half cycle of (1); at the AC input voltage V AC The second boost circuit operates and the first boost circuit is turned off during the negative half-cycle of (1). The switching power factor corrector 200 provided by the present disclosure utilizes two voltage boosting circuits (a first voltage boosting circuit and a second voltage boosting circuit) according to an alternating input voltage V AC The alternating work of positive and negative half cycles is in order to provide the electric energy to first direct current output end c, mutual noninterference and working method are identical, perfect solution inductive current shunts the problem, has realized the circuit structure of the power factor correction of no rectifier bridge, has saved the power loss of interchange rectifier bridge, has improved power factor, has not only reduced control chip's the design degree of difficulty, has improved the integrated level of whole system moreover, effectively reduces its cost simultaneously.
It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (16)
1. A switching power factor corrector comprising:
the first booster circuit is connected between the first alternating current input end and the first direct current output end; and
a second boost circuit connected between a second AC input terminal and the first DC output terminal,
wherein the switching power factor corrector receives an AC input voltage between the first AC input terminal and the second AC input terminal and provides a DC output voltage between the first DC output terminal and ground,
in a positive half cycle of the AC input voltage, the first boost circuit operates, the second boost circuit turns off,
in the negative half period of the alternating current input voltage, the second boosting circuit works, and the first boosting circuit is turned off.
2. The switching power factor corrector of claim 1, wherein the first boost circuit comprises:
the first inductor and the first diode are connected between the first alternating current input end and the first direct current output end in series, and the second end of the first inductor is connected with the anode of the first diode;
the first switch tube is connected between the second end of the first inductor and the ground, and the second switch tube is connected between the second alternating current input end and the ground.
3. The switching power factor corrector of claim 2, wherein the second boost circuit comprises:
a second inductor and a second diode connected in series between the second ac input terminal and the first dc output terminal, a second end of the second inductor being connected to an anode of the second diode;
the third switch tube is connected between the second end of the second inductor and the ground, and the fourth switch tube is connected between the first alternating current input end and the ground.
4. The switching power factor corrector of claim 3, wherein the first switching transistor is coupled to ground via a first sense resistor, the first sense resistor providing a first inductor current signal through the first inductor when the first boost circuit is operating.
5. The switching power factor corrector of claim 3, wherein the third switching tube is coupled to ground via a second sense resistor, the second sense resistor providing a second inductor current signal through the second inductor when the second boost circuit is in operation.
6. The switching power factor corrector of claim 3, wherein the first switching transistor and the third switching transistor are coupled to ground via a common sense resistor, the sense resistor providing a first inductor current signal through the first inductor when the first boost circuit is in operation and providing a second inductor current signal through the second inductor when the second boost circuit is in operation.
7. The switching power factor corrector of claim 6, further comprising:
an input capacitance connected between the first AC input terminal and the second AC input terminal configured to high frequency filter the AC input voltage;
an output capacitor connected between the first DC output terminal and ground.
8. The switching power factor corrector of claim 7, further comprising:
a control circuit configured to generate a switching control signal according to a detection signal, the first/second inductor current signal and a feedback voltage sampling the dc output voltage, and generate a first control signal, a second control signal, a third control signal and a fourth control signal through processing the switching control signal to be correspondingly and sequentially provided to control terminals of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube,
the detection signal is used for representing the states of positive and negative half cycles of the work of the alternating current input voltage.
9. The switching power factor corrector of claim 8, wherein the control circuit comprises:
the detection unit is coupled to the first alternating current input end and the second alternating current input end and outputs the detection signal;
an output feedback unit configured to sample the direct current output voltage and generate the feedback voltage by voltage division;
the positive input end of the operational amplifier is connected with a preset reference voltage, the negative input end of the operational amplifier is connected with the output feedback unit and is connected with the feedback voltage, and the output end of the operational amplifier provides a first voltage signal;
the non-inverting input end of the first comparator is connected to the first voltage signal, the inverting input end of the first comparator is connected to the ground through the detection resistor to obtain the first/second current sensing signal, and the output end of the first comparator provides a second voltage signal;
a logic control unit configured to generate the switch control signal according to the detection signal and the second voltage signal;
a driver configured to generate the first control signal, the second control signal, the third control signal, and the fourth control signal, respectively, according to processing of the switching control signal.
10. The switching power factor corrector of claim 9, wherein the detection unit includes a first resistor, a second resistor, and a third resistor connected to each other, and a second comparator,
the first end of the first resistor is connected to the second alternating current input end, the second end of the first resistor is connected to the non-inverting input end of the second comparator through the third resistor, the first end of the second resistor is connected to the first alternating current input end, the second end of the second resistor and the second end of the first resistor are connected to the first end of the third resistor together, the inverting input end of the second comparator is grounded, and the output end of the second comparator is used for providing the detection signal.
11. The switching power factor corrector of claim 10, wherein the output feedback unit comprises a fourth resistor, a fifth resistor and a sixth resistor connected in series between the first dc output terminal and ground, and a connection node of the fifth resistor and the sixth resistor is used to provide the feedback voltage.
12. The switching power factor corrector of claim 11, wherein the control circuit further comprises:
a high pass filter including a seventh resistor and a first capacitor connected in series between an output of the operational amplifier and ground.
13. The switching power factor corrector of claim 9, wherein the second control signal and the fourth control signal are a pair of complementary signals, and a high level of the second control signal is used to maintain an on state of the second switching tube and an off state of the fourth switching tube, and a low level of the second control signal is used to maintain an off state of the second switching tube and an on state of the fourth switching tube.
14. The switching power factor corrector of claim 13, wherein the ac input voltage operates in a positive half cycle, the second control signal maintains a high state during which the first switching transistor is turned on and off at a high frequency to provide power to the first dc output terminal through the first inductor;
the alternating current input voltage works in a negative half period, the fourth control signal maintains a high level state, and the third switching tube is switched on and off at high frequency in the period so as to provide electric energy for the first direct current output end through the second inductor.
15. The switching power factor corrector of claim 3, wherein any one of the first switching transistor, the second switching transistor, the third switching transistor and the fourth switching transistor is an N-channel metal oxide semiconductor field effect transistor.
16. An AC/DC switching converter, comprising:
a switching power factor corrector as claimed in any one of claims 1 to 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211150839.4A CN115483823B (en) | 2022-09-21 | 2022-09-21 | Switching power factor corrector and AC/DC converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211150839.4A CN115483823B (en) | 2022-09-21 | 2022-09-21 | Switching power factor corrector and AC/DC converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115483823A true CN115483823A (en) | 2022-12-16 |
| CN115483823B CN115483823B (en) | 2024-01-19 |
Family
ID=84392537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211150839.4A Active CN115483823B (en) | 2022-09-21 | 2022-09-21 | Switching power factor corrector and AC/DC converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115483823B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222746B1 (en) * | 1998-02-09 | 2001-04-24 | Samsung Electronics Co., Ltd. | Power supply device and method with a power factor correction circuit |
| CN2591836Y (en) * | 2002-08-27 | 2003-12-10 | 石家庄国耀电子科技有限公司 | Positive and negative double-voltage output single-phase active power factor correction step-up transformer |
| TW200938988A (en) * | 2008-03-11 | 2009-09-16 | Delta Electronics Inc | Bridgeless PFC for critical conduction mode and controlling method thereof |
| CN101789684A (en) * | 2010-03-05 | 2010-07-28 | 于锁平 | Power factor corrector |
| CN102136792A (en) * | 2011-04-15 | 2011-07-27 | 浙江大学 | Boost double-voltage power factor correction circuit utilizing reverse blocking IGBT |
| CN202059338U (en) * | 2011-05-05 | 2011-11-30 | 天宝电子（惠州）有限公司 | Alternating-current rectifier circuit with PFC (power factor correction) function |
| KR20170064100A (en) * | 2015-11-30 | 2017-06-09 | 서울과학기술대학교 산학협력단 | High Power Factor And High Efficiency Interleaved Dual-Buck Converter And Method Therefor |
| CN107508474A (en) * | 2017-09-07 | 2017-12-22 | 西华大学 | ON time method of adjustment, circuit and SEPIC power factor correcting converters |
| CN108512431A (en) * | 2018-04-24 | 2018-09-07 | 上海推拓科技有限公司 | Double rectification alternating expression full-bridge single stage power factor correction power circuits and control method |
| CN211656002U (en) * | 2020-04-28 | 2020-10-09 | 陕西科技大学 | Resonance bridgeless boost power factor correction AC-DC converter |
| CN114123758A (en) * | 2021-11-29 | 2022-03-01 | 珠海格力电器股份有限公司 | AC-DC converter and control method of AC-DC converter |
-
2022
- 2022-09-21 CN CN202211150839.4A patent/CN115483823B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222746B1 (en) * | 1998-02-09 | 2001-04-24 | Samsung Electronics Co., Ltd. | Power supply device and method with a power factor correction circuit |
| CN2591836Y (en) * | 2002-08-27 | 2003-12-10 | 石家庄国耀电子科技有限公司 | Positive and negative double-voltage output single-phase active power factor correction step-up transformer |
| TW200938988A (en) * | 2008-03-11 | 2009-09-16 | Delta Electronics Inc | Bridgeless PFC for critical conduction mode and controlling method thereof |
| CN101789684A (en) * | 2010-03-05 | 2010-07-28 | 于锁平 | Power factor corrector |
| CN102136792A (en) * | 2011-04-15 | 2011-07-27 | 浙江大学 | Boost double-voltage power factor correction circuit utilizing reverse blocking IGBT |
| CN202059338U (en) * | 2011-05-05 | 2011-11-30 | 天宝电子（惠州）有限公司 | Alternating-current rectifier circuit with PFC (power factor correction) function |
| KR20170064100A (en) * | 2015-11-30 | 2017-06-09 | 서울과학기술대학교 산학협력단 | High Power Factor And High Efficiency Interleaved Dual-Buck Converter And Method Therefor |
| CN107508474A (en) * | 2017-09-07 | 2017-12-22 | 西华大学 | ON time method of adjustment, circuit and SEPIC power factor correcting converters |
| CN108512431A (en) * | 2018-04-24 | 2018-09-07 | 上海推拓科技有限公司 | Double rectification alternating expression full-bridge single stage power factor correction power circuits and control method |
| CN211656002U (en) * | 2020-04-28 | 2020-10-09 | 陕西科技大学 | Resonance bridgeless boost power factor correction AC-DC converter |
| CN114123758A (en) * | 2021-11-29 | 2022-03-01 | 珠海格力电器股份有限公司 | AC-DC converter and control method of AC-DC converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115483823B (en) | 2024-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| De Souza et al. | A new ZVS-PWM unity power factor rectifier with reduced conduction losses | |
| Cheng et al. | A novel single-stage high-power-factor AC/DC converter featuring high circuit efficiency | |
| Pan et al. | Power factor correction using a series active filter | |
| US20100259240A1 (en) | Bridgeless PFC converter | |
| CN113489308B (en) | Step-down power factor correction converter without input current dead zone and control method | |
| CN102801329A (en) | High-efficiency and low-loss AC/DC (Alternating Current/Direct Current) power supply circuit and control method thereof | |
| CN113765359A (en) | Multi-unit parallel connection integrated voltage reduction bridgeless PFC converter | |
| US20230208279A1 (en) | Active diode circuit and ac/dc power conversion circuit | |
| Shen et al. | A novel high-efficiency single-stage PFC converter with reduced voltage stress | |
| CN100377481C (en) | Integration converton with three phase power factor correction | |
| CN210093612U (en) | LED double-color dimming built-in power supply | |
| CN115483823B (en) | Switching power factor corrector and AC/DC converter | |
| KR100420964B1 (en) | Single-stage converter compensating power factor | |
| JP3367539B2 (en) | DC power supply | |
| WO2022179564A1 (en) | Bridgeless voltage-drop power factor correction circuit | |
| Pandhi et al. | An approach for power factor correction of single-phase single-stage three-level AC-DC converter with phase shift modulation | |
| CN111555604A (en) | Novel quasi-single-stage high power factor circuit | |
| Do et al. | Single-stage asymmetrical PWM AC–DC converter with high power factor | |
| CN220359032U (en) | Power factor corrector, power factor correction circuit and power supply equipment | |
| Jimoh et al. | Single-Phase AC-DC PFC Converters for EV Chargers: An Overview | |
| CN221784041U (en) | High-efficient bridgeless PFC circuit | |
| CN215990574U (en) | Mains supply voltage reduction circuit | |
| CN220382954U (en) | Efficient switching power supply circuit | |
| Jumadril et al. | An Improved Two-Switch Bridgeless PFC SEPIC Structure for Total Harmonic Distortion Reduction and Circulating Current Minimization | |
| Sooksatra et al. | Near Unity Power Factor Using Non-inverting Boost-Buck Converter with Programmed PWM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |