CN115486864B

CN115486864B - Assembly structure of silicon-based detector module for CT and dead zone data completion method

Info

Publication number: CN115486864B
Application number: CN202211315899.7A
Authority: CN
Inventors: 任彦
Original assignee: Sinovision Technology Beijing Co ltd
Current assignee: Sinovision Technology Beijing Co ltd
Priority date: 2022-10-26
Filing date: 2022-10-26
Publication date: 2023-04-18
Anticipated expiration: 2042-10-26
Also published as: CN115486864A

Abstract

The application discloses packaging structure and blind spot data completion method for silicon-based detector module for CT, this packaging structure for silicon-based detector module for CT includes: the detector comprises silicon wafers, a plurality of silicon wafers and a plurality of silicon wafers, wherein the silicon wafers are stacked to form a detector module; the adjacent silicon wafers are staggered with each other by two times or more dead zone widths in the direction perpendicular to the outgoing direction of the X-ray. A plurality of silicon chips are stacked in the Z direction, and staggered twice or more than twice of dead zone width along the X direction, X rays are emitted into the detector module along the Y direction, and the Z direction, the X direction and the Y direction are mutually vertical. According to the method and the device, the influence caused by the missing of the dead zone data at the edge of the silicon wafer is reduced, the technical effect of improving the imaging quality is achieved, and the problems that partial data cannot be obtained due to the dead zone of the packaging process of a silicon-based detector in the related technology, the resolution ratio is reduced due to insufficient sampling, and image artifacts are generated are solved.

Description

Assembly structure of silicon-based detector module for CT and dead zone data completion method

Technical Field

The application relates to the technical field of CT equipment, in particular to an assembly structure of a silicon-based detector module for CT and a dead zone data completion method.

Background

CT is a widely used device in both medical and industrial applications. Detectors for CT generally consist of a large number of modules that are closely packed.

If a silicon wafer is used as a detector, a dead zone of a certain width must be left at the edge of the silicon wafer (fig. 1) because of process limitations. Even with close splicing of the wafers, there are two dead zone width regions at the seams (fig. 2). Rays striking the dead zone do not produce valid data, which results in the loss of a portion of the data. If the detector module (fig. 3) is packaged according to a conventional method, in the area with data loss, resolution reduction caused by undersampling can occur, and image artifacts can also occur.

Disclosure of Invention

The main objective of the present application is to provide an assembly structure of a silicon-based detector module for CT and a dead zone data completion method, so as to solve the problems that in the related art, due to the dead zone existing in the packaging process of the silicon-based detector, part of data cannot be obtained, the resolution is reduced due to insufficient sampling, and image artifacts are generated.

In order to achieve the above object, the present application provides an assembly structure of a silicon-based detector module for CT, including: the detector comprises a plurality of silicon chips, a plurality of silicon chips and a plurality of silicon chips, wherein the silicon chips are arranged and stacked to form a detector module; the adjacent silicon wafers are staggered with each other by two times or more dead zone widths in the direction perpendicular to the outgoing direction of the X-ray.

Furthermore, a plurality of silicon wafers are stacked in the Z direction and staggered by two times or more dead zone widths along the X direction, X rays are emitted into the detector module along the Y direction, and the Z direction, the X direction and the Y direction are mutually perpendicular.

Furthermore, the silicon wafers are staggered by two times or more dead zone widths along the X direction row by row.

Further, a plurality of silicon wafers stacked along the Z direction are alternatively staggered along the X direction by two times or more dead zone widths.

Further, a plurality of silicon wafers stacked along the Z direction are periodically staggered along the X direction by two times or more dead zone widths.

According to another aspect of the present application, there is provided a method for completing dead zone data of a silicon-based photon counting detector module for CT, the method comprising:

stacking a plurality of silicon wafers to form a detector module, and mutually staggering the adjacent silicon wafers by two times or more than two times of dead zone width in the direction vertical to the emergent direction of the X-ray;

when the X-ray passes through the silicon wafer, acquiring data of the surrounding area of the dead zone on each silicon wafer;

and completing the data of the dead zone based on the data of the surrounding area.

Further, the surrounding region includes data of a region located in the nearest neighbor and/or a next neighbor of the dead zone on each of the silicon wafers.

Further, completing the data of the dead zone based on the data of the surrounding area, specifically: and supplementing the data of the dead zone by interpolation based on the data of the surrounding area.

Further, the interpolation method is linear interpolation or spline interpolation or bilinear interpolation or laplacian interpolation.

Further, completing the data of the dead zone based on the data of the surrounding area, specifically: completing the data of the dead zone by using a trained neural network model based on the data of the surrounding area;

the neural network model is trained by the following steps:

preparing a plurality of die bodies with different shapes and materials for scanning;

the method comprises the following steps of firstly scanning, marking the position of a detector module as P0, and marking the obtained data as D0;

in the second batch of scanning, the detector module moves in the staggered direction of the silicon wafer by the distance which is the same as the staggered width of the silicon wafer to reach the position P1, and data D01 of the original dead zone position are obtained;

combining the D01 and the D0 to obtain complete data D1;

and repeating the steps to scan the plurality of motifs in sequence, and training the neural network model by using D0 obtained by scanning the plurality of motifs as input and D1 as output.

In the embodiment of the application, a plurality of silicon chips are arranged and stacked to form a detector module; the adjacent silicon wafers are staggered by two times or more than two times of dead zone widths in the direction perpendicular to the X-ray emitting direction, so that the purposes that data can be generated in the surrounding area of the dead zone on the silicon wafers when the X-ray passes through the silicon wafers and the data around the dead zone can be used for completing the dead zone data are achieved, the influence caused by the dead zone data loss at the edges of the silicon wafers is reduced, the imaging quality is improved, and the problems that in the related technology, due to the fact that dead zones exist in the packaging technology, partial data cannot be acquired, the resolution ratio is reduced due to insufficient sampling, and image artifacts are generated are solved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:

FIG. 1 is a schematic structural diagram of a silicon wafer according to an embodiment of the present application;

FIG. 2 is a schematic top view of a silicon wafer according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a conventional silicon wafer assembly according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a silicon wafer assembly according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another structure of a silicon wafer assembly according to the embodiment of the present application;

FIG. 6 is a schematic diagram of another structure for silicon wafer assembly according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another structure for silicon wafer assembly according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another structure for silicon wafer assembly according to an embodiment of the present application;

wherein, 1 silicon chip, 2 dead zone and 3 surrounding area.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used.

In the present application, the terms "upper", "lower", "inner", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used in other meanings besides orientation or positional relationship, for example, the term "upper" may also be used in some cases to indicate a certain attaching or connecting relationship. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "disposed," "provided," "connected," "secured," and the like are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.

In addition, the term "plurality" shall mean two as well as more than two.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

If a silicon wafer is used as a detector, a dead zone of a certain width must be left at the edge of the silicon wafer (fig. 1) because of process limitations. Even with close splicing of the wafers, there are two dead zone width regions at the seams (fig. 2). The rays striking the dead zone do not produce valid data, which results in the loss of a portion of the data. If the detector module (fig. 3) is packaged by a conventional method, in the area where data is lost, resolution reduction caused by undersampling can occur, and image artifacts can also occur.

To solve the above technical problem, as shown in fig. 4 to 8, an embodiment of the present invention provides an assembly structure of a silicon-based detector module for CT, including: the detector comprises a silicon chip 1, wherein a plurality of silicon chips 1 are arranged and stacked to form a detector module; the adjacent silicon chips 1 are staggered with each other by two or more times of the width of the dead zone 2 in the direction perpendicular to the emission direction of the X-ray. A plurality of silicon chips 1 are stacked in the Z direction, and staggered twice or more than twice of the width of the dead zone 2 in the X direction, X rays are emitted into the detector module in the Y direction, and the Z direction, the X direction and the Y direction are mutually vertical.

In the present embodiment, the assembly structure of the silicon wafers 1 constituting the detector module is improved. In the original assembly structure, the silicon wafers 1 are stacked along the Z direction, the edges of the adjacent silicon wafers 1 are flush, and the dead zones 2 of the adjacent silicon wafers 1 are in an overlapping state. When X-rays are incident from the Y direction of the silicon wafer 1, the dead zone 2 at both sides of the silicon wafer 1 cannot generate any data. For this purpose, adjacent silicon wafers 1 are displaced from each other by two or more dead zone 2 widths in a direction perpendicular to the emission direction of the X-rays. When the adjacent silicon wafers 1 are staggered with each other by twice the width of the dead zone 2 in the direction perpendicular to the emission direction of the X-ray, although the dead zone 2 on a single hot silicon wafer 1 still exists objectively and cannot generate data, the peripheral area 3 adjacent to the dead zone 2 on the adjacent silicon wafer 1 can normally generate data, the data of the dead zone 2 can be supplemented through the data of the peripheral area 3, and the supplementing mode can be realized through an interpolation method or a neural network model.

The core point of the silicon wafer 1 assembly in the present application is to make the adjacent silicon wafers 1 mutually staggered by two or more than two times of the width of the dead zone 2 in the X direction, and the purpose of defining the staggered width is to obtain more data of the surrounding area 3 most adjacent to the dead zone 2 when the X-ray is irradiated, so that the data of the surrounding area 3 is more accurate when the data of the dead zone 2 is used for completing. The silicon wafer 1 has a plurality of assembly modes on the premise of meeting the staggered width:

for example, the silicon wafers 1 are staggered twice or more the width of the dead zone 2 in the X direction row by row. As shown in fig. 4, the detector module formed in this way is a parallelogram structure, taking the silicon wafers 1 in four rows in the Z direction and staggered twice the width of the dead zone 2 in the X direction as an example, the peripheral region 3 nearest to the dead zone 2 at the left end of the first row of silicon wafers 1 is the region on the right side of the dead zone 2, the peripheral region 3 nearest to the dead zone 2 at the left end of the second row of silicon wafers 1 is the region on the right side of the dead zone 2, the region on the lower right, the region on the right lower side and the region on the lower left corner, and the same peripheral region 3 nearest to the dead zone 2 at the left ends of the third row of silicon wafers 1 and the fourth row of silicon wafers 1 is the same as that of the second row. The peripheral area 3 nearest to the dead zone 2 at the right end of the first row of silicon wafers 1 is the area at the left side, the upper left corner, the area at the right upper side and the area at the right upper side of the dead zone 2, and similarly, the peripheral area 3 nearest to the dead zone 2 at the right end of the second row and the third row of silicon wafers 1 is the same as that of the first row, and the area nearest to the dead zone 2 at the right end of the fourth row of silicon wafers 1 is the area at the left side of the dead zone 2. In the embodiment, the data of the dead zone 2 is complemented by acquiring the data of the area closest to the dead zone 2, so that the influence caused by the dead zone 2 data missing can be reduced.

In order to further improve the accuracy of data completion of the dead zone 2 at the right end of the silicon wafer 1, in this embodiment, the silicon wafers 1 may be arranged in two rows in the X direction, as shown in fig. 5, the silicon wafers 1 located on the same plane in the two rows of silicon wafers 1 are tightly attached to each other, so that the dead zone 2 at the right end of the first row of silicon wafers 1 and the dead zone 2 at the left end of the second row of silicon wafers 1 can have more nearest surrounding areas 3, and thus the accuracy of data completion of the dead zones 2 at the two ends is improved.

When adjacent silicon wafers 1 are staggered by three times the width of the dead zone 2 in the X direction, as shown in fig. 6, the detector module formed by the assembly is also parallelogram, and the difference from the two times the width of the dead zone 2 is that there are more sub-adjacent surrounding areas 3 in part of the dead zone 2, and the data of the dead zone 2 can be supplemented by more sub-adjacent areas when the supplementation is performed. In the same way, in order to further improve the accuracy of data completion of the dead zone 2 at the right end of the silicon wafer 1, the silicon wafers 1 may be arranged in two rows in the X direction in this embodiment, and the silicon wafers 1 located on the same plane in the two rows of the silicon wafers 1 are tightly attached.

In another assembly, as shown in fig. 7, several silicon wafers 1 stacked in the Z direction are alternately staggered by two or more times the width of the dead zone 2 in the X direction to form a detector module with zigzag edges. Take the silicon wafer 1 as five rows in the Z direction and stagger twice the width of the dead zone 2 in the X direction as an example. The edges of the first row of silicon wafers 1, the third row of silicon wafers 1 and the fifth row of silicon wafers 1 are parallel and level, and the edges of the second row of silicon wafers 1 and the fourth row of silicon wafers 1 are parallel and level and staggered with the adjacent silicon wafers 1 by twice the width of the dead zone 2. The peripheral area 3 nearest to the dead zone 2 at the left end of the first, third and fifth rows of silicon wafers 1 is the area on the right side of the dead zone 2, and the peripheral area 3 nearest to the dead zone 2 at the left end of the second and fourth rows of silicon wafers 1 is the area on the lower left side, the area on the lower right side, the area on the upper left side, the area on the upper right side and the area on the upper right side of the dead zone 2. Similarly, the peripheral region 3 nearest to the dead region 2 at the right end of the five rows of silicon wafers 1 can be determined. In this embodiment, the silicon wafers 1 may be arranged in two rows in the X direction, and the silicon wafers 1 located on the same plane in the two rows of silicon wafers 1 are closely attached to each other, so as to improve the accuracy of data completion of the dead zone 2.

In another assembly mode, as shown in fig. 8, several silicon wafers 1 stacked along the Z direction are periodically staggered by two or more times the width of the dead zone 2 along the X direction to form another detector module with zigzag edges or form a V-shaped detector module, and the silicon wafer 1 in this embodiment still determines the peripheral area 3 most adjacent to the dead zone 2 through the above-mentioned embodiment, and completes the data of the dead zone 2 based on the data of the peripheral area 3.

According to another aspect of the present application, there is provided a dead zone 2 data completion method for a silicon-based photon counting detector module for CT, the method including:

stacking a plurality of silicon wafers 1 to form a detector module, and mutually staggering the adjacent silicon wafers 1 in the direction perpendicular to the emergent direction of the X-ray by two times or more than two times of the width of a dead zone 2;

acquiring data of a surrounding area 3 of a dead zone 2 on each silicon chip 1 when the X-ray passes through the silicon chip 1;

completing the data of the dead zone 2 based on the data of the surrounding area 3; the surrounding region 3 includes data of a region located in the nearest vicinity and/or a next nearest vicinity to the dead region 2 on each silicon wafer 1.

When the compensation is performed, the data of the dead zone 2 can be compensated by interpolation based on the data of the surrounding area 3, or the data of the dead zone 2 can be compensated by a neural network model. The interpolation method is linear interpolation or spline interpolation or bilinear interpolation or Laplace interpolation, and has the main function of estimating target pixel points based on data of adjacent pixel points, so that gaps among the pixels are formed during image transformation. In order to avoid the large-amplitude fluctuation phenomenon which may occur in the high-order interpolation, the approximation degree is usually increased by using the piecewise low-order interpolation in practical application, for example, the piecewise linear interpolation or the piecewise cubic Hermite interpolation can be used for realizing the approximation degree.

When the data of the dead zone 2 is supplemented by the trained neural network model based on the data of the peripheral area 3, a neural network needs to be established and trained to form a neural network model, specifically;

the neural network model is trained by the following steps:

scanning in a second batch, moving the detector module in the staggered direction of the silicon wafer 1 by the distance which is the same as the staggered width of the silicon wafer 1 to reach a position P1, and acquiring data D01 of the original dead zone 2;

combining the D01 and the D0 to obtain complete data D1;

and repeating the steps to scan the plurality of the motifs in sequence, using D0 obtained by scanning the plurality of the motifs as input and D1 as output, training a neural network model, and using the trained neural network model to complement actual scanning data.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An assembly structure of a silicon-based detector module for CT, comprising: the detector comprises silicon wafers, a plurality of silicon wafers and a plurality of silicon wafers, wherein the silicon wafers are stacked to form a detector module; the adjacent silicon wafers are mutually staggered by two times or more than two times of dead zone width in the direction vertical to the emergent direction of the X-ray.

2. The structure of claim 1, wherein a plurality of the silicon wafers are stacked in a Z direction and staggered by two or more dead zone widths in an X direction, and X rays are incident into the detector module in a Y direction, the Z direction, the X direction, and the Y direction being perpendicular to each other.

3. The structure of claim 2, wherein the silicon wafers are staggered two or more times the dead zone width in the X direction row by row.

4. The structure of claim 2, wherein the silicon wafers stacked in the Z direction are alternately staggered by two or more dead zone widths in the X direction.

5. The structure of claim 2, wherein the silicon wafers stacked in the Z direction are periodically staggered by two or more dead zone widths in the X direction.

6. A method for complementing dead zone data of a silicon-based detector module for CT is characterized in that a plurality of silicon wafers are stacked to form the detector module, and the adjacent silicon wafers are mutually staggered by two times or more than two times of dead zone width in the direction perpendicular to the emitting direction of X rays;

7. The method of claim 6, wherein the surrounding region comprises data of a region nearest to the dead region and/or a region next to the dead region on each silicon wafer.

8. The method for completing dead zone data of a silicon-based detector module for CT as claimed in claim 7, wherein the step of completing the dead zone data based on the data of the surrounding area comprises: and completing the data of the dead zone by interpolation based on the data of the surrounding area.

9. The method of claim 8, wherein the interpolation method is linear interpolation or spline interpolation or bilinear interpolation or laplacian interpolation.

10. The method for completing dead zone data of a silicon-based detector module for CT as claimed in claim 6, wherein the step of completing the dead zone data based on the data of the surrounding area comprises: completing the data of the dead zone by using a trained neural network model based on the data of the surrounding area;

the neural network model is trained by the following steps:

in the second batch of scanning, the detector module is moved in the staggered direction of the silicon wafer by the distance which is the same as the staggered width of the silicon wafer to reach a position P1, and data D01 of the original dead zone position is obtained;

combining the D01 and the D0 to obtain complete data D1;