CN115472720B - Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode - Google Patents

Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof, and a light-emitting diode. The light-emitting diode epitaxial wafer includes a substrate, a buffer layer sequentially stacked on the substrate, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, multi-quantum well layer, electron blocking layer, P-type GaN layer; the insertion layer includes Six _{N 1-x} crack layer, Al _1-y Sc _y N pretreatment layer and GaN cap layer, the _Six The N _1‑x crack layer, the Al _1‑y Sc _y N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1‑0.4; the value range of y is 0.1-0.3. The light-emitting diode epitaxial wafer prepared by the invention has lower operating voltage and better antistatic ability.

Description

Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode

technical field

The invention relates to the field of photoelectric technology, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof, and a light-emitting diode.

Background technique

At present, GaN-based light-emitting diodes have been widely used in the fields of solid-state lighting and display, attracting more and more people's attention. GaN-based light-emitting diodes have been industrialized and used in backlights, lighting, and landscape lights.

For LED devices with conventional structures, during the growth of N-type semiconductor layers, the concentration of N-type doping is very high, and the crystalline integrity of GaN materials will decrease with the incorporation of N-type doping, and high N-type doping Miscellaneous can introduce great stress. Moreover, due to the high growth temperature of intrinsic GaN, the stress accumulated from the buffer layer reaches the maximum when growing the N-type GaN layer, resulting in a large warp when growing the N-type doped layer, and the stress accumulation makes the N-type doped Difficulties, especially the edge position of the epitaxial wafer, often lead to uneven N-type doping, which leads to an increase in operating voltage, and is prone to defects such as fogging on the surface of the epitaxial wafer due to large warpage, and the quality of the lattice deteriorates. Affect the antistatic ability of light-emitting diodes.

Contents of the invention

The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer, which can release the underlying stress, increase the flatness of the epitaxial layer, increase the uniformity of N-type doping, thereby reducing the operating voltage and increasing the antistatic properties of the light-emitting diode. ability.

The technical problem to be solved by the present invention is also to provide a method for preparing a light-emitting diode epitaxial wafer, which has a simple process and a high production yield.

In order to solve the above technical problems, the present invention provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, and a multi-quantum well layer sequentially stacked on the substrate. , electron blocking layer, P-type GaN layer;

The insertion layer includes a Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, the Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.

In one embodiment, the thickness of the insertion layer is 50nm-70nm;

Wherein, the thickness of the Six _{N 1-x} crack layer is 10nm-20nm;

The thickness of the Al _1-y Sc _y N pretreatment layer is 20nm-30nm;

The thickness of the GaN cap layer is 20nm-30nm.

In one embodiment, the thickness of the buffer layer is 10nm-100nm;

The thickness of the intrinsic GaN layer is 300nm-800nm;

The thickness of the N-type GaN layer is 1 μm-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of Si is 5×10 ¹⁸ -1×10 ¹⁹ cm ^-3 ;

The thickness of the P-type GaN layer is 10nm-50nm, the P-type GaN layer is doped with Mg, and the doping concentration of Mg is 5×10 ¹⁷ -1×10 ²⁰ cm ^-3 .

In one embodiment, the multi-quantum well layer includes alternately stacked InGaN quantum well layers and GaN quantum barrier layers, and the number of stacking periods is 3-15;

The thickness of the InGaN quantum well layer is 2nm-4nm;

The thickness of the GaN quantum barrier layer is 9nm-11nm.

In one embodiment, the electron blocking layer includes alternately stacked AlGaN layers and InGaN layers, and the number of stacking periods is 3-15;

The thickness of the AlGaN layer is 5nm-7nm;

The thickness of the InGaN layer is 5nm-7nm.

In order to solve the above problems, the present invention also provides a method for preparing a light-emitting diode epitaxial wafer, comprising the following steps:

Prepare the substrate;

sequentially depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate;

The insertion layer includes a Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, the _Six N _1-x crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.

In one embodiment, the deposition of the Si _x N _1-x crack layer is accomplished by the following method:

The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 50Torr-100Torr, and H ₂ /N ₂ is fed as carrier gas, NH ₃ is fed as N source, and SiH ₄ is fed as Si source to complete the deposition.

In one embodiment, the deposition of the Al _1-y S _y N pretreatment layer is accomplished by the following method:

The temperature of the reaction chamber is controlled at 200°C-1000°C, the pressure is 5mTorr-10mTorr, Ar is passed in as the carrier gas, N ₂ is passed in as the reaction gas, and the ScAl alloy target is used as the sputtering target to complete the deposition.

In one embodiment, the deposition of the GaN cap layer is accomplished by the following method:

The temperature of the reaction chamber is controlled at 900°C-1000°C, the pressure is 100Torr-300Torr, and H ₂ /N ₂ is fed as carrier gas, NH ₃ is fed as N source, and TMGa is fed as Ga source to complete the deposition.

In one embodiment, the buffer layer is deposited on the front side of the substrate by the following method:

The temperature of the reaction chamber is controlled at 500°C-700°C, the pressure is 200Torr-400Torr, TMAl is introduced as the Al source, _NH3 is introduced as the N source, and the buffer layer is deposited on the front side of the substrate;

And/or, the following method is used to complete the deposition of the intrinsic GaN layer on the buffer layer:

Control the temperature of the reaction chamber at 1100°C-1150°C, the pressure at 100Torr-500Torr, feed NH ₃ as the N source, and feed TMGa as the Ga source, and complete the deposition of the intrinsic GaN layer on the buffer layer;

And/or, the following method is used to finish depositing the N-type GaN layer on the insertion layer:

The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 100Torr-500Torr, SiH ₄ is introduced as the Si source, NH ₃ is introduced as the N source, and TMGa is introduced as the Ga source to complete the deposition on the insertion layer. The N-type GaN layer;

And/or, the following method is used to finish depositing the P-type GaN layer on the electron blocking layer:

The temperature of the reaction chamber is controlled at 800°C-1000°C, the pressure is 100Torr-300Torr, and NH ₃ is introduced as the N source, TMGa as the Ga source, and CP ₂ Mg as the Mg source, and completed on the electron blocking layer. The P-type GaN layer is deposited.

In one embodiment, the following method is used to complete the deposition of the multiple quantum well layer on the N-type GaN layer:

Alternately depositing InGaN quantum well layers and GaN quantum barrier layers on the N-type GaN layer, the number of stacked layers is 3-15;

Wherein, the deposition step of the InGaN quantum well layer comprises:

Control the temperature of the reaction chamber at 700°C-800°C, the pressure at 100Torr-500Torr, feed TMIn as the In source, _NH3 as the N source, and TMGa as the Ga source to complete the deposition;

The deposition steps of the GaN quantum barrier layer include:

The temperature of the reaction chamber is controlled at 800°C-900°C, the pressure is 100Torr-500Torr, NH ₃ is fed in as the N source, and TMGa is fed in as the Ga source to complete the deposition.

In one embodiment, the following method is used to complete depositing the electron blocking layer on the multiple quantum well layer:

AlGaN layers and InGaN layers are alternately deposited on the multi-quantum well layer, and the number of stacked layers is 3 to 15;

Wherein, the deposition step of the AlGaN layer includes:

The temperature of the reaction chamber is controlled at 900°C-1000°C, the pressure is 100Torr-500Torr, and the deposition is completed by feeding TMAl as the Al source, _NH3 as the N source, and TMGa as the Ga source;

The deposition steps of the InGaN layer include:

Control the temperature of the reaction chamber at 900°C-1000°C, the pressure at 100Torr-500Torr, feed TMIn as the In source, _NH3 as the N source, and TMGa as the Ga source to complete the deposition.

Correspondingly, the present invention also provides a light emitting diode, which includes the light emitting diode epitaxial wafer.

Implement the present invention, have following beneficial effect:

In the light-emitting diode epitaxial wafer provided by the present invention, an insertion layer is added between the intrinsic GaN layer and the N-type semiconductor layer, and before the heavily doped N-type GaN semiconductor grows, the underlying stress is fully released, the flatness of the epitaxial layer is increased, and the Reduce the stress of N-type heavy doping growth, increase the uniformity of N-type doping, and increase the incorporation of N-type doping, successfully reduce the operating voltage, increase the surface flatness of epitaxial wafers, and increase the antistatic of light-emitting diodes ability.

Description of drawings

Fig. 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by the present invention, wherein, the substrate is 1, the buffer layer is 2, the intrinsic GaN layer is 3, the Six _{N 1-x} crack layer 41, Al _1-y Sc _y N pretreatment layer 42 , GaN cap layer 43 , N-type GaN layer is 5 , multi-quantum well layer is 6 , electron blocking layer is 7 , and P-type GaN layer is 8 .

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below.

Unless otherwise stated or contradictory, terms and phrases used herein have the following meanings:

In the present invention, "its combination", "any combination thereof", "any combination thereof" and the like include all suitable combinations of any two or more of the listed items.

In the present invention, "preferred" is only to describe an implementation or an example with better effects, and it should be understood that it does not constitute a limitation to the protection scope of the present invention.

In the present invention, the technical features described in open form include closed technical solutions consisting of the enumerated features, as well as open technical solutions including the enumerated features.

In the present invention, when referring to a numerical interval, unless otherwise specified, both endpoints of the numerical interval are included.

At present, the traditional N-type semiconductor layer has a lot of cumulative stress during growth, large warpage, prone to surface atomization, and poor lattice quality, which affects the antistatic ability of light-emitting diodes. Moreover, due to the large warpage, the N-type doping is uneven, resulting in a high working voltage of the light emitting diode.

In order to solve the above problems, the present invention provides a light emitting diode epitaxial wafer, as shown in FIG. , N-type GaN layer 5, multiple quantum well layer 6, electron blocking layer 7, P-type GaN layer 8;

The insertion layer 4 includes a Six _{N 1-x} crack layer 41, an Al _1-y Sc _y N pretreatment layer 42 and a GaN cap layer 43, and the Six _{N 1-x} crack layer 41, Al _1-y Sc _{The y} N pretreatment layer 42 and the GaN cap layer 43 are sequentially laminated on the intrinsic GaN layer 3 , wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.

In the light-emitting diode epitaxial wafer provided by the present invention, an insertion layer 4 is added between the intrinsic GaN layer 3 and the N-type GaN layer 5, and before the heavily doped N-type GaN semiconductor grows, the underlying stress is fully released and the flatness of the epitaxial layer is increased. degree, reducing the stress of N-type heavy doping growth, increasing the uniformity of N-type doping, and increasing the incorporation of N-type doping, successfully reducing the operating voltage, increasing the surface flatness of the epitaxial wafer, and increasing the light-emitting diode antistatic ability.

It should be noted that the present invention first grows the Si _x N _1-x crack layer on the undoped intrinsic GaN layer. SiN material has high flatness under the condition of high Si doping, low pressure and high temperature growth state, but it is easy to Slight cracks appear, and the slight nano-scale cracks are the release of the accumulated stress in the early stage of the epitaxial layer during the occurrence process. Then grow the Al _1-y Sc _y N pretreatment layer. When the Sc doping is 10-30%, the AlScN material and the GaN material have very good lattice matching, and can exist as a transition layer between SiN and GaN. Further, AlScN grown by PVD method has higher flatness, which can well fill up the fine cracks generated by SiN material. If only the Six _{N 1-x} crack layer is added, the unhealed cracks will make the lattice quality worse, which has the opposite effect. Finally, a GaN cap layer is stacked after the Al _1-y Sc _y N pretreatment layer to prevent Sc atoms from entering the N-type semiconductor layer and affecting N-type doping. Before the growth of the N-type layer, the underlying stress is well released, the warpage is small, and the surface flatness is high, which is conducive to the incorporation and uniform distribution of N-type doping.

In one embodiment, the thickness of the insertion layer is 50nm-70nm; wherein, the thickness of the Six _{N 1-x} crack layer is 10nm-20nm; the Al _1-y Sc _y N pretreatment layer The thickness is 20nm-30nm; the thickness of the GaN cap layer is 20nm-30nm. Preferably, the thickness of the insertion layer is 56nm-64nm; wherein, the thickness of the Six _{N 1-x} crack layer is 12nm-18nm; the thickness of the Al _1-y Sc _y N pretreatment layer is 22nm- 28nm; the thickness of the GaN cap layer is 22nm-28nm.

Specifically, the light emitting diode epitaxial wafer includes the following layered structure. In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. The buffer layer is mainly used to provide crystal seeds, alleviate the lattice mismatch between the substrate and the epitaxial layer, and improve the lattice quality of the epitaxial wafer. In one embodiment, the buffer layer has a thickness of 10 nm-100 nm.

The intrinsic GaN layer is an undoped GaN layer, and in one embodiment, the thickness of the intrinsic GaN layer is 300nm-800nm.

The N-type GaN layer mainly provides electrons. In one embodiment, the thickness of the N-type GaN layer is 1 μm-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of Si is 5 μm. ×10 ¹⁸ -1×10 ¹⁹ cm ^-3 ; the P-type GaN layer mainly provides holes. In one embodiment, the thickness of the P-type GaN layer is 10nm-50nm, and the P-type GaN layer is Mg doping, the Mg doping concentration is 5×10 ¹⁷ -1×10 ²⁰ cm ^-3 .

The multi-quantum well layer is the core structure of the light-emitting diode. In one embodiment, the multi-quantum well layer includes alternately stacked InGaN quantum well layers and GaN quantum barrier layers, and the number of stacking cycles is 3-15; the thickness of the InGaN quantum well layer is 2nm-4nm; the The thickness of the GaN quantum barrier layer is 9nm-11nm.

The electron blocking layer is mainly used to block electrons and prevent electron overflow. In one embodiment, the electron blocking layer includes alternately stacked AlGaN layers and InGaN layers, and the number of stacking cycles is 3-15; the AlGaN layer The thickness of the InGaN layer is 5nm-7nm; the thickness of the InGaN layer is 5nm-7nm.

Correspondingly, the present invention also provides a method for preparing the above-mentioned light-emitting diode epitaxial wafer, comprising the following steps:

S1. Prepare the substrate;

In one embodiment, the substrate is a sapphire substrate. Then, control the temperature of the reaction chamber at 1000°C~1200°C, control the pressure of the reaction chamber at 200 Torr-600Torr, and perform high-temperature annealing on the substrate for 5min-8min in _H2 atmosphere to clean the particles and oxides on the substrate surface .

S2, sequentially depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate;

The insertion layer includes a Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, the Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.

In one embodiment, the step S2 includes the following steps:

S21. Depositing the buffer layer on the front side of the substrate by the following method:

In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer is an AlN buffer layer, and the AlN buffer layer is prepared by the following method: the temperature of the reaction chamber is controlled at 500°C-700°C, the pressure is 200Torr-400Torr, and TMAl is introduced as the Al source. Inject NH ₃ as the N source to complete the deposition of the buffer layer on the front side of the substrate.

S22. Depositing the intrinsic GaN layer on the buffer layer by using the following method:

The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 100Torr-500Torr, NH ₃ is fed in as the N source, and TMGa is fed in as the Ga source to complete the deposition of the intrinsic GaN layer on the buffer layer.

S23. The deposition of the Six _{N 1-x} crack layer is completed by the following method:

The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 50Torr-100Torr, and H ₂ /N ₂ is fed as carrier gas, NH ₃ is fed as N source, and SiH ₄ is fed as Si source to complete the deposition.

It should be noted that in the present invention, a Six _{N 1-x} crack layer is first grown on the intrinsic GaN layer. In the above method, preferably, the pressure is 60 Torr-80 Torr, and the temperature of the reaction chamber is controlled at 1140°C-1150°C , the value range of x is 0.2-0.4. The SiN material has high flatness under the condition of high Si doping, low pressure and high temperature growth, but slight cracks will appear. The process of slight nanoscale cracks is also the release of the accumulated stress in the early stage of the epitaxial layer. The setting of the _Six N _1-x crack layer is conducive to fully releasing the underlying stress before the growth of the heavily doped N-type GaN semiconductor, increasing the flatness of the epitaxial layer, reducing the stress of N-type heavily doped growth, and increasing the N-type doped growth. Mixed uniformity.

However, if only the Six _{N 1-x} crack layer is added, the unhealed cracks will make the lattice quality worse, thus playing the opposite effect. To solve this problem, the present application introduces an Al _1-y Sc _y N pretreatment layer.

S24. Complete the deposition of the Al _1-y Sc _y N pretreatment layer by the following method:

The temperature of the reaction chamber is controlled at 200°C-1000°C, the pressure is 5mTorr-10mTorr, Ar is passed in as the carrier gas, N ₂ is passed in as the reaction gas, and the ScAl alloy target is used as the sputtering target to complete the deposition.

Preferably, the epitaxial wafer is transferred to PVD, that is, the deposition of the Al _1-y Sc _y N pretreatment layer is completed in a magnetron sputtering device. When the Sc doping in the Al _1-y Sc _y N pretreatment layer is 10-30%, the AlScN material and the GaN material have very good lattice matching, and can exist as a transition layer between SiN and GaN, further Therefore, AlScN grown by PVD method has higher flatness, which can well fill up the fine cracks produced by SiN materials.

S25, using the following method to complete the deposition of the GaN cap layer:

The temperature of the reaction chamber is controlled at 900°C-1000°C, the pressure is 100Torr-300Torr, and H ₂ /N ₂ is fed as carrier gas, NH ₃ is fed as N source, and TMGa is fed as Ga source to complete the deposition.

Preferably, the epitaxial wafer is transferred back to the MOCVD equipment to complete the deposition of the GaN cap layer.

The GaN cap layer is stacked after the Al _1-y Sc _y N pretreatment layer, which can prevent Sc atoms from entering the N-type semiconductor layer and affecting the N-type doping. In this way, before the growth of the N-type layer, the stress of the bottom layer is well released, the warpage is small, and the surface flatness is high, which is conducive to the incorporation and uniform distribution of N-type doping.

S26. Depositing the N-type GaN layer on the insertion layer by using the following method:

The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 100Torr-500Torr, SiH ₄ is introduced as the Si source, NH ₃ is introduced as the N source, and TMGa is introduced as the Ga source to complete the deposition on the insertion layer. The N-type GaN layer;

S27. Depositing the multiple quantum well layer on the N-type GaN layer by using the following method:

Alternately depositing InGaN quantum well layers and GaN quantum barrier layers on the N-type GaN layer, the number of stacked layers is 3-15;

Wherein, the deposition step of the InGaN quantum well layer comprises:

Control the temperature of the reaction chamber at 700°C-800°C, the pressure at 100Torr-500Torr, feed TMIn as the In source, _NH3 as the N source, and TMGa as the Ga source to complete the deposition;

The deposition steps of the GaN quantum barrier layer include:

The temperature of the reaction chamber is controlled at 800°C-900°C, the pressure is 100Torr-500Torr, NH ₃ is fed in as the N source, and TMGa is fed in as the Ga source to complete the deposition.

S28. Depositing the electron blocking layer on the multiple quantum well layer by using the following method:

AlGaN layers and InGaN layers are alternately deposited on the multi-quantum well layer, and the number of stacked layers is 3 to 15;

Wherein, the deposition step of the AlGaN layer includes:

The temperature of the reaction chamber is controlled at 900°C-1000°C, the pressure is 100Torr-500Torr, and the deposition is completed by feeding TMAl as the Al source, _NH3 as the N source, and TMGa as the Ga source;

The deposition steps of the InGaN layer include:

Control the temperature of the reaction chamber at 900°C-1000°C, the pressure at 100Torr-500Torr, feed TMIn as the In source, _NH3 as the N source, and TMGa as the Ga source to complete the deposition.

S29. Depositing the P-type GaN layer on the electron blocking layer by the following method:

The temperature of the reaction chamber is controlled at 800°C-1000°C, the pressure is 100Torr-300Torr, and NH ₃ is introduced as the N source, TMGa as the Ga source, and CP ₂ Mg as the Mg source, and completed on the electron blocking layer. The P-type GaN layer is deposited.

Correspondingly, the present invention also provides a light emitting diode, which includes the light emitting diode epitaxial wafer.

Above, MOCVD equipment or PVD equipment is used to complete the deposition process, and the present invention does not limit the deposition method. Moreover, the above Al source, N source, Ga source, Si source, Mg source, Sc source, and In source are exemplary descriptions, and are not limited to the above-mentioned enumerations.

Further illustrate the present invention with specific embodiment below:

Example 1

This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P layer sequentially stacked on the substrate. type GaN layer;

The insertion layer includes a Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, the Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein x is 0.3; y is 0.2.

The method for preparing the above-mentioned light-emitting diode epitaxial wafer includes the following steps:

S1. Prepare a substrate; the substrate is a sapphire substrate.

S2, sequentially depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate;

Specifically, S2 includes the following steps:

S21. Depositing the buffer layer on the front side of the substrate by the following method:

Control the temperature of the reaction chamber at 600°C, feed TMAl as the Al source, feed _NH3 as the N source, deposit a buffer layer on the front side of the substrate, complete the deposition and control the thickness of the deposited buffer layer to be 30nm .

S22. Depositing the intrinsic GaN layer on the buffer layer by using the following method:

Control the temperature of the reaction chamber at 1150°C, feed NH ₃ as the N source, and feed TMGa as the Ga source, complete the deposition and control the deposition thickness to 400nm;

S23. The deposition of the Six _{N 1-x} crack layer is completed by the following method:

The temperature of the reaction chamber is controlled at 1050°C, the pressure is 70 Torr, H ₂ /N ₂ is introduced as the carrier gas, NH ₃ is introduced as the N source, and SiH ₄ is introduced as the Si source to complete the deposition and control the deposited Si The thickness of _{the x} N _1-x crack layer is 15 nm.

S24. Complete the deposition of the Al _1-y Sc _y N pretreatment layer by the following method:

In the PVD equipment, the temperature of the reaction chamber is controlled at 600 ° C, the pressure is 7 mTorr, Ar is introduced as the carrier gas, N ₂ is introduced as the reaction gas, and the ScAl alloy target is used as the sputtering target to complete the deposition and control the deposition. The thickness of the Al _1-y Sc _y N pretreatment layer is 25nm.

S25, using the following method to complete the deposition of the GaN cap layer:

The temperature of the reaction chamber is controlled at 950°C, the pressure is 200 Torr, H ₂ /N ₂ is introduced as the carrier gas, NH ₃ is introduced as the N source, and TMGa is introduced as the Ga source to complete the deposition and control the deposited GaN cap The thickness of the layer is 25 nm.

S26. Depositing the N-type GaN layer on the insertion layer by using the following method:

Control the temperature of the reaction chamber at 1050°C, feed SiH ₄ as the Si source, NH ₃ as the N source, and TMGa as the Ga source, complete the deposition and control the deposition thickness to 2 μm, and the Si doping concentration to 1*10 ¹⁹ cm ^-3 ;

S24. Depositing the multiple quantum well layer on the N-type GaN layer by using the following method:

Alternately depositing InGaN quantum well layers and GaN quantum barrier layers on the N-type GaN layer, the number of stacked layers is 10;

Wherein, the deposition step of the InGaN quantum well layer comprises:

Control the temperature of the reaction chamber at 800°C, feed In source, feed NH ₃ as N source, feed TMGa as Ga source, complete the deposition and control the deposition thickness to 3nm;

The deposition steps of the GaN quantum barrier layer include:

Control the temperature of the reaction chamber at 800°C, feed NH ₃ as the N source, and feed TMGa as the Ga source, complete the deposition and control the deposition thickness to 10nm.

S28. Depositing the electron blocking layer on the multiple quantum well layer by using the following method:

AlGaN layers and InGaN layers are alternately deposited on the multi-quantum well layer, and the number of stacked layers is 8;

Wherein, the deposition step of the AlGaN layer includes:

Control the temperature of the reaction chamber at 950°C and the pressure at 300 Torr, feed TMAl as the Al source, feed NH ₃ as the N source, feed TMGa as the Ga source, complete the deposition and control the deposition thickness to 6nm;

The deposition steps of the InGaN layer include:

The temperature of the reaction chamber is controlled at 950°C, the pressure is 300 Torr, TMIn is introduced as the In source, NH ₃ is introduced as the N source, and TMGa is introduced as the Ga source, and the deposition thickness is controlled to be 6nm.

S29. Depositing the P-type GaN layer on the electron blocking layer by the following method:

Control the temperature of the reaction chamber at 850°C, feed Mg source as the dopant source, feed NH ₃ as the N source, feed TMGa as the Ga source, complete the deposition and control the deposition thickness to 4nm, and the Mg doping concentration to 5*10 ¹⁹ cm ^-3 .

Example 2

This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P layer sequentially stacked on the substrate. type GaN layer;

The insertion layer includes a Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, the Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein x is 0.4; y is 0.1.

For the preparation method of the above-mentioned light-emitting diode epitaxial wafer, refer to Example 1.

Example 3

This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P layer sequentially stacked on the substrate. Type GaN layer;

The insertion layer includes a Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, the Six _{N 1-x} crack layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein x is 0.1; y is 0.3.

For the preparation method of the above-mentioned light-emitting diode epitaxial wafer, refer to Example 1.

Comparative example 1

This comparative example provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, a Si _x N _1-x crack layer, an N-type GaN layer, and a multi-quantum well layer sequentially stacked on the substrate. , an electron blocking layer, and a P-type GaN layer, wherein x is 0.3; y is 0.2.

For the preparation method of the above-mentioned light-emitting diode epitaxial wafer, refer to Example 1.

Comparative example 2

This comparative example provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate. .

For the preparation method of the above-mentioned light-emitting diode epitaxial wafer, refer to Example 1.

The light-emitting diode epitaxial wafers prepared in Examples 1-3 and Comparative Examples 1-2 were used to make chips for performance testing, and the test results are shown in Table 1.

Table 1 shows the performance test results of light-emitting diode epitaxial wafers prepared in Examples 1-3 and Comparative Examples 1-2

From the above results, it can be known that the light-emitting diode epitaxial wafer proposed by the present invention has a specific insertion layer structure, which makes the epitaxial wafer have higher flatness, lower working voltage, and better antistatic ability. If only the SiN crack layer is added, the unhealed cracks will make the lattice quality worse, which has the opposite effect.

The above is the preferred embodiment of the invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also considered as protection scope of the present invention.

Claims (10)

1. A light-emitting diode epitaxial wafer, characterized in that, comprises a substrate and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, and an electron blocking layer stacked sequentially on the substrate , P-type GaN layer; The insertion layer includes a Six _{N 1-x} cracked layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, and the Six _{N 1-x} cracked layer, an Al _{1- y} Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer from bottom to top, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3. 2. The light-emitting diode epitaxial wafer according to claim 1, wherein the thickness of the insertion layer is 50nm-70nm; Wherein, the thickness of the Six _{N 1-x} crack layer is 10nm-20nm; The thickness of the Al _1-y Sc _y N pretreatment layer is 20nm-30nm; The thickness of the GaN cap layer is 20nm-30nm. 3. The light-emitting diode epitaxial wafer according to claim 1, wherein the thickness of the buffer layer is 10nm-100nm; The thickness of the intrinsic GaN layer is 300nm-800nm; The thickness of the N-type GaN layer is 1 μm-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of Si is 5×10 ¹⁸ -1×10 ¹⁹ cm ^-3 ; The thickness of the P-type GaN layer is 10nm-50nm, the P-type GaN layer is doped with Mg, and the doping concentration of Mg is 5×10 ¹⁷ -1×10 ²⁰ cm ^-3 . 4. The light-emitting diode epitaxial wafer according to claim 1, wherein the multi-quantum well layer comprises alternately stacked InGaN quantum well layers and GaN quantum barrier layers, and the number of stacking cycles is 3-15; The thickness of the InGaN quantum well layer is 2nm-4nm; The thickness of the GaN quantum barrier layer is 9nm-11nm. 5. The light-emitting diode epitaxial wafer according to claim 1, wherein the electron blocking layer comprises alternately stacked AlGaN layers and InGaN layers, and the number of stacking cycles is 3-15; The thickness of the AlGaN layer is 5nm-7nm; The thickness of the InGaN layer is 5nm-7nm. 6. A method for preparing a light-emitting diode epitaxial wafer according to any one of claims 1 to 5, comprising the following steps: Prepare the substrate; sequentially depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate; The insertion layer includes a Six _{N 1-x} cracked layer, an Al _1-y Sc _y N pretreatment layer and a GaN cap layer, and the Six _{N 1-x} cracked layer, an Al _{1- y} Sc _y N pretreatment layer and a GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3. 7. The preparation method of light-emitting diode epitaxial wafer as claimed in claim 6, is characterized in that, adopts following method to finish the deposition of described Six _{N 1-x} crack layer: The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 50Torr-100Torr, and H ₂ /N ₂ is fed as carrier gas, NH ₃ is fed as N source, and SiH ₄ is fed as Si source to complete the deposition. 8. The preparation method of light-emitting diode epitaxial wafer as claimed in claim 6, is characterized in that, adopts following method to finish the deposition of described Al _1-y Sc _y N pretreatment layer: The temperature of the reaction chamber is controlled at 200°C-1000°C, the pressure is 5mTorr-10mTorr, Ar is passed in as the carrier gas, N ₂ is passed in as the reaction gas, and the ScAl alloy target is used as the sputtering target to complete the deposition. 9. The preparation method of light-emitting diode epitaxial wafer as claimed in claim 6, is characterized in that, adopts following method to finish the deposition of described GaN cap layer: The temperature of the reaction chamber is controlled at 900°C-1000°C, the pressure is 100Torr-300Torr, and H ₂ /N ₂ is fed as carrier gas, NH ₃ is fed as N source, and TMGa is fed as Ga source to complete the deposition. 10. A light emitting diode, characterized in that the light emitting diode comprises the light emitting diode epitaxial wafer according to any one of claims 1-5.

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