CN115454906A

CN115454906A - Data communication system, method, device and readable storage medium

Info

Publication number: CN115454906A
Application number: CN202211071480.1A
Authority: CN
Inventors: 葛志华; 王海波
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-09-02
Filing date: 2022-09-02
Publication date: 2022-12-09

Abstract

The application discloses a data communication system, a data communication method, a data communication device and a readable storage medium, and relates to the field of electronic information. The data communication system provided by the application comprises: the BMC, the PCH, the SMBus Slave and the CPLD read the communication signals of the BMC and the PCH through the CPLD, so that the SMBus Slave is controlled in a switching mode, and the condition that the whole board is stopped due to abnormal faults of the BMC is guaranteed. Compared with the prior scheme, the data communication system provided by the application utilizes the CPLD to detect and analyze the communication data between the PCH and the BMC, and judges whether the BMC is abnormal according to the communication signals between the BMC and the PCH so as to switch the control of the SMBusslavle, so that the stability of the function of the machine is ensured, and the usability of the machine is enhanced.

Description

Data communication system, method, device and readable storage medium

Technical Field

The present application relates to the field of electronic information, and in particular, to a data communication system, method, apparatus, and readable storage medium.

Background

In recent years, with the progress of information technology, information computers are increasingly applied in daily life and industrial production, and in order to maintain and manage the equipment under a server operating system, it is necessary to acquire data such as the temperature of each board, the power supply voltage value, an alarm thereof, asset information, and the like in the current equipment, and to execute operations such as controlling fans, updating boards, and the like.

In the existing scheme, a temperature sensor, a power supply chip, an asset information storage chip, a fan board and the like on a board card are all mounted on a Baseboard Management Controller (BMC) through a System Management Bus (SMBus), a command for acquiring related information is obtained under a server operating System, a PCH sends to the BMC through a Channel in an Enhanced Peripheral Interface (ESPI) ESPI Bus, the BMC converts the command into a corresponding SMBus operation, and after a corresponding read-write operation is completed, the command is returned to a Paging Channel (PCH) through the ESPI Bus.

In view of the above-mentioned technologies, a need exists for a data communication system with higher stability.

Disclosure of Invention

The application aims to provide a data communication system, a data communication method, a data communication device and a readable storage medium, so that the problem that the usability and the stability of a machine are affected because a command for acquiring related information under a current server operating system is sent to a BMC by a PCH through an OOB channel in an ESPI bus, the BMC is converted into corresponding SMBus operation, the corresponding read-write operation is completed, the command is returned to the PCH through the ESPI bus, and if the BMC is hung up abnormally, the maintenance and management action on the machine under the operating system cannot be responded is solved.

In order to solve the above technical problem, the present application provides a data communication system, including: BMC, PCH, SMBus Slave, CPLD:

the BMC is connected with the PCH and is used for carrying out data communication with the PCH;

the CPLD comprises an SMBus Master and an SMBus Switch, wherein the SMBus Switch is used for controlling the BMC to be communicated with the SMBus Slave when the BMC works normally, and controlling the SMBus Master to be communicated with the SMBus Slave when the BMC is abnormal;

and the SMBus Master is connected with the PCH and is used for carrying out data communication with the PCH when the BMC fails.

Preferably, the BMC communicates with the PCH, the CPLD communicates with the PCH through an eSPI bus, and the CPLD communicates with the SMBus Slave, and the CPLD communicates with the BMC through an SMBus bus.

Preferably, the CPLD further includes a bypass, and the bypass is used for communicating the BMC and the SMBus Switch, and determining whether the BMC is abnormal according to a WDT signal of the BMC.

In order to solve the above problem, the present application provides a data communication method, which is applied to a data communication system including: a data communication system of BMC, PCH, SMBus Slave, CPLD, wherein said BMC is connected to said PCH, said CPLD includes SMBus Master, SMBus Switch, said SMBus Master is connected to said PCH, said method comprising:

controlling the SMBus Switch to acquire communication information between the PCH and the BMC;

judging whether the BMC is abnormal or not according to the communication information;

if yes, controlling the SMBus switch to switch the BMC to the SMBus Master;

and controlling the SMBus Master to communicate with the PCH, and performing read-write operation on the SMBus Slave according to the information sent by the PCH.

Preferably, the CPLD further includes a bypass, and the determining whether the BMC is abnormal according to the communication information includes:

and detecting whether the WDT signal of the BMC is overturned through the bypass, if the WDT signal is overturned, representing that the BMC is not abnormal, and if the WDT signal is not overturned, representing that the BMC is abnormal.

Preferably, after the controlling the SMBus switch to switch the BMC to the SMBus Master, the method further includes:

judging whether the data in the buffer area of the CPLD is valid or not;

if yes, controlling the SMBus Master and the PCH to communicate according to the data of the buffer area;

if not, taking over and executing the information sent by the PCH, and performing read-write operation on the SMBus Slave.

Preferably, the controlling the SMBus Master to communicate with the PCH and performing read-write operation on the SMBus Slave according to the information sent by the PCH includes:

receiving a preset address of the SMBus Slave sent by the PCH and the length of the communication data;

confirming a communication instruction of the PCH according to the length of the communication data;

if the command is a read command, reading the SMBus slave according to the preset address, and sending a read result to the PCH;

and if the communication data is a write instruction, writing the write data in the communication data into the corresponding SMBus Slave according to the preset address of the SMBus Slave.

In order to solve the above problem, the present application provides a data communication apparatus, including: BMC, PCH, SMBus Slave, CPLD's data communication system, wherein, BMC is connected with the PCH, CPLD includes SMBus Master, SMBus Switch, SMBus Master with the PCH is connected, the device includes:

the acquisition module is used for controlling the SMBus Switch to acquire the communication information between the PCH and the BMC;

the judging module is used for judging whether the BMC is abnormal or not according to the communication information, and if so, the BMC enters the switching module;

the switching module is used for controlling the SMBus switch to switch the BMC to the SMBus Master;

and the communication module is used for controlling the SMBus Master to communicate with the PCH and carrying out read-write operation on the SMBus Slave according to the information sent by the PCH.

Preferably, the apparatus further comprises:

the buffer module is used for judging whether the data in the buffer area of the CPLD is valid or not;

To solve the above problem, the present application also provides a data communication apparatus, including a memory for storing a computer program;

a processor for implementing the steps of the data communication method as described above when executing said computer program.

To solve the above problem, the present application further provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and the computer program, when executed by a processor, implements the steps of the data communication method as described above.

The data communication system provided by the application comprises: the system comprises a BMC, a PCH, an SMBus Slave, a CPLD and a controller, wherein the CPLD comprises an SMBus Master, an SMBus Switch and an SMBus Switch, the SMBus Switch is used for controlling the BMC to be communicated with the SMBus Slave when the BMC works normally, and when the BMC is abnormal, the SMBus Master and the SMBus Slave are controlled to be communicated, so that the whole board can be prevented from being shut down due to abnormal faults of the BMC. Compared with the prior art, the data communication system of the application utilizes the CPLD to detect and analyze the communication data between the PCH and the BMC, and judges whether the BMC is abnormal according to the communication signals between the BMC and the PCH so as to switch the control of the SMBus slave, so that the maintenance and management actions of the system on the machine are not interrupted, the influence of the abnormal BMC is avoided, the function stability of the machine is ensured, and the usability of the machine is enhanced.

The data communication method, the data communication device and the computer-readable storage medium provided by the application correspond to the data communication method, and have the advantages.

Drawings

In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.

Fig. 1 is a block diagram of a data communication system according to an embodiment of the present application;

fig. 2 is a flowchart of a data communication method according to an embodiment of the present application;

fig. 3 is a schematic diagram of a data communication device according to an embodiment of the present application;

fig. 4 is a schematic diagram of a data communication device according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.

The core of the application is to provide a data communication system, method, device and readable storage medium, so as to solve the problem that the usability and stability of a machine are affected because a command for acquiring relevant information under the current server operating system is sent to a BMC by a PCH through an OOB channel in an ESPI bus, the BMC is converted into a corresponding SMBus operation, and the corresponding read-write operation is completed and then returned to the PCH through the ESPI bus.

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.

Fig. 1 is a structural diagram of a data communication system according to an embodiment of the present application, including: BMC1, PCH2, SMBus Slave3, CPLD4:

the BMC1 is connected with the PCH2 and is used for carrying out data communication with the PCH 2;

the CPLD4 comprises an SMBus Master and an SMBus Switch, wherein the SMBus Switch is used for controlling the communication between the BMC1 and the SMBus Slave3 when the BMC1 works normally, and controlling the communication between the SMBus Master and the SMBus Slave3 when the BMC1 works abnormally;

the SMBus Master is connected with the PCH2 and is used for carrying out data communication with the PCH2 when the BMC1 fails.

It should be noted that the SMBus provides a control bus for such tasks as system and power management, and the system using the SMBus can save the pin count of the devices by sending and receiving messages between the devices through the SMBus instead of using a separate control line. Using the SMBus, the device may also provide its production information, tell the system its model, part number, etc., save its status for a pending event, report a different class of errors, receive control parameters, and return its status, etc. SMBus devices exist at the first 3 layers of the existing 7-layer OSI network model, namely the physical layer, the data link layer, and the network layer. SMBus is also used to connect various devices including power-related devices, system sensors, EEPROM communication devices, and the like. In this embodiment, the type of SMBus is not particularly limited, and may be different depending on the specific situation.

The SPI is an abbreviation of a Serial Peripheral Interface (Serial Peripheral Interface), is a high-speed, full-duplex, synchronous communication bus, and occupies only four lines on the pins of the chip, saving the pins of the chip, and providing convenience for the layout of the PCB.

PCH2 is an abbreviation of Paging Indicator CHannel, which is translated into a Paging CHannel. The memory controller and PCIe controller in the north bridge are integrated into the CPU, which is equivalent to the whole north bridge chip integrated into the CPU, and only the south bridge is left on the mainboard, therefore, PCH2 can be understood as the south bridge, some SOCs of Intel are integrated into the CPU together with PCH2, and the paging channel is a downlink transmission channel for transmitting data related to the paging process and is used for initializing the network and the terminal. One of the simplest examples is to initiate a voice call to the terminal and the network will send a paging message to the terminal using the paging channel of the cell in which the terminal is located. Different PCH2 channels can be used for paging different paging groups, the number of combined channel paging groups is reduced, the number of non-combined channels is increased, and the more paging groups, the longer waiting time is needed for a user.

The baseboard management controller is used to provide intelligent features in the IPMI architecture. It is a dedicated microcontroller embedded on the motherboard of a computer (usually a server). BMC1 is responsible for managing the interface between system management software and platform hardware. The BMC1 is an independent processor embedded in a server motherboard, and communicates with other software and hardware components inside the host through various interfaces such as IPMB, LPC (low-pin-count-interface), SMBus, and the like, and provides query and control functions to the local host/remote server through interfaces such as network, serial/modem, PCI, and the like. In this embodiment, the specific structure type and the like of the BMC1 are not particularly limited.

It should be noted that in this scheme, switching of the control modes is realized through the SMBus Switch, the read-write control of the SMBus Slave3 by the BMC1 is switched to the read-write control of the SMBus Slave3 by the CPLD4, and the core is to determine whether the BMC1 fails, and in this embodiment, the method for determining the BMC1 failure is not specifically limited.

The data communication system provided by the application comprises: BMC1, PCH2, SMBus Slave3, CPLD4, CPLD4 includes SMBus Master, SMBus Switch is used for when BMC1 normally works, controls BMC1 and SMBus Slave3 intercommunication, when BMC1 is unusual, controls SMBus Master and SMBus Slave3 intercommunication to the assurance can not lead to the whole board to shut down because BMC 1's abnormal fault. Compared with the prior art, the data communication system of the application utilizes the CPLD4 to detect and analyze the communication data seen by the PCH2 and the BMC1, judges whether the BMC1 is abnormal according to the communication signals of the BMC1 and the PCH2 so as to switch the control of SMBus slave, ensures that the maintenance and management actions of the system on the machine are not interrupted, is not influenced by the abnormality of the BMC1, ensures the stability of the machine function and enhances the usability of the machine.

In the above embodiments, the specific communication method is not limited, and a preferable scheme is provided here, where BMC1 communicates with PCH2, CPLD4 communicates with PCH2 through an eSPI bus, and CPLD4 communicates with SMBus Slave3, CPLD4 communicates with BMC1 through an SMBus bus.

It should be noted that the above communication method is adopted to improve the efficiency of signal transmission.

In the above embodiment, how to determine whether BMC1 is abnormal is not limited, and a preferable scheme is provided herein, where the CPLD4 further includes a bypass, and the bypass is used to communicate between BMC1 and SMBus Switch, and determine whether BMC1 is abnormal according to a WDT signal of BMC 1.

What needs to be explained is that the bypass is a bypass on a UPS, a bypass in an anti-theft alarm system, a bypass in a chemical process, a bypass in electrician and electronics, and a bypass in a security alarm system. The bypass is different from the main loop, and means that the bypass can be switched to another loop when the function is needed, so that the normal operation of the load is not influenced. The bypass concept is applied to actual systems, such as bypass buses, bypass switches and the like. The Watchdog (Watchdog Timer, WDT) is a Timer circuit, generally has an input called feeding dog and an output to RST end of MCU, when MCU normally works, it outputs a signal to feeding dog end at intervals to zero the WDT, if the time is over the set time, then it will give a reset signal to MCU to reset MCU to prevent MCU from dead halt, so that Watchdog can prevent program from dead-cycling or program from running off, so that it can easily obtain abnormal state of BMC1 based on WDT.

Fig. 2 is a flowchart of a data communication method according to an embodiment of the present application, and as shown in fig. 2, the method includes:

the application provides a data communication method, which is applied to the following steps: BMC, PCH, SMBus Slave, CPLD's data communication system, wherein, BMC is connected with PCH, and CPLD includes SMBus Master, SMBus Switch, and SMBus Master is connected with PCH, and the method includes:

s10: controlling the SMBus Switch to acquire communication information between the PCH and the BMC;

s11: judging whether the BMC is abnormal or not according to the communication information, and if so, entering S12;

s12: controlling the SMBus switch to switch the BMC to the SMBus Master;

s13: and controlling the SMBus Master to communicate with the PCH, and performing read-write operation on the SMBus Slave according to information sent by the PCH.

It should be noted that in this embodiment, switching of control modes is realized through the SMBus Switch, read-write control over the SMBus Slave by the BMC is switched to read-write control over the SMBus Slave by the CPLD, and the core lies in determining whether the BMC fails.

Since the method provided by the present application corresponds to the system described above, the detailed description of the specific embodiment is given in the above system section, which is not repeated herein.

The data communication method provided by the application is applied to the following steps: the system comprises a BMC, a PCH, an SMBus Slave and a CPLD, wherein the CPLD comprises an SMBus Master and an SMBus Switch, the SMBus Switch is used for controlling the BMC to be communicated with the SMBus Slave when the BMC works normally, and when the BMC is abnormal, the SMBus Master and the SMBus Slave are controlled to be communicated, so that the whole board can not be shut down due to abnormal faults of the BMC. Compared with the prior art, the data communication system of the application utilizes the CPLD to detect and analyze the communication data between the PCH and the BMC, and judges whether the BMC is abnormal according to the communication signals between the BMC and the PCH so as to switch the control of the SMBus slave, so that the maintenance and management actions of the system on the machine are not interrupted, the influence of the abnormal BMC is avoided, the function stability of the machine is ensured, and the usability of the machine is enhanced.

In the above embodiment, how to determine whether the BMC is abnormal is not limited, and a preferred scheme is provided herein, where the CPLD further includes a bypass, and determining whether the BMC is abnormal according to the communication information includes:

and detecting whether the WDT signal of the BMC is overturned or not through a bypass, if the WDT signal is overturned, representing that the BMC is not abnormal, and if the WDT signal is not overturned, representing that the BMC is abnormal.

It should be noted that, if the WDT signal is normally inverted, it means that the BMC normally performs the timing operation, and therefore, when the WDT signal is normally inverted, it means that the BMC normally operates, and therefore, the detection is simple, and the acquisition result is obtained

After controlling the SMBus switch to switch the BMC to the SMBus Master, the method further comprises the following steps:

judging whether the data in the buffer area of the CPLD is effective or not;

It should be noted that the buffer is a memory for temporarily storing the output or input data. The data in the buffer is placed in the buffer from a storage device (e.g., a hard disk) and is to be sent to a CPU or other computing device. Buffer this Chinese translation meaning comes from the fact that when a high-speed component of a computer communicates with a low-speed component, the output of the high-speed component must be buffered somewhere to ensure that the high-speed component matches the low-speed component.

In summary, a preferred scheme is provided herein, when the CPLD detects that the WDT signal of the BMC normally flips, the BMC is considered to normally operate, and the internal SMBus switch is controlled to switch to the Bypass part, that is, the CPLD directly passthrough the SMBus operation of the BMC to the subsequent SMBus slave. At this time, the CPLD is transparent to the entire system and does not affect the existing functions.

When the CPLD detects that the WDT signal of the BMC is not turned over, the BMC is considered to be hung, and the internal SMBus switch is controlled to switch the SMBus Master inside the CPLD.

And if the BMC is abnormal and the data in the Massge Buffer is effective, controlling the SMBus Master to read and write the following SMBus slave according to the data in the Massge Buffer, and returning a corresponding result to the PCH to ensure that the eSPI exchange is not interrupted.

And if the BMC is abnormal and the data in the Massge Buffer is empty, the CPLD takes over and executes the subsequent OOB channel operation on the eSIP bus.

The CPLD modifies OOB _ FREE and OOB _ AVAIL zone bits in an internal eSPI slave state register according to the current actual state:

if SMBus read-write operation exists currently, removing OOB _ FREE; otherwise set OOB _ FREE.

And if the current SMBus data reading is completed, setting the OOB _ AVAIL.

Under the server operating system, in order to perform maintenance management on the machine and access the SMBus slave device in the machine, the PCH should check whether the OOB _ FREE flag bit in the current STATUS register is valid through a GET _ STATUS command.

If the OOB _ FREE zone bit is valid, if the SMBus Slave is read, the address of the SMBus Slave and the length of data are issued through a PUT _ OOB command in the OOB channel. After the CPLD analyzes the PUT _ OOB command and detects data length data, if no other game data exists, the SMBus slave is judged to be read; and controlling the SMBus Master to read the SMBus slave data and clearing the OOB _ FREE mark at the same time.

After reading is finished, setting the OOB _ AVAIL, triggering an alert signal to the PCH, enabling the PCH to receive the alert signal and use a GET _ STATUS command, and after the OOB _ AVAIL setting is detected, using the GET _ OOB command to acquire data; and after the CPLD analyzes the GET _ OOB command, returning the read SMBus slave data to the PCH.

If the OOB _ FREE zone bit is valid, if the SMBus Slave is written, the address of the SMBus Slave is issued, the length of the written data and the written specific data are written through a PUT _ OOB command in the OOB channel. And after the CPLD resolves the PUT _ OOB command, controlling the SMBus Master to write the SMBus slave and clearing the OOB _ FREE mark. And setting the OOB _ FREE after the writing is finished.

In the above embodiments, the data communication method is described in detail, and the present application also provides embodiments corresponding to the data communication apparatus. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.

Fig. 3 is a schematic diagram of a data communication apparatus according to an embodiment of the present application, which is applied to a data communication apparatus including: as shown in fig. 3, the data communication system of BMC, PCH, SMBus Slave, CPLD includes:

an obtaining module 10, configured to control an SMBus Switch to obtain communication information between the PCH and the BMC;

the judging module 11 is used for judging whether the BMC is abnormal according to the communication information, and if so, entering the switching module;

a switching module 12, configured to control the SMBus switch to switch the BMC to the SMBus Master;

and the communication module 13 is used for controlling the SMBus Master to communicate with the PCH and performing read-write operation on the SMBus Slave according to information sent by the PCH.

Since the embodiment of the apparatus portion and the embodiment of the method portion correspond to each other, please refer to the description of the embodiment of the method portion for the embodiment of the apparatus portion and the corresponding beneficial effects, which is not repeated herein.

The data communication device provided by the application is applied to the data communication device comprising: BMC, PCH, SMBus Slave, CPLD's data communication system, CPLD include SMBus Master, SMBus Switch is used for when BMC normally works, controls BMC and SMBus Slave intercommunication, when BMC is unusual, controls SMBus Master and SMBus Slave intercommunication to guarantee can not lead to the whole board to shut down because BMC's abnormal fault. Compared with the prior art, the data communication system of the application utilizes the CPLD to detect and analyze the communication data between the PCH and the BMC, and judges whether the BMC is abnormal according to the communication signals between the BMC and the PCH so as to switch the control of the SMBus slave, so that the maintenance and management actions of the system on the machine are not interrupted, the influence of the abnormal BMC is avoided, the function stability of the machine is ensured, and the usability of the machine is enhanced.

Fig. 4 is a schematic diagram of a data communication device according to another embodiment of the present application, and as shown in fig. 4, the data communication device includes: a memory 20 for storing a computer program;

a processor 21 for implementing the steps of the data communication method as mentioned in the above embodiments when executing the computer program.

The data communication device provided by the embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.

The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The Processor 21 may be implemented in at least one hardware form of Digital Signal Processor (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computing operations related to machine learning.

The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, wherein after being loaded and executed by the processor 21, the computer program can implement the relevant steps of the data communication method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among other things, windows, unix, linux, etc. Data 203 may include, but is not limited to, data involved in data communication methods, and the like.

In some embodiments, the data communication device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

Those skilled in the art will appreciate that the configuration shown in fig. 4 is not limiting to data communication devices and may include more or fewer components than those shown.

The data communication device provided by the embodiment of the application comprises a memory and a processor, and when the processor executes a program stored in the memory, the following method can be realized: the data communication method referred to in the above embodiments.

The data communication device provided by the application is applied to the data communication device comprising: BMC, PCH, SMBus Slave, CPLD's data communication system, CPLD include SMBus Master, SMBus Switch is used for when BMC normally works, controls BMC and SMBus Slave intercommunication, when BMC is unusual, controls SMBus Master and SMBus Slave intercommunication to guarantee can not lead to the whole board to shut down because BMC's abnormal fault. Compared with the prior scheme, the data communication system provided by the application detects and analyzes the communication data between the PCH and the BMC by using the CPLD, and judges whether the BMC is abnormal according to the communication signals between the BMC and the PCH so as to switch the control of the SMBus slave, so that the maintenance and management actions of the system on the machine are not interrupted, the influence of the abnormal BMC is avoided, the function stability of the machine is ensured, and the usability of the machine is enhanced.

Since the embodiment of the apparatus portion and the embodiment of the method portion correspond to each other, reference is made to the description of the embodiment of the method portion for the embodiment of the apparatus portion and the corresponding advantageous effects, which are not repeated herein.

Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.

It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be substantially or partially implemented in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods of the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Since the embodiment of the readable storage medium portion and the embodiment of the method portion correspond to each other, please refer to the description of the embodiment of the method portion for the embodiment of the apparatus portion and the corresponding beneficial effects, which are not repeated herein.

A data communication system, a method, an apparatus and a computer readable storage medium provided by the present application are described above in detail. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A data communication system, comprising: BMC, PCH, SMBus Slave, CPLD:

the SMBus Master is connected with the PCH and is used for carrying out data communication with the PCH when the BMC fails.

2. The data communication system of claim 1, wherein the BMC communicates with the PCH, the CPLD communicates with the PCH over an eSPI bus, and the CPLD communicates with the SMBus Slave, the CPLD communicates with the BMC over an SMBus bus.

3. The data communication system of claim 2, wherein the CPLD further comprises a bypass, the bypass is configured to communicate the BMC with the SMBus Switch, and determine whether the BMC is abnormal according to the WDT signal of the BMC.

4. A data communication method is characterized by comprising the following steps: a data communication system of BMC, PCH, SMBus Slave, CPLD, wherein said BMC is connected to said PCH, said CPLD includes SMBus Master, SMBus Switch, said SMBus Master is connected to said PCH, said method comprising:

if yes, controlling the SMBus switch to switch the BMC to the SMBus Master;

5. The data communication method according to claim 4, wherein the CPLD further comprises a bypass, and the determining whether the BMC is abnormal according to the communication information comprises:

6. The data communication method according to claim 5, further comprising, after the controlling the SMBus switch to switch the BMC to the SMBus Master:

judging whether the data in the buffer area of the CPLD is valid or not;

if so, controlling the SMBus Master to communicate with the PCH according to the data of the buffer area;

if not, taking over and executing the information sent by the PCH, and carrying out read-write operation on the SMBus Slave.

7. The data communication method according to claim 6, wherein the controlling the SMBus Master to communicate with the PCH and performing read-write operation on the SMBus Slave according to the information sent by the PCH includes:

receiving a preset address of the SMBus Slave sent by the PCH, and the length of the communication data;

and if the communication data is the write instruction, writing the write data in the communication data into the corresponding SMBus Slave according to the preset address of the SMBus Slave.

8. A data communication apparatus, characterized in that, it is applied to a data communication apparatus comprising: BMC, PCH, SMBus Slave, CPLD's data communication system, wherein, BMC is connected with said PCH, said CPLD includes SMBus Master, SMBus Switch, said SMBus Master is connected with said PCH, said apparatus includes:

9. A data communications apparatus comprising a memory for storing a computer program;

a processor for implementing the steps of the data communication method of any one of claims 4 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the data communication method according to any one of claims 4 to 7.