CN115426315B - Information processing method, device and equipment - Google Patents
Information processing method, device and equipment Download PDFInfo
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Abstract
The invention provides an information processing method, an information processing device and information processing equipment, wherein the method comprises the following steps: acquiring at least one policy table; storing the at least one policy table in a target memory area of a double-rate synchronous dynamic random access memory (DDR SDRAM), wherein the DDR SDRAM comprises at least two memory areas, and the addresses of two adjacent memory areas are continuous; and caching a target policy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target policy table is a policy table matched with a target message. The scheme of the invention can realize higher rate matching and greatly improve the table look-up rate.
Description
Technical Field
The present invention relates to the field of computer information processing technologies, and in particular, to an information processing method, apparatus, and device.
Background
With the popularization and application of high-speed networks, the requirements on the strategy matching of IP messages and the searching speed of the route are higher. In the traditional design, an external TCAM (ternary content addressable memory) special chip is adopted for IP message strategy matching and route searching, and the method has high cost and high power consumption.
Disclosure of Invention
The technical problem to be solved by the invention is how to provide an information processing method, device and equipment. The matching rate is improved, and the power consumption is reduced.
In order to solve the technical problems, the technical scheme of the invention is as follows:
an information processing method, the method comprising:
acquiring at least one policy table;
storing the at least one policy table in a target memory area of a double-rate synchronous dynamic random access memory (DDR SDRAM), wherein the DDR SDRAM comprises at least two memory areas, and the addresses of two adjacent memory areas are continuous;
and caching a target policy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target policy table is a policy table matched with a target message.
Optionally, storing the at least one policy table in a target storage area of the ddr sdram includes:
performing hash operation according to the content of a first policy table in the at least one policy table to obtain a first result;
performing hash operation according to the content of a second policy table in the at least one policy table to obtain a second result;
and storing the at least one policy table in a target memory area of the double rate synchronous dynamic random access memory according to the first result and the second result.
Optionally, storing the at least one policy table in a target storage area of the ddr sdram according to the first result and the second result, including:
if the first result is different from the second result, storing the first policy table in a first target storage area according to the first result and storing the second policy table in the first target storage area according to the second result;
and if the first result is the same as the second result, storing the first strategy table in a first target storage area, carrying out Hash operation on the second result to obtain a third result, and storing the second strategy table according to the third result.
Optionally, storing the first policy table in a first target storage area according to the first result includes:
and taking the low N1 bits of the first result as the storage address of the first policy table, and storing the first policy table in the first target storage area, wherein N1 is a positive integer.
Optionally, storing the second policy table in the first target storage area according to the second result includes:
and taking the low N1 bits of the second result as the storage address of the second policy table, and storing the second policy table in the first target storage area, wherein N1 is a positive integer.
Optionally, storing the second policy table according to the third result includes:
if the third result is different from the first result and the second result, taking the low N1 bit of the third result as a storage address of the second policy table, and storing the second policy table in a second target storage area, wherein the second target storage area and the first target storage area are adjacent storage areas;
and if the third result is the same as the first result or the second result, performing hash operation on the second result and the third result to obtain a fourth result, and if the fourth result is different from the first result, the second result and the third result, taking the low N1 bit of the fourth result as the address of the second policy table, and storing the second policy table in a third target storage area, wherein N1 is a positive integer.
Optionally, caching the target policy table in the target storage area into a random access memory corresponding to the target storage area, including:
searching a target policy table from the first target storage area according to the first result, and if the content in the first target storage area is not 0, analyzing the target policy table;
and transferring the low N2 bits of the preset field in the target policy table to a random access memory corresponding to the target storage area, wherein N2 is a positive integer.
Optionally, the information processing method further includes:
receiving a query request for a target policy table;
and reading the target policy table from the random access memory according to the query request.
An embodiment of the present invention further provides a key processing apparatus, including:
the obtaining module is used for obtaining at least one policy table;
the processing module is used for storing the at least one policy table in a target storage area of a double-rate synchronous dynamic random access memory (DDR SDRAM), the DDR SDRAM comprises at least two storage areas, and the addresses of two adjacent storage areas are continuous; and caching a target policy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target policy table is a policy table matched with a target message.
Embodiments of the present invention also provide a computing device, comprising: a processor, a memory storing a computer program which, when executed by the processor, performs the method as described above.
The scheme of the invention at least comprises the following beneficial effects:
the scheme of the invention adopts two-level cache mechanisms of an external double-rate synchronous dynamic random access memory DDR and an internal random access memory RAM, the external DDR is used as the first-level cache of the matching content table, and the DDR has larger storage space and can be used for storing tens of millions of matching strategies. The internal RAM is used as a content storage address which is actually matched due to the characteristic of high read-write speed. The strategy table is firstly stored in the external DDR, when the matching is hit, the address is recorded, and the memory content of the DDR is simultaneously stored in the internal RAM. After many times of training and learning, a large number of active strategies are stored in the internal RAM, and the hit probability of matching is increased. Because the read-write speed of the internal RAM is extremely high, the multi-port parallel operation can be realized, and the matching speed is greatly improved.
Drawings
FIG. 1 is a flow chart diagram of an information processing method of an embodiment of the invention;
FIG. 2 is a flow chart of a fast lookup method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a policy table according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a specific format of a policy table according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of 2 computing hashes of a policy table according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a 3-time hash computation of a policy table according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of an address table maintained by the address scheduler of an embodiment of the invention;
FIG. 8 is a diagram illustrating the main format of a policy table according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a format of a received message according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a mapping relationship between a first-level cache and a second-level cache according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a first level and second level cache map according to an embodiment of the present invention;
fig. 12 is a block diagram of an information processing apparatus according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As shown in fig. 1, an embodiment of the present invention provides an information processing method, including:
step 12, storing the at least one policy table in a target memory area of a double-rate synchronous dynamic random access memory, where the double-rate synchronous dynamic random access memory includes at least two memory areas, and addresses of two adjacent memory areas are consecutive;
and step 13, caching the target policy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target policy table is a policy table matched with a target message.
In this embodiment of the present invention, the policy table is first stored in an external DDR (double data rate synchronous dynamic random access memory), and when the address of the policy table matches and hits the address stored in the DDR, the address is recorded, and the memory content of the DDR is transferred to an internal RAM (random access memory). A large number of active strategies are stored in the internal RAM, and the hit probability of matching is increased. Because the read-write speed of the internal RAM is extremely high, the multi-port parallel operation can be realized, and the matching speed is greatly improved.
In an optional embodiment of the present invention, as shown in fig. 3, the policy table issued by the CPU is in a form of a table header and a content, the policy table includes quintuple and key information, and a hash result calculated according to the content of the policy table;
in this embodiment, the hash value calculation uses a cryptographic algorithm SM3 (cryptographic hash algorithm), which is mainly used for digital signature and verification, message authentication code generation, and verification random number generation.
As shown in fig. 4 to 6, the policy table includes the quintuple and the key information, and the HASH result format is: format after three HASH calculations.
In an alternative embodiment of the present invention, step 12 may include:
and step 122, performing hash operation according to the content of a second policy table in the at least one policy table to obtain a second result.
Step 123, storing the at least one policy table in a target storage area of the ddr sdram according to the first result and the second result.
In an alternative embodiment of the present invention, step 123 may include:
step 1231, if the first result is different from the second result, storing the first policy table in a first target storage area according to the first result and storing the second policy table in the first target storage area according to the second result; in this embodiment, 4096 policy tables are taken as an example, software records results of each policy table HASH1, and if the 1 st policy table and the 4096 th policy table HASH1 do not conflict, the first policy table may be directly stored in the first target storage area and the second policy table may be directly stored in the first target storage area;
step 1232, if the first result is the same as the second result, storing the first policy table in a first target storage area, performing hash operation on the second result to obtain a third result, and storing the second policy table according to the third result. In this embodiment, taking 4096 policy tables as an example, the software records the HASH1 result of each policy table, and if the 1 st policy table and the 4096 th policy table HASH1 conflict, it will be identified in the COLLISON field. For example: in this case, the results of the results 32'h3a4b5e7f8c7d0102 in strategy table 1 and the two values 32' h3a4b5e7f8c7d0102 in strategy table 4096 in HASH1 are equal to each other, and it is necessary to calculate the second HASH2 result (32 bit low) of the 4096 strategy table and place the result in the tail of the strategy table, and if the result of the second HS4AH 2 is 32 h5e3f2a34672a3d, the results are compared with the results of all the previous strategy tables and no collision is found, and the result is issued.
In an optional embodiment of the present invention, in step 1231, storing the first policy table in the first target storage area according to the first result includes:
step 12311, using the low N1 bits of the first result as the storage address of the first policy table, storing the first policy table in the first target storage area, where N1 is a positive integer, for example, using the low 32 bits of the first result as the storage address of the first policy table, and storing the first policy table in the first target storage area.
In step 1231, storing the second policy table in the first target storage area according to the second result may include:
step 12312, using the low N1 bits of the second result as the storage address of the second policy table, storing the second policy table in the first target storage area, where N1 is a positive integer, e.g., using the low 32 bits of the second result as the storage address of the second policy table, and storing the second policy table in the first target storage area.
In an optional embodiment of the present invention, in step 1232, storing the second policy table according to the third result includes:
step 12321, if the third result is different from the first result and the second result, using the low N1 bit of the third result as a storage address of the second policy table, and storing the second policy table in a second target storage area, where the second target storage area and the first target storage area are adjacent storage areas;
step 12322, if the third result is the same as the first result or the second result, performing a hash operation on the second result and the third result to obtain a fourth result, and if the fourth result is different from the first result, the second result, and the third result, using the low N1 bit of the fourth result as an address of the second policy table to store the second policy table in a third target storage area.
If the first hash result has no conflict, directly storing the first hash result into a first target storage area DDR _ SEG1 of the double-rate synchronous dynamic random access memory; if the first hash result conflicts, performing second hash on the first hash result and storing the first hash result in a DDR _ SEG2 space of a second target storage area of the double-rate synchronous dynamic random access memory; and if the conflict continues for the second time, performing third hash on the second result, and storing the result into a DDR _ SEG3 space of a third target storage area of the double-rate synchronous dynamic random access memory.
In specific implementation, as shown in fig. 4 to 6:
1) Taking 4096 tables as an example, the software records each table phase HASH1 result.
2) If the 1 st table phase and the 4096 th table phase conflict with the first HASH value HASH1, they are identified in the name conflict COLLISON field.
For example: in this case, it is necessary to calculate the result (lower 32 bits) of the second HASH value HASH2 of the 4096 front phases and put the result to the front phase tail, and to send the result if the result of the second HASH value HSAH2 is 32'h3a4b5e7f8c7d0102 is 32' h5e3f4d2a34673d and the HASH results of all the front phases are compared and no collision is found.
3) And the receiving end takes the value 32' h5e3f4d2a34672a3d of the lower 32b bit of the second HASH value HASH2 value as the storage address of the double-rate synchronous dynamic random access memory DDR, and directly stores the storage address into the double-rate synchronous dynamic random access memory DDR.
4) If the first hash result conflicts, the first hash result is hashed for the second time and stored in the DDR _ SEG2 space, and if the second hash result conflicts continuously for the second time, the second hash result is hashed for the third time and stored in the DDR _ SEG3 space. If the first HASH value HASH1 is consistent in collision calculation, and if the second HASH value HASH2 result is also in collision, the results of the previous 2 times need to be subjected to HASH calculation together to obtain a third HASH value HASH3, and the third HASH value HASH3 is placed at the tail of the policy table. In this embodiment, the hash calculation uses a cryptographic algorithm SM3, and takes the lower 32 bits of the result.
In an alternative embodiment of the present invention, step 13 may include:
step 131, searching a target policy table from the first target storage area according to the first result, and if the content in the first target storage area is not 0, analyzing the target policy table;
and 132, transferring the low N2 bits of the preset field SEQ _ NUM in the target policy table to a Random Access Memory (RAM) corresponding to the target storage area.
In this embodiment, as shown in fig. 7, the address scheduler maintains an address list, which includes the following specific contents: the identity ID, the first HASH value HASH1, the second HASH value HASH2 and the third HASH value HASH3.
In an alternative embodiment of the present invention, random access memory RAM 1-RAM 128 is used to store the contents of the policy after a hit as a second level cache.
Specifically, table matching first matches the contents of the second level cache, and if hit, the table is stored in the random access memory RAM; and if the double-speed synchronous dynamic random access memory is not hit, the content of the first-level cache double-speed synchronous dynamic random access memory DDR is matched.
In an optional embodiment of the present invention, the information processing method further includes:
step 14, receiving a query request for a target policy table;
and step 15, reading the target policy table from the random access memory according to the query request.
In this embodiment, as shown in fig. 2, an address Processor IP Processor module initiates reading of the double data rate synchronous dynamic random access memory DDR and reading and comparing of the contents of the random access memory RAM.
The address Processor IP Processor module maintains the content consistency between the secondary cache RAM and the primary cache DDR. In the double-rate synchronous dynamic random access memory DDR, all the table phases issued by software are stored. These facies contents are all user-configurable, requiring all storage reservations.
In the random access memory RAM, the table phases matched in the actual scene, that is, the active table phases, are stored.
In a specific implementation, the message 1 is an IGMP message matched with the five-tuple information of the table facies 1, and the table facies 1 is transferred from the first-level cache to the second-level cache.
Message 2 matches the five tuple information of entry 4096 for the ICMP message, and entry 4096 is transferred from the first level cache to the second level cache.
By analogy, if the message 128 matches the five-tuple information of the phase 128 for the ROP message, the phase 128 is transferred from the first-level cache to the second-level cache.
Finally, 128 table phases which are once hit are stored in the second-level cache, and the following messages are firstly subjected to table lookup in the second-level cache, so that the hit probability is increased.
In an optional embodiment of the present invention, the storage content of the second level cache is consistent with the storage content of the first level cache, and the storage address calculation methods are different.
As shown in fig. 8, for issuing the main contents of the table phase by software, the contents in the DDR take the hash value as an address, and the ID value in the secondary cache as an address (i.e. the SEQ _ NUM field in the table phase).
In an optional embodiment of the present invention, the specific process of the first-level cache to the second-level cache is as follows:
step (a), as shown in fig. 9, the computation service port receives a hash value of the packet quintuple information:
and calculating a hash value by adopting an SM3 hash algorithm according to a network data exchange rule PROTOCOL, session initiation PROTOCOLs SIP and DIP, a destination PORT D _ PORT and a source PORT S _ PORT.
Step (b), storing the first-level cache data into a second-level cache:
as shown in fig. 10, the table phase is searched in the DDR according to the HASH result calculated in step (a), if the content in the DDR is not 0, the table phase is parsed, whether HASH results in the table phase conflict or not is further parsed, and if so, the two table phases are continuously read according to the second HASH value HASH 2. And (4) as the table phase not only retains the hash result but also retains the SEQ _ NUM result, the lower 7 bits of the SEQ _ NUM number in the read table phase are transferred to the internal random access memory RAM.
The external double-rate synchronous dynamic random access memory DDR and the internal random access memory RAM are not in linear correspondence.
Step (c), updating the second-level cache:
if the newly received message hits in the RAM, the service is processed directly according to the hit result. The internal 128 blocks of random access memory RAM can operate in parallel and the processing speed is very fast.
If the received message can not hit in the internal random access memory RAM, repeating the operation of the step (a)/the operation of the step (b), continuously reading from the DDR, and repeating the above actions.
And (d) deleting a primary table phase:
when a first-level table phase is deleted and updated, searching a HASH address needing to be updated according to a deletion mark in the table phase under software to delete the content in the DDR.
Step (e), deleting the secondary table phase:
as shown in fig. 11, according to the hash address to be deleted, the first-level cache mapping table is searched, and whether the table exists in the second-level cache is searched, if so, the table is deleted, and if not, the table is not required to be deleted.
In the embodiment of the invention, the external DDR adopts a MICRON DDR4 chip, and the interface controller of the DDR adopts MIG DDR4 of xilins; the internal secondary cache adopts internal ram or UltraRam of xilinx; when the IP messages need to be matched, the strategy table in the secondary cache RAM is matched firstly, and if the strategy table is successfully matched, the next matching is continued. If the matching is not successful, the mapping position in the DDR is searched in the address distributor according to the HASH value, the DDR extraction is removed, and if the matching is successful, the corresponding representation is updated to the secondary cache RAM. And when the next time the appearance matching is needed, directly reading from the second-level cache.
The embodiment of the invention autonomously updates the active strategy table, and when no expression is hit in the secondary cache RAM, the expression is read from the primary cache DDR, thereby greatly improving the table look-up rate. And when the first-level cache is read, the storage strategy table in the DDR is directly read according to the HASH address. By using the external DDR and the internal RAM, 10G high-speed appearance matching search can be realized, the problems of high cost and high power consumption of a TCAM chip are solved through algorithm architecture design, the TCAM interface speed is not limited, and higher speed matching can be realized by expanding the number of the secondary cache RAMs.
As shown in fig. 12, an embodiment of the present invention also provides an information processing apparatus 120, including:
an obtaining module 121, configured to obtain at least one policy table;
the processing module 122 is configured to store the at least one policy table in a target memory area of a double rate synchronous dynamic random access memory, where the double rate synchronous dynamic random access memory includes at least two memory areas, and addresses of two adjacent memory areas are consecutive; and caching a target policy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target policy table is a policy table matched with a target message.
Optionally, storing the at least one policy table in a target storage area of the ddr sdram, including:
performing hash operation according to the content of a first policy table in the at least one policy table to obtain a first result;
performing hash operation according to the content of a second policy table in the at least one policy table to obtain a second result;
and storing the at least one policy table in a target storage area of the double rate synchronous dynamic random access memory according to the first result and the second result.
Optionally, storing the at least one policy table in a target storage area of the ddr sdram according to the first result and the second result, including:
if the first result is different from the second result, storing the first policy table in a first target storage area according to the first result and storing the second policy table in the first target storage area according to the second result;
and if the first result is the same as the second result, storing the first strategy table in a first target storage area, carrying out Hash operation on the second result to obtain a third result, and storing the second strategy table according to the third result.
Optionally, storing the first policy table in the first target storage area according to the first result includes:
and taking the low N1 bit of the first result as a storage address of the first policy table, and storing the first policy table in the first target storage area, wherein N1 is a positive integer.
Optionally, storing the second policy table in the first target storage area according to the second result includes:
and taking the low N1 bit of the second result as a storage address of the second policy table, and storing the second policy table in the first target storage area, wherein N1 is a positive integer.
Optionally, storing the second policy table according to the third result includes:
if the third result is different from the first result and the second result, the low N1 bit of the third result is used as a storage address of the second policy table, the second policy table is stored in a second target storage area, and the second target storage area and the first target storage area are adjacent storage areas;
and if the third result is the same as the first result or the second result, performing hash operation on the second result and the third result to obtain a fourth result, and if the fourth result is different from the first result, the second result and the third result, taking the low N1 bit of the fourth result as the address of the second policy table, and storing the second policy table in a third target storage area, wherein N1 is a positive integer.
Optionally, caching the target policy table in the target storage area into a random access memory corresponding to the target storage area, including:
searching a target policy table from the first target storage area according to the first result, and if the content in the first target storage area is not 0, analyzing the target policy table;
and transferring and storing the low N2 bits of the preset field in the target policy table into a random access memory corresponding to the target storage area, wherein N2 is a positive integer.
Optionally, the information processing method further includes:
receiving a query request for a target policy table;
and reading the target policy table from the random access memory according to the query request.
Embodiments of the present invention also provide a computing device, comprising: a processor, a memory and a program or instructions stored on the memory and executable on the processor, which when executed by the processor, implement the steps of the method as described above.
Embodiments of the present invention also provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method as described above. All the implementation manners in the above method embodiments are applicable to the embodiment, and the same technical effect can be achieved.
According to the embodiment of the invention, the external double-rate synchronous dynamic random access memory DDR and the internal random access memory RAM are used, the table matching search of 10G high rate can be realized, the problems of high cost and high power consumption of a TCAM chip are solved through the design of an algorithm architecture, the interface rate of the TCAM chip is not limited, and the higher rate matching can be realized by expanding the number of the secondary cache random access memory RAM.
The information processing method can autonomously update the active strategy table phase, and when the table phase is not hit in the RAM of the secondary cache random access memory, the DDR of the primary cache double-rate synchronous dynamic random access memory is read; when the first-level cache is removed for reading, the stored phase in the DDR can be directly read according to the HASH address, and the table lookup rate is greatly improved.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present invention or a part thereof which substantially contributes to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.
Furthermore, it is to be noted that in the device and method of the invention, it is obvious that the individual components or steps can be decomposed and/or recombined. These decompositions and/or recombinations are to be regarded as equivalents of the present invention. Also, the steps of performing the series of processes described above may naturally be performed chronologically in the order described, but need not necessarily be performed chronologically, and some steps may be performed in parallel or independently of each other. It will be understood by those skilled in the art that all or any of the steps or elements of the method and apparatus of the present invention may be implemented in any computing device (including processors, storage media, etc.) or network of computing devices, in hardware, firmware, software, or any combination thereof, which can be implemented by those skilled in the art using their basic programming skills after reading the description of the present invention.
Thus, the objects of the invention may also be achieved by running a program or a set of programs on any computing device. The computing device may be a general purpose device as is well known. The object of the invention is thus also achieved merely by providing a program product comprising program code for implementing the method or device. That is, such a program product also constitutes the present invention, and a storage medium storing such a program product also constitutes the present invention. It is to be understood that the storage medium may be any known storage medium or any storage medium developed in the future. It is further noted that in the apparatus and method of the present invention, it is apparent that each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be regarded as equivalents of the present invention. Also, the steps of executing the series of processes described above may naturally be executed chronologically in the order described, but need not necessarily be executed chronologically. Some steps may be performed in parallel or independently of each other.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. An information processing method, characterized in that the method comprises:
acquiring at least one policy table;
storing the at least one policy table in a target memory area of a double-rate synchronous dynamic random access memory (DDR SDRAM), wherein the DDR SDRAM comprises at least two memory areas, and the addresses of two adjacent memory areas are continuous;
caching a target strategy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target strategy table is a strategy table matched with a target message;
storing the at least one policy table in a target memory area of the DDR SDRAM, comprising:
performing hash operation according to the content of a first policy table in the at least one policy table to obtain a first result;
performing hash operation according to the content of a second policy table in the at least one policy table to obtain a second result;
storing the at least one policy table in a target memory area of the DDR SDRAM according to the first result and the second result;
storing the at least one policy table in a target memory area of the DDR SDRAM according to the first result and the second result, comprising:
if the first result is different from the second result, storing the first policy table in a first target storage area according to the first result and storing the second policy table in the first target storage area according to the second result;
and if the first result is the same as the second result, storing the first policy table in a first target storage area, performing hash operation on the second result to obtain a third result, and storing the second policy table according to the third result.
2. The information processing method of claim 1, wherein storing the first policy table in a first target storage area according to the first result comprises:
and taking the low N1 bit of the first result as a storage address of the first policy table, and storing the first policy table in the first target storage area, wherein N1 is a positive integer.
3. The information processing method of claim 1, wherein storing the second policy table in the first target storage area according to the second result comprises:
and taking the low N1 bits of the second result as the storage address of the second policy table, and storing the second policy table in the first target storage area, wherein N1 is a positive integer.
4. The information processing method according to claim 1, wherein storing the second policy table according to the third result includes:
if the third result is different from the first result and the second result, the low N1 bit of the third result is used as a storage address of the second policy table, the second policy table is stored in a second target storage area, and the second target storage area and the first target storage area are adjacent storage areas;
if the third result is the same as the first result or the second result, performing hash operation on the second result and the third result to obtain a fourth result, and if the fourth result is different from the first result, the second result and the third result, taking the low N1 bit of the fourth result as the address of the second policy table and storing the second policy table in a third target storage area; n1 is a positive integer.
5. The information processing method of claim 1, wherein caching the target policy table in the target storage area into a random access memory corresponding to the target storage area comprises:
searching a target policy table from the first target storage area according to the first result, and if the content in the first target storage area is not 0, analyzing the target policy table;
and transferring and storing the low N2 bits of the preset field in the target policy table into a random access memory corresponding to the target storage area, wherein N2 is a positive integer.
6. The information processing method according to claim 1, further comprising:
receiving a query request for a target policy table;
and reading the target policy table from the random access memory according to the query request.
7. An information processing apparatus characterized by comprising:
the obtaining module is used for obtaining at least one policy table;
the processing module is used for storing the at least one policy table in a target storage area of a double-rate synchronous dynamic random access memory (DDR SDRAM), the DDR SDRAM comprises at least two storage areas, and the addresses of two adjacent storage areas are continuous; caching a target strategy table in the target storage area into a random access memory corresponding to the target storage area, wherein the target strategy table is a strategy table matched with a target message;
storing the at least one policy table in a target memory area of the DDR SDRAM, comprising:
performing hash operation according to the content of a first policy table in the at least one policy table to obtain a first result;
performing hash operation according to the content of a second policy table in the at least one policy table to obtain a second result;
storing the at least one policy table in a target memory area of the DDR SDRAM according to the first result and the second result;
storing the at least one policy table in a target memory area of the DDR SDRAM according to the first result and the second result, comprising:
if the first result is different from the second result, storing the first policy table in a first target storage area according to the first result and storing the second policy table in the first target storage area according to the second result;
and if the first result is the same as the second result, storing the first policy table in a first target storage area, performing hash operation on the second result to obtain a third result, and storing the second policy table according to the third result.
8. A computing device, comprising: processor, memory storing a computer program which, when executed by the processor, performs the method of any of claims 1 to 6.
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| CN102035727A (en) * | 2010-11-17 | 2011-04-27 | 杭州华三通信技术有限公司 | Method and equipment for processing routing |
| CN111782578A (en) * | 2020-05-29 | 2020-10-16 | 西安电子科技大学 | Cache control method, system, storage medium, computer equipment and application |
| CN114501135A (en) * | 2022-01-05 | 2022-05-13 | 伟乐视讯科技股份有限公司 | Method and device for realizing debouncing of code stream by two-stage smoothing |
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| US8776207B2 (en) * | 2011-02-16 | 2014-07-08 | Fortinet, Inc. | Load balancing in a network with session information |
| CN108363621B (en) * | 2018-01-18 | 2020-09-01 | 东软集团股份有限公司 | Message forwarding method and device under numa architecture, storage medium and electronic equipment |
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| CN102035727A (en) * | 2010-11-17 | 2011-04-27 | 杭州华三通信技术有限公司 | Method and equipment for processing routing |
| CN111782578A (en) * | 2020-05-29 | 2020-10-16 | 西安电子科技大学 | Cache control method, system, storage medium, computer equipment and application |
| CN114501135A (en) * | 2022-01-05 | 2022-05-13 | 伟乐视讯科技股份有限公司 | Method and device for realizing debouncing of code stream by two-stage smoothing |
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