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CN115425962A - Single-event transient reinforcing circuit applied to DC-DC converter - Google Patents

Single-event transient reinforcing circuit applied to DC-DC converter Download PDF

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Publication number
CN115425962A
CN115425962A CN202210948689.5A CN202210948689A CN115425962A CN 115425962 A CN115425962 A CN 115425962A CN 202210948689 A CN202210948689 A CN 202210948689A CN 115425962 A CN115425962 A CN 115425962A
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circuit
mos transistor
mos tube
current
mos
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郭仲杰
刘楠
卢沪
林涛
邱子忆
李梦丽
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Xian University of Technology
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Xian University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a single-event transient reinforcing circuit applied to a DC-DC converter, which comprises an RHBD circuit, wherein the forward end of the RHBD circuit is sequentially connected with a sampling capacitor C S Upper polar plate and sampling switch S 1 Sampling switch S 1 The other end of the buffer is connected to the output end of the analog buffer, the positive input end of the buffer is directly connected to the output node of the error amplifier EA, the output end of the RHBD circuit is directly connected with the output end of the error amplifier EA, the Control circuit collects load transient information from the error amplifier EA, and outputs an EN signal to Control the RHBD circuit. When the system is stable, the circuit outputs low level, and the reinforcing circuit works normally to detect the single event transient effect and compensate in time. When the system becomes negativeWhen the load responds to the transient state, the circuit outputs high level, and the reinforcing circuit is closed, so that the problem of system oscillation caused by misoperation of the reinforcing circuit to the transient response of the load is solved.

Description

Single-event transient reinforcing circuit applied to DC-DC converter
Technical Field
The invention belongs to the technical field of radiation hardening of a switching power supply, and relates to a single-particle transient hardening circuit applied to a DC-DC converter.
Background
DC-DC converters play a crucial role in the power system of aerospace power systems. DC-DC converters are commonly used to generate a regulated DC output voltage with high power efficiency from a DC input source, and any variation in the output voltage caused by irradiation may affect the operation of other circuits powered by the converter. With the development of deep submicron technology, the failure rate caused by Single Event Transient (SET) is greatly improved. SET has attracted a high attention. At present, the radiation-resistant reinforcing technology of the process and the radiation-resistant reinforcing technology of the digital integrated circuit are mainly focused in the research field of the radiation-resistant integrated circuit for aerospace in China, and the radiation-resistant analog integrated circuit is rarely researched.
An Error Amplifier (EA) is used as one of the core modules of the voltage loop of the DC-DC converter to feed back the voltage V FB And a reference voltage V REF The output of the differential amplifier is used as an input signal of the inverting terminal of the PWM comparator, and meanwhile, the EA provides enough gain for the loop so as to ensure the precision of feedback regulation. When heavy ions or high-energy electrons bombard an output node of the EA and trigger an Analog Single-particle Transient (ASET) pulse, the node can generate large Transient voltage change, and a large capacitor C of the frequency compensation module C The recovery is slow, the PWM outputs wide and narrow pulses, the duty ratio D is changed, and the output voltage V is caused OUT Ripple voltage increase or output voltage V OUT Large fluctuations occur.
The reinforcement effect of the traditional layout-level or process-level reinforcement scheme cannot provide good reliability evaluation during circuit-level design, which brings great trouble to circuit design, and the reinforcement scheme is urgently required to be introduced from the circuit level to evaluate the anti-irradiation capability of the circuit at present.
Disclosure of Invention
The invention aims to provide a single-event transient reinforcing circuit applied to a DC-DC converter, which solves the problem that an EA output node in a voltage loop of the DC-DC converter causes an output voltage V due to the influence of ASET OUT Increase of ripple voltage or output voltage V OUT The problem of fluctuations.
The technical scheme adopted by the invention is that the single-particle transient reinforcing circuit applied to the DC-DC converter comprises an RHBD circuit, wherein the positive end of the RHBD circuit is sequentially connected with a sampling capacitor C S Upper polar plate and sampling switch S 1 Sampling switch S 1 The other end of the buffer is connected to the output end of the analog buffer, the positive input end of the buffer is directly connected to the output node of the error amplifier EA, the output end of the RHBD circuit is directly connected with the output end of the error amplifier EA, the Control circuit collects load transient information from the error amplifier EA, and outputs an EN signal to Control the RHBD circuit.
The invention is also characterized in that:
the Control circuit comprises a current mirror I, the current mirror I is connected with a current mirror II, and a current subtraction circuit I is formed between the current mirror I and the current mirror II;
the current mirror III is connected with the current mirror IV, and a current subtraction circuit II is formed between the current mirror III and the current mirror IV;
the current mirror II is connected with a two-input XNOR gate through an inverter INV1 and a current mirror IV through an inverter INV 2.
The current mirror I comprises an MOS tube M 1 MOS transistor M 1 Source end of the MOS tube M is grounded, and the MOS tube M is connected with a power supply 1 Drain electrode of and MOS tube M 2 Is connected with the source electrode of the MOS transistor M 2 The drain electrode of (1) is the output node of the error amplifier EA, and the MOS tube M 1 、M 2 A MOS transistor M for pull-down branch of output branch of error amplifier EA 3 MOS transistor M 4 Respectively with MOS transistor M 1 MOS transistor M 2 Is connected with the grid and is used for copying the current of a pull-down branch circuit, and an MOS tube M 3 Source electrode grounding drain electrode and MOS tube M 4 Is connected to the source of (a).
MOS transistor M 3 MOS tube M 4 The cascode stage circuit is used as an input signal of the current subtraction circuit I, and the MOS transistor M 4 Drain and bias current I bias1 Connected, MOS transistor M 5 MOS tube M 6 The formed cascode stage circuit is used as an output signal of the current subtraction circuit I; MOS transistor M 5 Gate, drain and M 4 Is connected with the drain electrode of the MOS transistor M 6 The grid electrode, the drain electrode and the MOS tube M of 5 Is connected with the source electrode of the MOS transistor M 6 The source is connected to VDD.
The current mirror II comprises an MOS tube M 7 And MOS transistor M 8 MOS transistor M 7 、M 8 Respectively connected with MOS transistor M 5 、M 6 Is connected with the grid of the MOS transistor M 8 Source electrode of the transistor is connected with VDD and MOS transistor M 8 Drain electrode of and MOS tube M 7 Is connected with the source electrode of the MOS transistor M 7 As the output of the current mirror II and the reference current I REF1 And to the input of inverter INV 1.
The current mirror III comprises an MOS tube M 1 ' and MOS tube M 2 ', MOS tube M 1 ’、M 2 The output branch of the error amplifier EA is a pull-up branch, and the MOS transistor M is a pull-up branch 2 The source electrode of the transistor is connected with VDD, and the MOS transistor M 2 ' the drain electrode and the MOS tube M 1 ' the source electrodes are connected, and the MOS tube M 1 The drain of the transistor is the output node of the error amplifier EA, and the MOS transistor M 3 ’、M 4 'the grid electrode of the' is respectively connected with the MOS transistor M 1 ’、M 2 ' the grid electrode of the transistor is connected with the MOS transistor M for copying the pull-up branch current 4 The source electrode of the transistor is connected with VDD, the drain electrode is connected with the MOS transistor M 3 ' are connected at their source ends.
MOS transistor M 3 ’、M 4 ' the formed cascode stage circuit is used as an input signal of the current subtraction circuit II, and the MOS tube M 3 ' Drain and bias Current I bias2 Is connected with the output of the MOS transistor M 5 ' MOS tube M 6 ' the formed cascode stage circuit is used as an output signal of the current subtraction circuit II, and the MOS transistor M 6 ' Gate, drain and M 3 ' the drain electrode of the transistor is connected with the MOS transistor M 5 ' the grid, the drain and the MOS tube M 6 ' the source electrodes of the transistors are connected, and the MOS transistor M 5 The source is grounded.
The current mirror IV comprises an MOS tube M 7 ’、M 8 ', MOS tube M 7 ’、M 8 'the grid of' is respectively connected with MOS transistor M 5 ’、M 6 ' the grid electrode is connected with the MOS tube M 7 ' the source electrode is grounded, the MOS tube M 7 ' the drain and MOS transistor M 8 ' the source electrodes of the transistors are connected, and the MOS transistor M 8 ' the drain of the transistor is used as the output of the current mirror II and the reference current I REF2 Is connected with the input of the inverter INV 2;
the output ends of the inverters INV1 and INV2 are respectively connected with the input ends A and B of the XNOR gate, and the output end of the XNOR gate outputs an EN control signal to control the RHBd circuit.
The single-event transient reinforcing circuit applied to the DC-DC converter has the advantages that the reinforcing circuit is simple in structure, and the reinforced circuit and the reinforcing circuit achieve suppression of single-event transient effects. Meanwhile, the load transient state and the single-particle transient state are distinguished, and misoperation of a reinforcing circuit is avoided. Compared with the traditional layout-level reinforcement scheme, the method can evaluate and design the anti-irradiation capability of the circuit in the design stage of the schematic diagram of the circuit. Meanwhile, the problem that the EA output node in a voltage loop of the DC-DC converter causes the output voltage V due to the influence of ASET is solved OUT Increase of ripple voltage or output voltage V OUT And the recovery time of the DC-DC converter loop after single-event disturbance is accelerated due to the problem of fluctuation.
Drawings
Fig. 1 is a schematic diagram of a single-event transient reinforcing circuit applied to a DC-DC converter according to the present invention.
Fig. 2 is a schematic diagram of a control circuit of the single-event transient reinforcing circuit applied to the DC-DC converter according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The single-event transient reinforcing circuit applied to the DC-DC converter comprises an RHBD circuit as shown in figure 1, wherein the positive end of the RHBD circuit is sequentially connected with a sampling capacitor C S Upper polar plate and sampling switch S 1 One terminal of (C), a sampling capacitor C S The lower polar plate is grounded and a sampling switch S is arranged 1 The other end of the RHBD circuit is connected to the output end of the analog buffer, the positive input end of the buffer is directly connected to the output node of the error amplifier EA, and the output end of the RHBD circuit is directly connected with the output end of the error amplifier EA to provide a charging and discharging circuit. A resistor Rc is connected between the error amplifier EA and the analog buffer, and the resistor Rc is connected with a compensation capacitor Cc; and the Control circuit collects load transient information from the error amplifier EA and outputs an EN signal to Control the RHBD circuit.
As shown in FIG. 2, the Control circuit includes a current mirror I, a current mirror II, a current mirror III, a current mirror IV, a current subtraction circuit I, a current subtraction circuit II, and a bias current I bias1 、I bias2 Reference current I REF1 Reference current I REF2 An inverter INV1, an inverter INV2 and a two-input XNOR.
The current mirror I comprises an MOS tube M 1 ～M 4 ，M 1 、M 2 A pull-down branch for the output branch of the error amplifier EA, a MOS transistor M 1 Source electrode of the MOS transistor M is grounded, and the MOS transistor M is connected with a power supply 1 Drain electrode of (3) and MOS tube M 2 Is connected with the source electrode of the MOS transistor M 2 The drain electrode of (1) is the output node of the error amplifier EA, and the MOS tube M 3 MOS transistor M 4 Respectively with MOS transistor M 1 MOS transistor M 2 Is connected with the gate of the transistor for duplicating the pull-down branch current, wherein the MOS transistor M 3 Source electrode grounded drain electrode and current tube M 4 Is connected to the source of (a).
MOS transistor M 3 MOS transistor M 4 The cascode circuit is used as an input signal of the current subtraction circuit I, and the MOS tube M 4 Drain and bias current I bias1 Is connected with the output of the MOS transistor M 5 MOS transistor M 6 The formed cascode stage circuit is used as an output signal of the current subtraction circuit I;
MOS transistor M 5 Gate, drain and M 4 Is connected with the drain electrode of the MOS transistor M 6 The grid electrode, the drain electrode and the MOS tube M of 5 Is connected with the source electrode of the MOS transistor M 6 The source is connected to VDD.
MOS transistor M 5 ～M 8 Form the electricityFlow mirror II, MOS tube M 7 、M 8 Respectively connected with MOS transistor M 5 、M 6 Is connected with the grid of the MOS transistor M 8 Source electrode of the transistor is connected with VDD and MOS transistor M 8 Drain electrode of and MOS tube M 7 Is connected with the source electrode of the MOS transistor M 7 As the output of the current mirror II and the reference current I REF1 And to the input of inverter INV 1.
The current mirror III comprises an MOS tube M 1 ', MOS tube M 2 ' MOS tube M 3 ' MOS tube M 4 ', MOS tube M 1 ', MOS tube M 2 ' it is an output branch of error amplifier EA, a pull-up branch, MOS tube M 2 The source of the transistor is connected with VDD and MOS transistor M 2 ' Drain and M 1 The source end of the transistor is connected with the MOS transistor M 1 The drain of the transistor is the output node of the error amplifier EA, and the MOS transistor M 3 ' MOS tube M 4 'the grid of' is respectively connected with MOS transistor M 1 ’、M 2 ' connected to the gate for reproducing the pull-up branch current, wherein the MOS transistor M 4 The source electrode of the transistor is connected with the VDD drain electrode and the MOS transistor M 3 ' is connected to the source.
MOS transistor M 3 ', MOS tube M 4 ' the formed cascode stage circuit is used as an input signal of the current subtraction circuit II, and the MOS tube M 3 ' Drain and bias Current I bias2 Is connected with the output of the MOS transistor M 5 ’、M 6 ' the formed cascode stage circuit is used as an output signal of the current subtraction circuit II, and the MOS tube M 6 ' Gate, drain and M 3 ' the drain electrode of the MOS transistor M is connected with the drain electrode of the MOS transistor M 5 ' the grid, the drain and the MOS tube M 6 ' the source electrodes are connected, and the MOS tube M 5 The source is grounded.
MOS transistor M 5 ’～M 8 ' component current mirror IV, MOS tube M 7 ’、M 8 'the grid of the' is respectively connected with the current tube M 5 ’、M 6 ' the grid electrode of the transistor is connected with the MOS transistor M 7 ' the source electrode is grounded, the MOS tube M 7 ' the drain electrode and the MOS tube M 8 ' the source electrodes are connected, and the MOS tube M 8 ' the drain of the transistor is used as the output of the current mirror II and the reference current I REF2 And to the input of inverter INV 2.
The output ends of the inverters INV1 and INV2 are respectively connected with the input ends A and B of the XNOR gate, and the output end of the XNOR gate outputs an EN control signal to control the RHBd circuit.
The invention utilizes the analog buffer to isolate the EA output stage and the sampling circuit. Using a sampling switch S 1 Sampling capacitor C S To EA output V C Sampling is carried out, a sampling signal is used as an input signal of a forward end of the RHBD circuit, a reverse end of the RHBD circuit is directly connected with an EA output end, real-time single-particle detection is carried out on an EA output node, and rapid charging and discharging operations are carried out on the EA output node by comparing the sizes of the sampling signal and the EA output node. When the output end of the RHBD circuit is directly connected with the output end of the EA, the detection and the suppression of the single-event transient effect can be realized.
The circuit of fig. 2 of the present invention detects load current transients. M 1 、M 2 、M 1 ’、M 2 ' is an output stage of an error amplifier, M 3 、M 4 Cascode stage constructed for replica flow-through M 1 、M 2 Current of (M) 4 Drain and bias current I bias1 And M 5 Is connected to the drain electrode, M 5 、M 6 The cascode stage formed serves as a mirror source of a current mirror II, M 7 、M 8 Cascode stage constructed for replica current flow through M 5 、M 6 Current and amplification of, M 7 Drain of (1) and reference current I REF1 The input end of the inverter INV1 is connected, and the output end of the inverter INV1 is connected to the A input end of the XNOR; m 3 ’、M 4 ' constructed cascode stage for replica flow-through M 1 ’、M 2 Current of `, M 3 ' Drain and bias Current I bias2 And M 6 ' the gate and drain are connected, M 5 ’、M 6 ' the constructed cascode stage acts as a mirror source for the current mirror II, M 7 ’、M 8 ' constructed cascode stage for replica current flow through M 5 ’、M 6 Current and amplification of, M 8 ' Drain and reference Current I REF2 The input end of the inverter INV2 is connected, and the output end of the inverter II is connected to the B input end of the XNOR; XNOR for outputting EN signalTo control the RHBd circuit.
The current mirror I is used for copying the pull-down current of the branch where the EA output node is located, namely the pull-down current flows through M 1 、M 2 Is input as a reduced number to the current subtraction circuit 1, i.e. flows through M 4 、M 3 Current of (I) 3 Amplifying the result I of the current subtraction circuit 1 by means of a current mirror 2 4 Using the output of the inverter INV1 to the current mirror II and the reference current I REF1 Shaping the comparison result of (c). The current mirror III is used for copying the pull-up current of the branch where the EA output node is located, namely the current flows through M 2 ’、M 1 ' the current is input to the current subtraction circuit II as a subtracted number, i.e. flows through M 4 ’、M 3 Current of ` 3 ' amplifying the result I of the current subtraction circuit II using a current mirror IV 4 ', the output of the current mirror IV is coupled to the reference current I by the inverter INV2 REF2 The result of the comparison is shaped and the result is input to the B terminal of the XNOR gate in fig. 2.
When the system is stable, the output common mode level of the error amplifier is stable, and the branch current I of the output node is 1 ＝I 2 Current mirror I replicated current I 3 ＝I 1 And is less than I bias1 ，I bias1 For the bias current of the output branch of the error amplifier, in order to meet the practical application requirement, the current is slightly larger than the bias current of the error amplifier, at the moment, the output of the current subtraction circuit is 0, namely I 4 =0, current mirror II replica result I 5 =0, inverter INV1 input is IREF 1 Low, inverter INV1 outputs logic "1"; current I replicated by current mirror III 3 ’＝I 2 And is less than I bias2 ，I bias2 For the bias current of the output branch of the error amplifier, in order to meet the practical application requirement, the current is slightly larger than the bias current of the error amplifier, and the output of the current subtraction circuit is 0 at the moment, namely I 4 ' =0, current mirror IV replica result I 5 ' =0, inverter INV2 input end IREF 2 High, inverter INV2 outputs logic "0"; the output signals A and B of the inverter INV1 and the inverter INV2 are operated by an XNOR gate to output logic '0', and the RHBd circuit is controlled to work normally.
When the system load current jumps from a heavy load to a light load, the error amplifier outputs a voltage V C Reducing, generating, from the compensation capacitance C C Warp beam M 2 、M 1 Discharge current I to GND tran1 So that the pull-down current is increased, the replica current I of the current mirror I 3 ＝I 1 +I tran1 Reduced amount of current subtracter I 3 Over I bias1 ，I 4 Increase of I 4 ＝I 3 -I bias Current mirror II will I 4 Amplifying by m times to obtain I 5 ＝m I 4 ＝m(I 3 -I bias1 ) And I is 5 At this time greater than I REF1 The input end of the inverter INV1 is pulled high, the inverter INV1 outputs logic '0', the inverter INV2 outputs logic '0', the XNOR gate outputs logic '1', and the RHBd circuit is turned off.
When the system load current jumps from light load to large load, the output voltage V of the error amplifier C Increase, generate from VDD through M 2 ’、M 1 ' to EA compensation capacitance C C Charging current I of tran2 So that the pull-up current is increased, and the replica current I of the current mirror III 3 ’＝I 1 +I tran2 Reduced amount I of current subtracter II 3 ' more than I bias ，I 4 ' increase, I 4 ’＝I 3 ’-I bias Current mirror IV will I 4 ' obtaining I after m times of magnification 5 ’＝mI 4 ’＝m(I 3 ’-I bias ) And I is 5 At this time greater than I REF2 The input end of the inverter INV2 is pulled low, the inverter INV2 outputs logic "1", the inverter 1 outputs logic "1", the XNOR gate outputs logic "1", and the RHBD circuit is turned off.
When the system works normally, the control circuit outputs low level to control the reinforcing circuit to work normally and detect the single event transient effect.
When the system has load transient, if the system jumps from heavy load to light load, the error amplifier generates a voltage signal which is converted by the compensation capacitor C C Warp beam M 2 、M 1 Discharge path to GND, V C Decrease, increase of pull-down current of error amplifier, and current mirrorThe I output current is increased, the I output current of the current subtraction circuit is increased, the II output current of the current mirror is increased, the input end of the inverter INV1 is pulled to a high level, the inverter INV1 outputs logic '0', and after the same or operation, the control circuit outputs the high level to control the closing of the reinforcing circuit and avoid the misoperation of the reinforcing circuit.
When the system has load transient state, if the system jumps from light load to large load, the error amplifier generates VDD via M 2 ’、M 1 To compensation capacitor C C Charging path of, V C And increasing, increasing the pull-up current of the error amplifier, increasing the output current of the current mirror III, increasing the output current of the current subtraction circuit II, increasing the output current of the current mirror IV, pulling the input end of the inverter INV2 to a low level, outputting a logic '1' by the inverter INV2, and controlling the circuit to output a high level after the exclusive OR operation to control the closing of the reinforcing circuit so as to avoid the misoperation of the reinforcing circuit.
Through the mode, the single-particle transient pulse detection and reinforcement circuit of the error amplifier can distinguish the single-particle transient from the load transient, and further avoids misoperation of detecting the load transient as the single-particle transient by the reinforcement circuit.

Claims (8)

1. Be applied to single event transient state reinforcement circuit of DC-DC converter, its characterized in that: comprises an RHBD circuit, wherein the positive end of the RHBD circuit is sequentially connected with a sampling capacitor C S Upper polar plate and sampling switch S 1 Sampling switch S 1 The other end of the buffer is connected to the output end of the analog buffer, the positive input end of the buffer is directly connected to the output node of the error amplifier EA, the output end of the RHBD circuit is directly connected with the output end of the error amplifier EA, the Control circuit collects load transient information from the error amplifier EA, and outputs an EN signal to Control the RHBD circuit.
2. The single-event transient reinforcement circuit applied to the DC-DC converter according to claim 1, wherein: the Control circuit comprises a current mirror I, the current mirror I is connected with a current mirror II, and a current subtraction circuit I is formed between the current mirror I and the current mirror II;
the current mirror III is connected with the current mirror IV, and a current subtraction circuit II is formed between the current mirror III and the current mirror IV;
the current mirror II is connected with a two-input XNOR gate through an inverter INV1 and a current mirror IV through an inverter INV 2.
3. The single-event transient reinforcement circuit applied to the DC-DC converter according to claim 2, wherein: the current mirror I comprises an MOS tube M 1 MOS transistor M 1 Source end of the MOS tube M is grounded, and the MOS tube M is connected with a power supply 1 Drain electrode of and MOS tube M 2 Is connected with the source electrode of the MOS transistor M 2 The drain electrode of (1) is the output node of the error amplifier EA, and the MOS tube M 1 、M 2 A pull-down branch for the output branch of the error amplifier EA, a MOS transistor M 3 MOS transistor M 4 Respectively connected with MOS transistor M 1 MOS tube M 2 Is connected with the grid and is used for copying the current of a pull-down branch circuit, and an MOS tube M 3 Source electrode grounding drain electrode and MOS tube M 4 Is connected to the source of (a).
4. The single-event transient reinforcement circuit applied to the DC-DC converter according to claim 3, wherein: the MOS tube M 3 MOS transistor M 4 The cascode circuit is used as an input signal of the current subtraction circuit I, and the MOS tube M 4 Drain and bias current I bias1 Connected, MOS transistor M 5 MOS tube M 6 The formed cascode stage circuit is used as an output signal of the current subtraction circuit I; MOS transistor M 5 Gate, drain and M 4 Is connected with the drain electrode of the MOS tube M 6 Grid, drain and MOS tube M 5 Is connected with the source electrode of the MOS transistor M 6 The source is connected to VDD.
5. The single-event transient reinforcement circuit applied to the DC-DC converter according to claim 4, wherein: the current mirror II comprises an MOS tube M 7 And MOS transistor M 8 MOS transistor M 7 、M 8 Respectively with MOS transistor M 5 、M 6 Is connected with the grid of the MOS transistor M 8 Source electrode of (2) is connected toVDD, MOS tube M 8 Drain electrode of and MOS tube M 7 Is connected with the source electrode of the MOS transistor M 7 As the output of the current mirror II and the reference current I REF1 And to the input of inverter INV 1.
6. The single-event transient reinforcement circuit applied to the DC-DC converter according to claim 2, wherein: the current mirror III comprises an MOS tube M 1 ' and MOS tube M 2 ', MOS tube M 1 ’、M 2 The output branch of the error amplifier EA is a pull-up branch, and the MOS transistor M is a pull-up branch 2 The source electrode of the transistor is connected with VDD, and the MOS transistor M 2 ' the drain and MOS transistor M 1 ' the source electrodes are connected, and the MOS tube M 1 The drain of the transistor is the output node of the error amplifier EA, and the MOS transistor M 3 ’、M 4 'the grid of' is respectively connected with MOS transistor M 1 ’、M 2 ' the grid electrode is connected and used for duplicating the pull-up branch current, and the MOS tube M 4 The source electrode of the transistor is connected with VDD, the drain electrode is connected with the MOS transistor M 3 The source terminal of' is connected.
7. The single-event transient reinforcement circuit applied to the DC-DC converter of claim 6, wherein: the MOS tube M 3 ’、M 4 ' the formed cascode stage circuit is used as an input signal of the current subtraction circuit II, and the MOS tube M 3 ' Drain and bias Current I bias2 Is connected with the output of the MOS transistor M 5 ', MOS tube M 6 ' the formed cascode stage circuit is used as an output signal of the current subtraction circuit II, and the MOS transistor M 6 ' Gate, drain and M 3 ' the drain electrode of the transistor is connected with the MOS transistor M 5 ' the grid, the drain and the MOS tube M 6 ' the source electrodes are connected, and the MOS tube M 5 The source is grounded.
8. The single-event transient reinforcement circuit applied to the DC-DC converter of claim 7, wherein: the current mirror IV comprises an MOS tube M 7 ’、M 8 ', MOS tube M 7 ’、M 8 'the grid electrode of the' is respectively connected with the MOS transistor M 5 ’、M 6 ' the grid electrodeConnected MOS transistor M 7 ' the source electrode is grounded, the MOS tube M 7 ' the drain electrode and the MOS tube M 8 ' the source electrodes of the transistors are connected, and the MOS transistor M 8 ' the drain of the transistor is used as the output of the current mirror II and the reference current I REF2 Is connected with the input of the inverter INV 2;
the output ends of the inverters INV1 and INV2 are respectively connected with the input ends A and B of the XNOR gate, and the output end of the XNOR gate outputs an EN control signal to control the RHBd circuit.
CN202210948689.5A 2022-08-08 2022-08-08 Single-event transient reinforcing circuit applied to DC-DC converter Pending CN115425962A (en)

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CN202210948689.5A CN115425962A (en) 2022-08-08 2022-08-08 Single-event transient reinforcing circuit applied to DC-DC converter

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