CN115425094A - Perovskite/crystalline silicon tandem solar cell and preparation method thereof - Google Patents

Abstract

The invention discloses a perovskite/crystalline silicon stacked solar cell and a preparation method thereof, which relate to the field of photovoltaic technology. The perovskite/crystalline silicon stacked solar cell includes a top sub-cell and a bottom sub-cell, wherein: according to In the order of incident light, the top sub-cell includes: a top electrode, a window layer, a first carrier transport layer, an absorption layer, and a second carrier transport layer; in accordance with the order of incident light, the bottom sub-cell includes: an upper layer carrying A carrier transport structure, a silicon substrate, a lower carrier transport structure, a bottom passivation layer, and a bottom electrode. The invention reduces the manufacturing process of stacked cells through the improved silicon cell preparation method, thereby meeting the industrial application requirements of perovskite/crystalline silicon stacked solar cells.

Description

Perovskite/crystalline silicon tandem solar cell and preparation method thereof

technical field

The invention relates to the technical field of solar energy, in particular to a perovskite/crystalline silicon stacked solar cell and a preparation method thereof.

Background technique

Photovoltaic cells, or solar cells, are one of the most important technologies driving the renewable energy revolution. Today's research on solar cells has made significant progress in terms of conversion efficiency. However, improving the efficiency of photovoltaic modules is still necessary. Taller photovoltaic modules can make the system more compact, thereby reducing the cost of the system.

In general, it is necessary to reduce absorption losses while maintaining or increasing the voltage of photovoltaic cells. In addition, single-junction solar cells have an efficiency upper limit (Shockley-Queisser limit), and the efficiency of single-junction cells cannot exceed this limit. In view of this, one of the strategies to improve the efficiency of photovoltaic cells is to use tandem cells.

A tandem cell consists of multiple sub-cells composed of materials with different absorption properties, allowing for more efficient utilization of light energy in different wavelengths of the solar spectrum. Tandem cells combine an upper solar cell with a high-efficiency wide bandgap with a lower solar cell with a lower bandgap to increase overall efficiency. The stack allows high-energy photons to be absorbed in the upper sub-cell, which can generate a high voltage to reduce thermalization losses, and allows the lower sub-cell to absorb lower-energy photons (which have been transported through the upper sub-cell), allowing broader energy harvesting.

Silicon solar cells are often used as the bottom cell in stacks due to their bandgap properties. Silicon heterojunction (SHJ) bottom cells currently dominate stack research. In order to develop a stack structure suitable for commercial-scale production, the performance and cost of the bottom cell, as well as its compatibility with subsequent process steps to form the stack structure, are required. For example, heterojunction cells often use double-sided indium tin oxide as the transparent conductive layer, and the distribution of indium in the earth's crust is relatively small and scattered. It is listed as a rare metal, and it will be perovskite/crystalline silicon stack The use of solar cells, the crystalline silicon bottom cell in perovskite/crystalline silicon stacked solar cells will involve the use of indium materials, so it is very necessary to adopt different perovskite/crystalline silicon stacked solar cell solutions.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art. The present invention provides a perovskite/crystalline silicon stacked solar cell and a preparation method thereof, which meets the requirements of the perovskite/crystalline silicon solar cell by reducing the input of indium material for the silicon bottom cell. Application requirements of crystalline silicon tandem solar cells.

In order to solve the above problems, the present invention proposes a perovskite/crystalline silicon tandem solar cell, comprising a top subcell and a bottom subcell, wherein:

According to the order of incident light, the top sub-cell includes: a top electrode, a window layer, a first carrier transport layer, an absorption layer, and a second carrier transport layer;

In the order of incident light, the bottom subcell includes:

Upper transmission structure, silicon substrate, lower transmission structure, bottom passivation layer, bottom electrode;

The upload transmission structure includes: an upper carrier selective transport layer and an upper passivation layer, the upper carrier selective transport layer is doped polysilicon, the upper passivation layer is silicon oxide, and the upper transport structure is POLO structure composed of doped polysilicon and silicon oxide;

The lower transport structure includes: a lower passivation layer and a lower carrier selective transport layer, and the lower transport structure is a POLO structure or a diffused doped layer composed of doped polysilicon and silicon oxide;

The second carrier transport layer includes a titanium oxide material, and the bottom passivation layer includes a titanium oxide material.

The material in the second carrier transport layer includes: one or more of SnO2, TiO2, ZnO, ZrO2, fullerene and derivatives; the bottom passivation layer includes: Al2O3 or TiO2.

The window layer is a transparent conductive layer made of one or more of doped indium oxide, doped zinc oxide and indium zinc oxide, and the thickness of the window layer is in the range of 50-200nm.

The top sub-cell further includes a buffer layer located between the window layer and the first carrier transport layer, and the material of the buffer layer includes MoO ₃ , WO ₃ , V ₂ O ₅ , SnO ₂ , TiO ₂ , one or more of ZnO.

The first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer; or

The second carrier transport layer is an electron transport layer, and the first carrier transport layer is a hole transport layer.

The absorbing layer is composed of a perovskite material, and the perovskite material has a chemical formula expressed as: ABX3, wherein A is a monovalent cation, B is a divalent metal cation, and X is a monovalent halogen or a halogen-like anion; the The thickness of the light absorbing layer is 0.1um-2um.

The silicon substrate is an N-type silicon wafer or a P-type silicon wafer with a resistivity in the range of 0.5-20ohm·cm, the thickness of the silicon substrate is in the range of 100um-300um, and the surface of the silicon substrate is a polished surface or Suede.

When the upper carrier selective transport layer is an n-type doped layer, the lower carrier selective transport layer is a p-type doped layer; when the upper carrier selective transport layer is a p-type doped layer , then the lower carrier selective transport layer is an n-type doped layer.

Correspondingly, the present invention also proposes a method for preparing a perovskite/crystalline silicon stacked solar cell, including a method for preparing a bottom sub-cell and a method for preparing a top sub-cell on the bottom sub-cell and completing the preparation of the stacked cell, The methods include:

Wet processing of silicon substrates;

An upper passivation layer is deposited on the front surface of the silicon substrate, and the upper passivation layer is silicon oxide;

An upper carrier selective transport layer is deposited on the front surface of the upper passivation layer, the upper carrier selective transport layer is doped polysilicon, and the upper carrier selective transport layer and the upper passivation layer are shaped as POLO structure;

Depositing a lower passivation layer on the lower surface of the silicon substrate;

Depositing a lower layer carrier selective transport layer on the lower surface of the lower passivation layer;

ALD technology is used to deposit titanium dioxide on the lower surface of the lower carrier selective transport layer, and form a bottom passivation layer, and at the same time, use ALD technology to deposit titanium dioxide on the upper surface of the upper carrier selective transport layer, and form a second carrier sub-transport layer;

preparing a bottom electrode on the lower surface of the bottom passivation layer;

preparing a perovskite absorption layer on the second carrier transport layer;

preparing a first carrier transport layer on the perovskite absorber layer;

depositing a buffer layer on the first carrier transport layer;

preparing a window layer on the buffer layer;

A metal grid line top electrode is prepared on the window layer.

The lower passivation layer and the lower carrier selective transport layer form a POLO structure; or the lower passivation layer and the lower carrier selective transport layer are formed by a diffused doping layer.

The perovskite/crystalline silicon stacked solar cell and its preparation method in the embodiment of the present invention can reduce the use of indium material by reducing the application of double-sided indium tin oxide as a transparent conductive layer bottom subcell, thereby promoting calcium The use of titanium ore/crystalline silicon stacked solar cells has greatly improved the commercial efficiency and enhanced the absorption capacity of silicon bottom cells. The crystalline silicon bottom cells of this structure are all made of conventional materials, which can reduce the use of precious metal indium materials, reduce the cost of crystalline silicon bottom cells, and also popularize the perovskite/crystalline silicon stacking of crystalline silicon bottom cells. The application in solar cells also makes the subsequent process steps of forming the stacked structure more compatible. Here, by improving the preparation method of silicon cells, the preparation process of stacked cells is reduced, so as to meet the industrial application requirements of perovskite/crystalline silicon stacked solar cells.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the first structure schematic diagram of the perovskite/crystalline silicon laminated solar cell in the embodiment of the present invention;

Fig. 2 is the first schematic structural view of the top sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention;

Fig. 3 is the second structural schematic view of the top sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention;

4 is a schematic diagram of the third structure of the top sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention;

5 is a schematic diagram of the first structure of the bottom sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention;

Fig. 6 is a second structural schematic diagram of the bottom sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention;

7 is a schematic diagram of the third structure of the bottom sub-cell in the perovskite/crystalline silicon tandem solar cell in the example of the present invention;

8 is a schematic diagram of the second structure of the top sub-cell in the perovskite/crystalline silicon tandem solar cell according to the embodiment of the present invention;

9 is a schematic diagram of the third structure of the top sub-cell in the perovskite/crystalline silicon tandem solar cell according to the embodiment of the present invention;

Fig. 10 is a flow chart of a method for preparing a perovskite/crystalline silicon stacked solar cell in an embodiment of the present invention;

Figure 11 is a schematic diagram of the double-sided POLO structure in the embodiment of the present invention;

Fig. 12 is a schematic diagram of the single-sided POLO structure in the embodiment of the present invention;

FIG. 13 is a schematic structural diagram of a semi-finished silicon cell of a double-sided POLO in an embodiment of the present invention;

Fig. 14 is a schematic structural diagram of a semi-finished silicon cell of a double-sided POLO covered with a film in an embodiment of the present invention;

Fig. 15 is a schematic diagram of the silicon cell structure of the double-sided POLO in the embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Specifically, FIG. 1 shows a schematic diagram of the first structure of a perovskite/crystalline silicon tandem solar cell in an embodiment of the present invention, including a top sub-cell and a bottom sub-cell according to the order of incident light.

It should be noted that the perovskite/crystalline silicon tandem solar cell can be directly connected by the top sub-cell and the bottom sub-cell, or can be integrated by connecting the top sub-cell and the bottom sub-cell through an intermediate connection layer.

Specifically, Fig. 2 shows a schematic diagram of the first structure of the top sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention. According to the order of incident light, the top sub-cell includes a top electrode, a window layer, A buffer layer, a first carrier transport layer, an absorption layer, and a second carrier transport layer.

The top electrode here is a grid line structure made of metal or alloy materials. The prepared top electrode can be stacked or mixed with one or more of gold, silver, copper, nickel, chromium, and aluminum. The thickness of the top electrode ranges from 0.5-50um, such as 0.5um, 1um, 2um, 5um, 10um, 20um, 30um, 40un, 50um, etc.

The window layer here is a transparent conductive layer (TCO), and the material includes one or more of doped indium oxide (ITO, IWO, ICO, IZO), doped zinc oxide (AZO) and indium zinc oxide (IZO). The thickness of the window layer is in the range of 50-200nm, such as 50nm, 55nm, 60nm, 65nm, 79nm, 88nm, 99nm, 110nm, 150nm, 180nm, 190nm, 200nm and so on.

The buffer layer here is located between the window layer and the first carrier transport layer, and can be used to protect the bottom layer to prevent film layer damage caused by transparent contact deposition of the window layer by processes such as sputtering. The buffer layer material includes one or more of MoO ₃ , WO ₃ , V ₂ O ₅ , SnO ₂ , TiO ₂ , and ZnO. If the transparent contact deposition of the window layer will not cause film damage, the thickness of the buffer layer can be 0.

It should be noted that the first carrier transport layer and the second carrier transport layer here may be an electron transport layer or a hole transport layer.

It should be noted that the material in the second carrier transport layer includes: one or more of SnO2, TiO2, ZnO, ZrO2, fullerene and derivatives; the bottom passivation layer includes: Al2O3 Or TiO2 and so on.

Specifically, Fig. 3 shows a second schematic structural view of the top subcell in the perovskite/crystalline silicon stacked solar cell in the embodiment of the present invention, the top subcell includes a top electrode, a window layer, a buffer layer, a first Carrier transport layer, absorption layer, second carrier transport layer. That is, the first carrier transport layer here is an electron transport layer, and the second carrier transport layer is a hole transport layer.

Specifically, FIG. 4 shows a schematic diagram of the third structure of the top subcell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention. The top subcell includes a top electrode, a window layer, a buffer layer, a first Carrier transport layer, absorption layer, second carrier transport layer. That is, the second carrier transport layer here is an electron transport layer, and the first carrier transport layer is a hole transport layer.

It should be noted that the material of the hole transport layer is PTAA, NiO _x , TaTm, D18, P3HT, V ₂ O ₅ , MoO _x , PEDOT:PSS, WO _x , Sprio-OMeTAD, CuSCN, Cu ₂ O, CuI, Spiro -One or more of TTB, F4-TCNQ, F6-TCNNQ, m-MTDATA, 2PACz, meo-2PACz, 4PACz or TAPC, the thickness of the hole transport layer is 0-100nm, which can be 1nm, 2nm, 10nm, 20nm, 30nm, 50nm, 70nm, 100nm, etc.

It should be noted that the electron transport layer material is one or more of SnO ₂ , TiO ₂ , ZnO, ZrO ₂ , fullerene and its derivatives (C60, C70, PCBM), with a thickness of 0-500nm, which can be The values are 1nm, 2nm, 10nm, 20nm, 30nm, 50nm, 70nm, 100nm, 200nm, 300nm, 400nm, 500nm and so on.

It should be noted that the absorbing layer is composed of perovskite materials, which can be expressed by the following chemical formula: ABX3, where A is a monovalent cation, including but not limited to methylammonium (MA), formamidine (FA), cesium (Cs), or rubidium (Rb) or any combination thereof; B is a divalent metal cation, including but not limited to lead (Pb), tin (Sn), tungsten (W), copper (Cu), zinc (Zn), Gallium (Ga) or any combination thereof; X is a monovalent halogen or halide-like anion, including but not limited to iodine (I), bromine (Br), chlorine (Cl), thiocyanate (SCN) or any combination thereof. The thickness of the light absorbing layer is 0.1um-2um, which can be 0.1um, 0.5um, 1um, 1.5um, 2um and so on.

It should be noted that the ratio of bromine (Br): iodine (I) in the absorbing layer is in the range of 0:1 to 1:1. A includes one or more monovalent cations, and the selection method is that the molar percentage of A is: formamidine (FA) from 0% to 100%; methylammonium (MA) from 0% to 100%; cesium (Cs) from 0% to 100%. % to 30%; rubidium (Rb) from 0% to 30%.

Specifically, Fig. 5 shows a schematic diagram of the first structure of the bottom sub-cell in the perovskite/crystalline silicon tandem solar cell in the embodiment of the present invention. According to the order of incident light, the bottom sub-cell includes: an upper layer transmission structure, a silicon substrate Bottom, bottom layer transfer structure, bottom passivation layer, bottom electrode. The upload transmission structure includes: an upper carrier selective transport layer and an upper passivation layer, the upper transport structure is a POLO structure composed of doped polysilicon and silicon oxide; the lower transport structure includes: a lower passivation layer and a lower passivation layer The carrier selects the transport layer, and the transport structure of the lower layer is a POLO structure composed of doped polysilicon and silicon oxide or a diffused doped layer.

The metal bottom electrode layer can be a full-coverage structure or a grid line structure, as shown in Figure 5, which is a metal bottom electrode layer with a full-coverage structure, and the metal bottom electrode layer can also refer to the gate line structure shown in Figures 1 to 4. Line structure molding. The material of the metal bottom electrode layer includes one or more of gold, silver, copper, nickel, chromium, aluminum stacked or mixed, and the thickness range is 0.5-50um.

The silicon substrate is an N-type silicon wafer or a P-type silicon wafer with a resistivity range of 0.5-20ohm·cm, and a thickness range of 100um-300um. The shape of the bottom sub-cell is determined by the silicon substrate. The surface of the silicon substrate is a polished surface or a textured surface, and the undulation range of the textured surface should be within 2um.

The upper carrier selective transport layer is a doped polysilicon layer (poly-Si), and the upper passivation layer is a silicon oxide layer (SiOx), where the upper carrier selective transport layer and the upper passivation layer Shaped into a POLO structure, that is, a POLO (Poly-sion Oxide) structure.

Here the upper carrier selective transport layer is an n-type doped layer, then the lower carrier selective transport layer is a p-type doped layer; the upper carrier selective transport layer is a p-type doped layer, then the lower carrier selective transport layer The selective transport layer is an n-type doped layer.

Specifically, FIG. 6 shows a schematic diagram of the second structure of the bottom subcell in the perovskite/crystalline silicon stacked solar cell in the embodiment of the present invention, where the upper carrier selective transport layer is an n-type doped layer, Here, the lower carrier selective transport layer is a p-type doped layer.

Specifically, FIG. 7 shows a schematic diagram of the third structure of the bottom subcell in the perovskite/crystalline silicon stacked solar cell in the example of the present invention, where the upper carrier selective transport layer is a p-type doped layer, where The lower carrier selective transport layer is an n-type doped layer.

The bottom passivation layer is configured to inhibit metal diffusion from the bottom electrode to the inner layer, the bottom passivation layer includes a material selected from the group consisting of transition metal oxides, metal halides, transparent conductive oxides, and metal nitrides. The bottom passivation layer may include transition metal oxides selected from the following group, such as: TiO ₂ , Ta ₂ O ₃ and Ga ₂ O ₃ , LiF, MgF ₂ , TiN, TaN, etc. alone or in combination.

The material used for the upper passivation layer and the upper passivation layer is: a silicon oxide layer (SiOx), and the upper passivation layer and the upper passivation layer are formed by thermal oxygen, or LPCVD, or PECVD.

The perovskite/crystalline silicon stacked solar cell structure in the embodiment of the present invention is connected by the top sub-cell and the bottom sub-cell, and the second carrier transport layer in the top sub-cell is connected to the upper carrier transport layer in the bottom sub-cell. Layers are connected, and the connection method can be connected through an intermediate connection layer or directly.

Specifically, FIG. 8 shows a schematic diagram of the second structure of the top subcell in the perovskite/crystalline silicon tandem solar cell according to the embodiment of the present invention, including: the top electrode is also the top electrode, the transparent window layer is also the window layer, The buffer protection layer is buffer layer, hole transport layer, absorption layer, electron transport layer, intermediate interconnection layer (optional), P-type doped layer, upper passivation layer, silicon substrate, lower passivation layer, N Type doped layer, bottom passivation layer, bottom electrode layer, also known as bottom electrode, etc. Here the second carrier transport layer is an electron transport layer, the first carrier transport layer is a hole transport layer, the upper carrier selective transport layer is a P-type doped layer, and the lower carrier selective transport layer is N-type doped layer.

Specifically, FIG. 9 shows a schematic diagram of the third structure of the top sub-cell in the perovskite/crystalline silicon tandem solar cell according to the embodiment of the present invention, including: the top electrode, that is, the top electrode, the transparent window layer, that is, the window layer, The buffer protection layer is buffer layer, electron transport layer, absorption layer, hole transport layer, intermediate interconnection layer (optional), N-type doped layer, upper passivation layer, silicon substrate, lower passivation layer, P Type doped layer, bottom passivation layer, bottom electrode layer, also known as bottom electrode, etc. Here the first carrier transport layer is an electron transport layer, the second carrier transport layer is a hole transport layer, the upper carrier selective transport layer is an N-type doped layer, and the lower carrier selective transport layer is P-type doped layer.

In the embodiment of the present invention, use simultaneous ALD technology to deposit TiO2 to form the passivation layer at the bottom of the second carrier transport layer, so that the titanium oxide on the front side can be used as all or part of the second carrier transport layer, and the titanium oxide on the back side That is, it can be used as the bottom passivation layer, which simplifies the manufacturing process of laminated batteries and greatly improves the efficiency of the manufacturing process. The method for preparing a perovskite/crystalline silicon stacked solar cell involved in the embodiment of the present invention includes a method for preparing a bottom sub-cell and a method for preparing a top sub-cell on the bottom sub-cell to complete the preparation of the stacked cell.

Specifically, FIG. 10 shows a flow chart of a method for preparing a perovskite/crystalline silicon stacked solar cell in an embodiment of the present invention, which includes the following steps:

S101, providing a silicon substrate to form the silicon substrate;

S102, performing wet processing on the silicon substrate;

Wet treatment is carried out here to ensure that the front surface of the silicon substrate is a polished surface or a textured surface with a fluctuation range less than 2um.

S103, depositing an upper passivation layer on the front surface of the silicon substrate;

The upper passivation layer is a silicon oxide layer (SiOx), and its preparation methods include but not limited to thermal oxygen, LPCVD, and PECVD methods.

S104, depositing an upper carrier selective transport layer on the front surface of the upper passivation layer;

The method for depositing the upper carrier selective transport layer includes: polysilicon layer (poly-Si) deposition and element doping, phosphorus (P) element doping is used for N-type doping, and boron (B) is used for P-type doping. ) element doping, including but not limited to LPCVD+ion implantation, LPCVD+thermal diffusion, LPCVD in-situ doping, PECVD in-situ doping methods.

S105, depositing a lower passivation layer on the lower surface of the silicon substrate;

The lower passivation layer is a silicon oxide layer (SiOx), and the preparation methods of the lower passivation layer include but not limited to thermal oxygen, LPCVD, and PECVD methods.

S106, depositing a lower carrier selective transport layer on the lower surface of the lower passivation layer;

The method for depositing the carrier selection transport layer of the lower layer includes: polysilicon layer (poly-Si) deposition and element doping, phosphorus (P) element doping is used for N-type doping, and boron (B) is used for P-type doping. ) element doping, including but not limited to LPCVD+ion implantation, LPCVD+thermal diffusion, LPCVD in-situ doping, PECVD in-situ doping methods.

S107, using ALD technology to deposit titanium dioxide;

Here, ALD technology is used to deposit titanium dioxide on the lower surface of the lower carrier selective transport layer to form a bottom passivation layer, and at the same time, ALD technology is used to deposit titanium dioxide on the upper surface of the upper carrier selective transport layer to form a second carrier layer. stream transport layer.

That is, the bottom passivation layer is deposited on the lower surface of the lower carrier selective transport layer. The material of the bottom passivation layer can be one or more of SiO _x , Al ₂ O ₃ , AlN, InSb, SiC, TiOx, TiN, The passivation layer can be a single layer, or a stack of dielectric layers, such as SiO _x /AlO _x , with a thickness of 0-300 nm.

The bottom passivation layer here can be formed by ALD.

S108, preparing a bottom electrode on the lower surface of the bottom passivation layer;

Here, but not limited to evaporation, printing or electroplating methods are used to prepare metal grid line bottom electrodes or fully covered bottom electrodes on the bottom passivation layer. Steps S101 to S109 are to complete the bottom sub-electrode preparation process.

The bottom electrode can be Al back electrode, which can avoid the loss of silver, but not limited to aluminum or silver.

It should be noted that the upper carrier selective transport layer and the upper passivation layer here are doped polysilicon and silicon oxide, which form a POLO structure (poly-Si/SiOx), and the lower passivation layer and The lower carrier selective transport layer forms a POLO structure or a silicon heterojunction structure; or the lower passivation layer and the lower carrier selective transport layer are formed from a diffuse doped layer. As shown in Figure 11, the upper carrier selective transport layer is an n-type doped polysilicon layer, the upper passivation layer is an upper tunneling silicon oxide layer, which forms a POLO structure, and the lower carrier selective transport layer is a p-type Doped polysilicon layer, the lower passivation layer is the lower tunneling silicon oxide layer, which forms a POLO structure; as shown in Figure 12, the upper carrier selective transport layer here is an N-type doped polysilicon layer, and the upper passivation layer is The upper tunneling silicon oxide layer forms a POLO structure, and the lower carrier selective transport layer and lower passivation layer are formed by a P-type diffusion doping layer.

Based on the double-sided POLO structure shown in Figure 11, Figure 13 shows a schematic diagram of the semi-finished silicon cell structure of the double-sided POLO in the embodiment of the present invention, which involves poly-Si(n+), SiOx, SiOx, poly-Si(p+ ), etc., there are carrier selective transport layers on the front and back sides, and the titanium oxide layer TiO2 can be prepared by the ALD process without preparing the intermediate tunnel connection layer, that is, the intermediate connection layer. Due to the characteristics of ALD, it can be simultaneously Film layers are formed on both the front and back sides of the silicon wafer, so as to realize the combination of the silicon preparation process and the lamination process, and simplify the lamination cell process preparation process.

Specifically, FIG. 14 shows a schematic diagram of the semi-finished silicon cell structure of the coated double-sided POLO in the embodiment of the present invention, which involves TiOx, poly-Si(n+), SiOx, SiOx, poly-Si(p+), TiOx, etc., here the bottom titanium oxide layer can be used as the bottom passivation layer of the silicon bottom cell, and the top layer of titanium oxide can be used as part of the second carrier transport layer (carrier transport layer) of the top perovskite The sub-transport layer can be one or more layers), where the poly-Si/SiOx and TiOx form a tunneling contact, which can perfectly avoid the use of the TCO tunneling layer, simplify the entire stacked cell structure, and improve The finished product processing efficiency.

The method for preparing the top sub-cell on the bottom sub-cell and completing the preparation of the laminated battery is described below, which specifically involves S109 to S113.

S109, preparing a perovskite absorption layer on the second carrier transport layer;

In the specific implementation process, the perovskite is prepared on the second carrier transport layer by using but not limited to spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, scrape coating, printing, inkjet printing or slit coating absorbent layer.

S110, preparing a first carrier transport layer on the perovskite absorption layer;

In the specific implementation process, the first carrier is prepared on the perovskite absorbing layer by using but not limited to spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, scraping coating, printing, inkjet printing or slit coating method transport layer.

S111, depositing a buffer layer on the first carrier transport layer;

During the specific implementation process, the buffer layer is deposited on the first carrier transport layer by using but not limited to sputtering, atomic deposition (ALD) or evaporation method.

S112. Prepare a window layer on the buffer layer;

During the specific implementation process, the window layer is prepared on the buffer layer by using but not limited to sputtering, atomic deposition (ALD) or evaporation method.

S113 , preparing a top electrode of a metal grid line on the window layer.

In the specific implementation process, the metal grid wire top electrode is prepared on the window layer by using but not limited to evaporation, printing or electroplating methods, so as to complete the preparation of the laminated solar cell.

Combining the descriptions in Figures 11 to 14, the schematic diagram of the silicon cell structure of the double-sided POLO is shown in Figure 15.

The perovskite/crystalline silicon stacked solar cell and its preparation method in the embodiment of the present invention can reduce the use of indium material by reducing the application of double-sided indium tin oxide as a transparent conductive layer bottom subcell, thereby promoting calcium The use of titanium ore/crystalline silicon stacked solar cells has greatly improved the commercial efficiency and enhanced the absorption capacity of silicon bottom cells. The crystalline silicon bottom cells of this structure are all made of conventional materials, which can reduce the use of precious metal indium materials, reduce the cost of crystalline silicon bottom cells, and also popularize the perovskite/crystalline silicon stacking of crystalline silicon bottom cells. The application in solar cells also makes the subsequent process steps of forming the stacked structure more compatible. Here, by improving the preparation method of silicon cells, the preparation process of stacked cells is reduced, so as to meet the industrial application requirements of perovskite/crystalline silicon stacked solar cells.

The embodiments of the present invention have been described in detail above, and specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only used to help understand the method of the present invention and its core idea; at the same time, for Those skilled in the art will have changes in the specific implementation and scope of application according to the idea of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (10)

1. A perovskite/crystalline silicon laminated solar cell, characterized in that it comprises a top subcell and a bottom subcell, wherein: According to the order of incident light, the top sub-cell includes: a top electrode, a window layer, a first carrier transport layer, an absorption layer, and a second carrier transport layer; According to the order of incident light, the bottom sub-cell includes: an upper layer transmission structure, a silicon substrate, a lower layer transmission structure, a bottom passivation layer, and a bottom electrode; The upload transmission structure includes: an upper carrier selective transport layer and an upper passivation layer, the upper carrier selective transport layer is doped polysilicon, the upper passivation layer is silicon oxide, and the upper transport structure is POLO structure composed of doped polysilicon and silicon oxide; The lower transport structure includes: a lower passivation layer and a lower carrier selective transport layer, and the lower transport structure is a POLO structure or a diffused doped layer composed of doped polysilicon and silicon oxide; The second carrier transport layer includes a titanium oxide material, and the bottom passivation layer includes a titanium oxide material. 2. The perovskite/crystalline silicon laminated solar cell as claimed in claim 1, wherein the material in the second carrier transport layer comprises: SnO2, TiO2, ZnO, ZrO2, fullerene and One or more of the derivatives; the bottom passivation layer includes: Al2O3 or TiO2. 3. The perovskite/crystalline silicon stacked solar cell according to claim 1, wherein the window layer is a transparent conductive layer, and the material includes doped indium oxide, doped zinc oxide and indium zinc oxide. One or several types are stacked, and the thickness of the window layer is in the range of 50-200nm. 4. The perovskite/crystalline silicon tandem solar cell according to claim 1, wherein the top sub-cell further comprises a buffer layer, and the buffer layer is located between the window layer and the first carrier transport layer Meanwhile, the buffer layer material includes one or more of MoO ₃ , WO ₃ , V ₂ O ₅ , SnO ₂ , TiO ₂ , and ZnO. 5. The perovskite/crystalline silicon stacked solar cell as claimed in claim 1, characterized in that, The second carrier transport layer is an electron transport layer, and the first carrier transport layer is a hole transport layer. 6. The perovskite/crystalline silicon stacked solar cell as claimed in claim 1, wherein the absorber layer is composed of a perovskite material, and the perovskite material has a chemical formula expressed as: ABX3, wherein A is a monovalent cation, B is a divalent metal cation, and X is a monovalent halogen or a halogen-like anion; the thickness of the light-absorbing layer is 0.1um-2um. 7. The perovskite/crystalline silicon tandem solar cell according to any one of claims 1 to 6, wherein the silicon substrate is an N-type silicon wafer or For a P-type silicon wafer, the thickness of the silicon substrate ranges from 100um to 300um, and the surface of the silicon substrate is a polished surface or a textured surface. 8. The perovskite/crystalline silicon stacked solar cell according to claim 7, wherein when the upper carrier selective transport layer is an n-type doped layer, the lower carrier selective transport layer is a p-type doped layer; when the upper carrier selective transport layer is a p-type doped layer, the lower carrier selective transport layer is an n-type doped layer. 9. A method for preparing a perovskite/crystalline silicon stacked solar cell, comprising a method for preparing a bottom subcell and a method for preparing a top subcell on the bottom subcell and completing the preparation of a stacked cell, characterized in that the Methods include: Wet processing of silicon substrates; An upper passivation layer is deposited on the front surface of the silicon substrate, and the upper passivation layer is silicon oxide; An upper carrier selective transport layer is deposited on the front surface of the upper passivation layer, the upper carrier selective transport layer is doped polysilicon, and the upper carrier selective transport layer and the upper passivation layer are shaped as POLO structure; Depositing a lower passivation layer on the lower surface of the silicon substrate; Depositing a lower carrier selective transport layer on the lower surface of the lower passivation layer; ALD technology is used to deposit titanium dioxide on the lower surface of the lower carrier selective transport layer, and form a bottom passivation layer, and at the same time, use ALD technology to deposit titanium dioxide on the upper surface of the upper carrier selective transport layer, and form a second carrier sub-transport layer; preparing a bottom electrode on the lower surface of the bottom passivation layer; preparing a perovskite absorption layer on the second carrier transport layer; preparing a first carrier transport layer on the perovskite absorber layer; depositing a buffer layer on the first carrier transport layer; preparing a window layer on the buffer layer; A metal grid line top electrode is prepared on the window layer. 10. the preparation method of perovskite/crystalline silicon laminated solar cell as claimed in claim 9 is characterized in that, described lower layer passivation layer and lower layer carrier selective transport layer have formed POLO structure; The mixed layer forms the lower passivation layer and the lower carrier selective transport layer.

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