CN115411099B - Preparation method of pure platinum barrier Schottky diode - Google Patents
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- CN115411099B CN115411099B CN202211189058.6A CN202211189058A CN115411099B CN 115411099 B CN115411099 B CN 115411099B CN 202211189058 A CN202211189058 A CN 202211189058A CN 115411099 B CN115411099 B CN 115411099B
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 title claims abstract description 92
- 230000004888 barrier function Effects 0.000 title claims abstract description 48
- 229910052697 platinum Inorganic materials 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 65
- 239000010703 silicon Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 17
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 15
- 239000011733 molybdenum Substances 0.000 claims abstract description 15
- 229910052786 argon Inorganic materials 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 13
- -1 argon ions Chemical class 0.000 claims abstract description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 230000007547 defect Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 238000009740 moulding (composite fabrication) Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 84
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000004544 sputter deposition Methods 0.000 claims description 12
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 12
- 238000005245 sintering Methods 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910001080 W alloy Inorganic materials 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000011265 semifinished product Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- XRZCZVQJHOCRCR-UHFFFAOYSA-N [Si].[Pt] Chemical compound [Si].[Pt] XRZCZVQJHOCRCR-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000717 platinum sputter deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A preparation method of a pure platinum barrier Schottky diode comprises the steps of firstly depositing a layer of platinum metal on a molybdenum large disc, then placing a silicon wafer on the molybdenum large disc, bombarding the surface of the silicon wafer by high-purity argon ions, removing a natural oxide layer on the surface of the silicon wafer, bombarding the large disc outside the silicon wafer by the argon ions, and depositing the platinum metal on the large disc on the surface of the silicon wafer after bombardment; and then depositing a TiW layer on the surface of the silicon slice platinum layer. Preparing a pure platinum barrier Schottky diode after depositing a TiW layer silicon wafer, wherein an n+ monocrystalline silicon substrate is used as a substrate sheet; an n+ monocrystalline silicon substrate produces an n-epitaxial layer; forming PN junction by zone oxidation and ion implantation, and forming passivation layer by field oxidation; photoetching and etching the epitaxial layer exposing Si; the preparation of the schottky barrier front surface cleaning ensures that the surface of the silicon wafer is sufficiently clean and the surface of the silicon wafer without process defects is exposed.
Description
Technical Field
The invention relates to the field of semiconductor chips, in particular to a Schottky diode pure platinum barrier process method.
Background
Schottky diodes are widely used in power management due to their relatively low turn-on voltage (low forward voltage drop) and relatively fast switching time, commonly found in switching power supplies and high frequency applications. Typical schottky diodes generally employ low barrier height metals (e.g., titanium (Ti), nickel (Ni), chromium (Cr), etc.), or high barrier height metals (e.g., platinum (Pt), etc.) to form contacts on N-type silicon. In many applications, low barrier height metal schottky diodes have lower forward voltage drops and greater reverse leakage currents than high barrier height metal schottky diodes. In some applications, however, it is desirable for the schottky diode to maintain schottky low forward voltage drop performance while having relatively little reverse leakage current. The rectifying performance (forward voltage drop and reverse leakage) of the schottky diode is mainly determined by schottky barrier metal, and when the metal is in close contact with silicon, a barrier is formed, the barrier height is Φb, and different Φb generate different rectifying characteristics. The higher the value of Φb, the lower the reverse leakage current. For low reverse leakage current applications, a barrier metal material of high Φb is required. Φb of platinum barrier: 0.80-0.90eV, which is the highest material of PhiB in metal materials, is also widely used in semiconductor manufacturing. How to form a good platinum silicide barrier is the subject of the main study herein. In general, schottky barriers formed of noble metals such as titanium, platinum, and palladium have stability and reproducibility.
The western microelectronics institute 202110287682.9 discloses a schottky diode of a NiPt15 alloy and a preparation method thereof, the preparation method comprises the steps of sequentially preparing an epitaxial layer, a p+ ring, a schottky barrier layer, an aluminum alloy layer and a positive electrode conductive layer on a substrate, and preparing a negative electrode conductive layer on the lower surface of the substrate. Because the NiPt15 alloy is adopted to infiltrate into the epitaxial layer of the first conductivity type to form a Schottky barrier layer, the generated metal silicide comprises nickel silicon and platinum silicon components, so that good Schottky contact can be formed, and the addition of platinum metal can improve the thermal stability of the nickel silicon film.
The traditional platinum barrier technology is to deposit a layer of platinum on the surface of N <111> silicon, then sinter (anneal) the silicon by a furnace tube to form platinum silicide, the reaction rate of platinum and silicon is fast, the temperature and time of sintering (anneal) are very tightly controlled, the uniformity in the sheet or batch is easy to be bad, the phenomenon of bad repeatability of the technology is caused, the main bad is that the reverse leakage of the Schottky product is large, and the deviation of the leakage is large. By adopting the process researched in the invention, a process method capable of repeatedly producing is found for manufacturing the Schottky diode.
Disclosure of Invention
Aiming at the problems in the prior art, the technical problem to be solved by the invention is to provide a pure platinum barrier process of a Schottky diode, so as to realize the process repeatability, and the process is suitable for a wider furnace tube sintering (annealing) process. The reverse leakage rate of the product is reduced, and the stability is good.
The invention aims at realizing the following technical scheme that a layer of platinum metal is deposited on a molybdenum large disc, then a silicon wafer is placed on the molybdenum large disc, the surface of the silicon wafer is bombarded by high-purity argon ions, the natural oxide layer on the surface of the silicon wafer is removed, meanwhile, the large disc outside the silicon wafer is bombarded by the argon ions, and the platinum metal on the large disc is deposited on the surface of the silicon wafer after being bombarded by the argon ions, so that a thin platinum layer with good uniformity can be formed on the surface of the silicon wafer; then depositing a TiW layer on the surface of the platinum layer of the (semi-finished product) silicon wafer; a further platinum layer may be deposited on the TiW layer, which provides a good starting point for the next run. Wherein the TiW layer is used for blocking the diffusion of the front metal to the barrier layer and protecting the characteristic of the Schottky barrier.
Wherein the sputtering process uses the main materials: the weight ratio of tungsten to titanium in the titanium-tungsten alloy target was 9:1, and the purity was 99.99%. The purity of the platinum target material metal is 99.99%, and the purity of the argon gas is 99.999%, which are all high-purity materials.
The platinum metal on the large disc is bombarded and then deposited to the surface of the silicon wafer below 10 nm; sputtering a layer of barrier protection layer TiW20nm, and sputtering a layer of platinum layer 20-60nm. The (semi-finished) silicon wafer is prepared in the following way, wherein the substrate slice can be an n+ monocrystalline silicon substrate; producing an n-epitaxial layer by using an n+ monocrystalline silicon substrate; forming PN junction by zone oxidation and ion implantation, and forming passivation layer by field oxidation; photoetching and etching to expose the epitaxial layer of Si (namely a Schottky hole region); surface cleaning before Schottky barrier ensures that the surface of the silicon wafer is sufficiently clean and the surface of the (semi-finished product) silicon wafer without process defects is exposed;
Preparing a pure platinum barrier Schottky diode after depositing a TiW layer silicon wafer, wherein an n+ monocrystalline silicon substrate can be selected as a substrate sheet; producing an n-epitaxial layer by using an n+ monocrystalline silicon substrate; forming PN junction by zone oxidation and ion implantation, and forming passivation layer by field oxidation; photoetching and etching the epitaxial layer exposing Si; the preparation of the schottky barrier front surface cleaning ensures that the surface of the silicon wafer is sufficiently clean and the surface of the silicon wafer without process defects is exposed.
The prepared device comprises an n+ substrate layer 1, an n-epitaxial layer 2, a pn junction 3, an oxidation layer 4, a Schottky barrier layer 5, a titanium tungsten layer 6, a front metal 7 and a back metal 8, wherein the front metal 7, the titanium tungsten layer 6, the Schottky barrier layer 5, the n-epitaxial layer 2, the n+ substrate layer 1, the back metal 8, the chip, the oxidation layer 4 and the front metal 7 are sequentially arranged from top to bottom, and the chip is sequentially arranged from right to left. The schottky barrier layer 5 is a conventional schottky junction.
Compared with the prior art, the invention has the advantages that:
(1) The chip has a simple structure, is divided into three layers from right to left, is easy to manufacture, has good adaptability and high compatibility;
(2) The formation of the barrier is most important in the overall schottky manufacturing process. Since schottky diodes are a surface effect device, cleaning of the silicon surface is critical. Any remaining photoresist and other contaminants can severely impact the formation of the schottky barrier. Special care must be taken to ensure that the silicon surface is clean. Prior to deposition, the wafer is subjected to an argon + reverse sputter clean to remove any residual oxide that may affect silicide formation. The repeatability of production is realized, and the uniformity among batches is ensured;
(3) The platinum barrier is manufactured by a (magnetron) sputtering process, the thickness is more than 60nm, special manufacturing process and equipment are not required to be introduced, and the manufacturability of the product and the compatibility of the process are improved.
(4) 8 Pieces of sputtering can be operated for one time, and a platinum sputtering layer provides a good starting point for the next operation in the sputtering process, so that the cost is reduced;
(5) The sintering (annealing) window range of the furnace tube is wide and is 400-500 ℃ for 20-60min, the process adaptability is strong, and the repeatability production is easy to realize.
Drawings
Fig. 1 is a schematic cross-sectional view of a schottky barrier diode of the present invention;
FIG. 2 is a schematic diagram of a molybdenum large disk 13 (deposited onto the molybdenum large disk after platinum bombardment) and silicon wafer preparation according to the present invention;
fig. 3 is a graph of the process of the present invention versus the prior art (parameter comparison of the finished product).
Detailed Description
The invention will now be described in detail with reference to the drawings and the accompanying specific examples.
In fig. 1, the device comprises an n+ substrate layer 1, an n-epitaxial layer 2, a pn junction 3, a passivation layer 4, a schottky barrier layer 5, a titanium tungsten layer 6, a front metal 7 and a back metal 8, wherein the chip capturing is sequentially from top to bottom, the front metal 7, the titanium tungsten layer 6, the schottky barrier layer 5, the n-epitaxial layer 2, the n+ substrate layer 1, the back metal 8, the chip capturing is sequentially from right to left, the passivation layer 4 and the front metal 7.
As shown in fig. 2, a molybdenum large disc 13 (which is deposited on the molybdenum large disc after the bombardment of platinum metal) is provided with a round hole 11 for loading and unloading the silicon wafer and a silicon wafer 12.
Firstly, depositing a layer of platinum metal on a molybdenum large disc, then placing a silicon wafer on the molybdenum large disc, bombarding (semi-finished product) the surface of the silicon wafer by high-purity argon ions, removing a natural oxide layer on the surface of the silicon wafer, bombarding the large disc outside the silicon wafer by the argon ions, and depositing the platinum metal on the molybdenum large disc on the surface of the silicon wafer after bombarding, so that a thin platinum layer with good uniformity can be formed on the surface of the silicon wafer; then depositing a TiW layer on the surface of the platinum layer of the (semi-finished product) silicon wafer; a platinum layer may be deposited over the TiW layer.
The development of the platinum barrier process for manufacturing the schottky diode comprises the following steps:
1. A substrate sheet: n+ single crystal silicon substrate 1, resistivity of n+ substrate < = 0.005ohm-cm, thickness is 300-625um.
2. Epitaxial wafer: producing an n-epitaxial layer 2 in an n+ monocrystalline silicon substrate region, wherein the thickness of the n-epitaxial layer is 2-30 mu m, and the resistivity of the n-epitaxial layer is 0.3-30.0 ohm.
3. Oxidizing, ion implanting to form PN junction 3, field oxidizing to form passivation layer 4
4. Etching the exposed Si epitaxial layer (i.e., schottky hole region);
5. Surface cleaning before schottky barrier: the cleaning adopts the 1# liquid, the 2# liquid and the HF which are commonly used in the industry to clean the surface of the silicon wafer after the treatment of the previous step, so that the surface of the silicon wafer is sufficiently clean and the silicon with no process defects on the surface is exposed;
6. Schottky barrier formation: and depositing a layer of platinum film on the molybdenum large disc by a magnetron sputtering instrument, wherein the thickness of the platinum film is 50nm. Then, the silicon wafer processed in the step 5 is loaded on a molybdenum large disc with a platinum film (50 nm) deposited on the surface, as shown in fig. 2, and is cleaned by argon + reverse sputtering under high vacuum, so as to remove the natural oxide layer on the silicon surface, and simultaneously, the platinum layer on the large disc is sputtered on the silicon wafer to form a very thin platinum film, the platinum film is 5nm, then a barrier protective layer TiW (20 nm) is sputtered, and then a platinum layer (50 nm) is sputtered, thus forming the Schottky barrier layer 5.
7. Metal photoetching, corrosion and photoresist removal: and (3) performing metal photoetching, then respectively corroding platinum and TiW by using aqua regia and H2O2 metal, and removing the photoresist after corrosion is finished.
8. Sintering and alloying: the silicon wafer after the step 7 is put into a furnace tube for sintering, and is used for forming metal silicide, wherein the sintering temperature is 400-500 ℃, the sintering time is 20-60mins, and the gas is N2;
9. Sputtering titanium tungsten: sputtering a titanium tungsten layer on the silicon wafer processed in the step 12 by using a magnetron sputtering instrument, wherein the thickness of the titanium tungsten is 0.1um-0.3um, and the titanium tungsten layer is used for protecting metal silicide at the bottom to form a titanium tungsten layer 6;
10. and (3) metallization: different front metals such as TiAl or TiNiAg can be evaporated according to different requirements, and the front metal 7 is formed by metal photoetching and metal corrosion and photoresist removal;
11. Annealing: placing the silicon wafer treated in the step 10 into an annealing furnace tube for eliminating stress among all layers of metal, wherein the temperature of the annealing furnace tube is 400-500 ℃, the time is more than 20min, and N2, N2/H2 or vacuum can be used;
12. Back thinning: the silicon wafer obtained in the step 11 is subjected to chemical mechanical polishing, the thickness of the silicon wafer is thinned to 260um from the back, back silicon corrosion is carried out, the mechanical capacity of the thinning procedure is released, the silicon damage layer on the surface is removed, and the back thinning and silicon corrosion processes are adopted, so that the forward on-resistance of the diode is reduced, the on-state performance of the diode is improved, and the reliability of the diode is improved;
13. Evaporating the backside metal: and (3) carrying out electron beam evaporation on the back surface of the silicon wafer obtained by the treatment in the step (12), and depositing back metal on the silicon wafer to form back metal 8. The back is silver, so that a back electrode is formed, and the silver has good conductivity, so that the chip has better conductivity and lower power consumption; table 1 shows the comparison of the reverse leakage uniformity of the new process and the conventional process (taking 70mil/200V,25 degree test data as an example)
Fig. 3 shows a graph of the process of the present invention compared to the prior art (parameter comparison of the finished product, mainly leakage parameters). The leakage deviation value of the new platinum process can be intuitively seen to be small, so that the stability of the new process is demonstrated, the repeatability is good, and the method is more suitable for large-scale production.
The invention and its embodiments have been described above schematically, without limitation, and the actual construction is not limited to this, but is shown in the drawings as one of its embodiments. Therefore, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical scheme are not creatively designed without departing from the gist of the present invention.
Claims (3)
1. A preparation method of a pure platinum barrier Schottky diode is characterized in that a layer of platinum metal is deposited on a molybdenum big disc, then a silicon wafer is placed on the molybdenum big disc, the surface of the silicon wafer is bombarded by high-purity argon ions, meanwhile, the big disc outside the silicon wafer is bombarded by the argon ions, a natural oxide layer on the surface of the silicon is removed, and the platinum metal on the big disc is deposited below 10 nm on the surface of the silicon wafer after bombarded; sputtering a layer of barrier protective layer TiW20nm, and sputtering a layer of platinum layer 20-60nm; and forming a Schottky barrier layer, sintering the silicon wafer in a furnace tube to form metal silicide, and finally forming a titanium tungsten layer and front metal.
2. The method for fabricating a pure platinum barrier schottky diode according to claim 1, wherein the sputtering process uses a main material: the weight ratio of tungsten to titanium in the titanium-tungsten alloy target is 9:1, and the purity is 99.99%; the purity of the platinum target metal was 99.99% and the purity of the argon was 99.999%.
3. The method for preparing the pure platinum barrier Schottky diode according to any one of claims 1-2, wherein the pure platinum barrier Schottky diode is prepared by depositing a TiW layer silicon wafer, and the substrate is an n+ monocrystalline silicon substrate; an n+ monocrystalline silicon substrate produces an n-epitaxial layer; forming PN junction by zone oxidation and ion implantation, and forming passivation layer by field oxidation; photoetching and etching the epitaxial layer exposing Si; the preparation of the schottky barrier front surface cleaning ensures that the surface of the silicon wafer is sufficiently clean and the surface of the silicon wafer without process defects is exposed.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06132243A (en) * | 1992-10-16 | 1994-05-13 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN107785251A (en) * | 2016-08-26 | 2018-03-09 | 英飞凌科技股份有限公司 | Formed using the barrier layer of heat treatment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4119446A (en) * | 1977-08-11 | 1978-10-10 | Motorola Inc. | Method for forming a guarded Schottky barrier diode by ion-implantation |
| JPH073870B2 (en) * | 1987-09-18 | 1995-01-18 | 日本電気株式会社 | Method for manufacturing semiconductor integrated circuit device |
| JPH07116588B2 (en) * | 1990-08-08 | 1995-12-13 | 信越化学工業株式会社 | Method for manufacturing transparent body of mask for X-ray lithography |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06132243A (en) * | 1992-10-16 | 1994-05-13 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN107785251A (en) * | 2016-08-26 | 2018-03-09 | 英飞凌科技股份有限公司 | Formed using the barrier layer of heat treatment |
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